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Anmol Purtycd9b8e52021-05-14 19:54:20 +05301<!---
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18
19A quick documentation of the Caravel memory map and operation
20---------------------------------------------------------------
21
22Caravel pinout:
23---------------
24
25 vddio 3.3V supply for all I/O and ESD
26 vssio Ground for all I/O and ESD
27 vdda 3.3V supply for management area
28 vssa Ground for management area
29 vccd 1.8V supply for management area
30 vssd Digital ground for management area
31
32 vdda1 3.3V supply for user area 1
33 vdda2 3.3V supply for user area 2
34 vssa1 Ground for user area 1
35 vssa2 Ground for user area 2
36 vccd1 1.8 supply for user area 1
37 vccd2 1.8 supply for user area 2
38 vssd1 Digital ground for user area 1
39 vssd2 Digital ground for user area 2
40
41 clock Master clock input
42 gpio 1 bit, mainly used for external LDO control of user power supply
43 mprj_io 32 bits general purpose programmable digital or analog I/O
44 resetb Master reset (sense inverted) input
45 flash_csb SPI flash controller chip select (sense inverted)
46 flash_clk SPI flash controller clock
47 flash_io0 SPI flash controller data out
48 flash_io1 SPI flash controller data in
49
50Special-use pins for the management SoC:
51----------------------------------------
52
53 On power-up, the "mprj_io" GPIO are under complete control of the managment
54 SoC. The first 8 user GPIO are special-purpose pads with dedicated functions
55 for the management SoC:
56
57 mprj_io[0] JTAG I/O
58 mprj_io[1] SDO, housekeeping SPI
59 mprj_io[2] SDI, housekeeping SPI
60 mprj_io[3] CSB, housekeeping SPI
61 mprj_io[4] SCK, housekeeping SPI
62 mprj_io[5] Rx, UART
63 mprj_io[6] Tx, UART
64 mprj_io[7] IRQ
65
66 The next 4 user GPIO are designed to be used with an SPI flash controller in
67 the user space. They allow the four pins to be overridden by the housekeeping
68 SPI to access the SPI flash in pass-through mode.
69
70 mprj_io[8] user flash CSB
71 mprj_io[9] user flash SCK
72 mprj_io[10] user flash IO0
73 mprj_io[11] user flash IO1
74
75 The last 2 GPIO pins can be used by the management SoC to drive the SPI flash
76 io2 and io3 pins for quad and DDR access, although they are set as inputs by
77 default and whenever the SPI flash is not in quad mode:
78
79 mprj_io[36] SPI flash io2
80 mprj_io[37] SPI flash io3
81
82 The user may additionally use any available GPIO for the SPI flash IO2 and IO3
83 lines; the pass-through mode only uses the basic 4-pin SPI mode.
84
85 All of the special-use pins are configured through a memory-mapped region. But
86 to avoid a large number of wires in the user space to reach all of the GPIO
87 pad controls, each user GPIO pad has a corresponding local control block. The
88 control block holds the configuration data for the corresponding pad. This
89 configuration data is a mirror of the data in the memory-mapped region, and is
90 loaded by a "transfer" bit in another memory-mapped register. In addition to
91 all of the static control bits for the GPIO, each block contains a single bit
92 that specifies whether that pad is under the control of the user or the management
93 area. All pins are configured from the management area. However, the configuration
94 of static control bits leaves three dynamic signals: input, output, and output
95 enable. One set of these three signals is available to the user when the pad is
96 under user control. The other set of these three signals is available to the
97 management SoC. Again, to reduce wiring, only the two pads for JTAG and the
98 housekeeping SDO have all three pins under control of the SoC; the remaining
99 pads have a single wire to the management SoC which is either an input wire
100 or an output wire, depending on how the control signals for the pad are set.
101
102 This setup gives a simplified view of the pad to the user: For digital
103 applications, the user can treat the pad as a simple bidirectional digital
104 pad with an output enable to switch between output and input functions.
105 The user can set the output enable line high or low for a static input or
106 output function. The user will also have access to the ESD-protected
107 pad connections for analog signals, and can connect to the VDDA domain
108 input digital signal if needed.
109
110Memory map:
111-----------
112
113 The Caravel memory map is as follows:
114
115 SRAM: 0000 0000
116
117 Flash: Config: 1000 0000
118
119 UART: Clock divider: 2000 0000
120 Data: 2000 0004
121 Enable 2000 0008
122
123 GPIO: Data: 2100 0000
124 Output enable: 2100 0004
125 Pullup 2100 0008
126 Pulldown 2100 000c
127
128 Counter 1: Config: 2200 0000
129 Value: 2200 0004
130 Data: 2200 0008
131
132 Counter 2: Config: 2300 0000
133 Value: 2300 0004
134 Data: 2300 0008
135
136 SPI master: Config: 2400 0000
137 Data: 2400 0004
138
139 Logic analyzer: Data 0: 2500 0000
140 Data 1: 2500 0004
141 Data 2: 2500 0008
142 Data 3: 2500 000c
143 Enable 0: 2500 0010
144 Enable 1: 2500 0014
145 Enable 2: 2500 0018
146 Enable 3: 2500 001c
147
148 Project ctrl: Data (L): 2600 0000
149 Data (H): 2600 0004
150 Transfer: 2600 0008
151 I/O Config: 2600 000c
152 to 2600 009c
153 Power Config: 2600 00a0
154 to 2600 0130
155
156 Flash ctrl: Config: 2D00 0000
157
158 System: PLL out: 2F00 0000
159 Trap out: 2F00 0004
160 IRQ7 source: 2F00 0008
161
162 User area base: 3000 0000
163
164 Crossbar: QSPI control 8000 0000
165 Storage area 9000 0000
166 Any slave 1 a000 0000
167 Any slave 2 b000 0000
168
169Project I/O Control:
170---------------------
171
172 Configuration bits per I/O (13 bits for each GPIO pad):
173 Global Default
174 Bits 12-10: digital mode (3 bits) 001
175 Bit 9: voltage trip point select 0
176 Bit 8: slow slew select 0
177 Bit 7: analog bus polarity 0
178 Bit 6: analog bus select 0
179 Bit 5: analog bus enable 0
180 Bit 4: IB mode select 0
181 Bit 3: input disable 0
182 Bit 2: holdover value 0
183 Bit 1: output disable 1
184 Bit 0: management control enable 1
185
186Default I/O modes:
187------------------
188 mprj_io[0] JTAG I/O 110 0 0 0 0 0 0 0 0 0 1
189 mprj_io[1] SDO, housekeeping SPI 110 0 0 0 0 0 0 0 0 0 1
190 all others: 001 0 0 0 0 0 0 0 0 1 1
191
192
193 Standard GPIO output configuration:
194 mprj_io[6] Tx, UART 110 0 0 0 0 0 0 1 0 0 1
195
196 Standard GPIO input configuration:
197 mprj_io[*] 001 0 0 0 0 0 0 0 0 1 1
198
199 Standard GPIO input configuration with pullup:
200 mprj_io[*] 010 0 0 0 0 0 0 0 0 1 1
201
202 Standard GPIO input configuration with pulldown:
203 mprj_io[*] 011 0 0 0 0 0 0 0 0 1 1
204
205 Specifically:
206 JTAG and SDO are set to output. The output enable configure bit
207 is a don't-care, since the output enable line is directly controlled
208 by the module (JTAG or housekeeping SPI, respectively).
209
210 All other I/O are set as input mode only, with output disabled.
211
212 Tx is set to input like the others; before enabling the UART
213 from a program in flash, the I/O must be set to an output configuration.
214
215 Note that the standard input configurations with pull-up and pull-down
216 require that "out" be set 1 or 0, respectively; since the I/O are
217 designed with minimal wiring, there is only one wire for input and
218 output, so the wire is used for input in these cases, and special
219 signal handling is done locally to set the value of "out" equal to
220 ~dm[0]. This is a (minor) restriction on the available I/O modes.
221
222 Other possible modes are open-drain (for I2C), weak drive strength
223 output (5k up + down), and analog mode (digital disabled)