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diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v new file mode 100644 index 0000000..eae4ab1 --- /dev/null +++ b/verilog/rtl/user_proj_example.v
@@ -0,0 +1,95 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_proj_example + * + * This is an example of a (trivially simple) user project, + * showing how the user project can connect to the logic + * analyzer, the wishbone bus, and the I/O pads. + * + * This project generates an integer count, which is output + * on the user area GPIO pads (digital output only). The + * wishbone connection allows the project to be controlled + * (start and stop) from the management SoC program. + * + * See the testbenches in directory "mprj_counter" for the + * example programs that drive this user project. The three + * testbenches are "io_ports", "la_test1", and "la_test2". + * + *------------------------------------------------------------- + */ + +module user_proj_example #( + parameter BITS = 32 +)( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + + // IOs + input in, + inout out +); + + avsdbgp_3v3_sky130_v2 #( + .BITS(BITS) + ) avsdbgp_3v3_sky130_v2 ( + .EN(in), + .VBGP(out) + ); + +endmodule + +module avsdbgp_3v3_sky130_v2 #( + parameter BITS = 32 +)( + + input EN, + output VBGP + +); + + reg real VBGP; + + initial begin + if (EN == 1'b1) begin + VBGP <= 1.19; + end else begin + VBGP <= 0.0; + end + end + + always @(EN) begin + if (EN == 1'b1) begin + VBGP <= 1.19; + end else begin + VBGP <= 0.0; + end + end + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v new file mode 100644 index 0000000..7c42f8f --- /dev/null +++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,108 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_project_wrapper + * + * This wrapper enumerates all of the pins available to the + * user for the user project. + * + * An example user project is provided in this wrapper. The + * example should be removed and replaced with the actual + * user project. + * + *------------------------------------------------------------- + */ + +module user_project_wrapper #( + parameter BITS = 32 +) ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + input gpio, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb, + + // Analog (direct connection to GPIO pad---use with caution) + // Note that analog I/O is not available on the 7 lowest-numbered + // GPIO pads, and so the analog_io indexing is offset from the + // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io). + inout [`MPRJ_IO_PADS-10:0] analog_io, + + // Independent clock (on independent integer divider) + input user_clock2, + + // User maskable interrupt signals + output [2:0] user_irq +); + +/*--------------------------------------*/ +/* User project is instantiated here */ +/*--------------------------------------*/ + + +user_proj_example mprj ( + `ifdef USE_POWER_PINS + .vdda1(vdda1), // User area 1 3.3V power + .vdda2(vdda2), // User area 2 3.3V power + .vssa1(vssa1), // User area 1 analog ground + .vssa2(vssa2), // User area 2 analog ground + .vccd1(vccd1), // User area 1 1.8V power + .vccd2(vccd2), // User area 2 1.8V power + .vssd1(vssd1), // User area 1 digital ground + .vssd2(vssd2), // User area 2 digital ground + `endif + + + // IOs + .in(io_in[23]), + .out(io_out[16]) + + ); + +endmodule // user_project_wrapper + +`default_nettype wire