blob: 6acab2178dc4764bb1a79f51afcf4571cddfec3d [file] [log] [blame]
---
project:
description: "General Purpose Bandgap Reference"
foundry: "SkyWater"
git_url: "https://github.com/vsdip/avsdbgp_3v3_sky130_v2"
organization: "VLSI System Design Corp. Pvt. Ltd."
organization_url: "https://www.vlsisystemdesign.com/"
owner: "Anmol Purty"
process: "SKY130"
project_name: "avsdbgp_3v3_sky130_v2"
project_id: "00000000"
tags:
- "Open MPW"
- "Test Harness"
category: "Test Harness"
top_level_netlist: "caravel/verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "docs/source/_static/caravel_harness.png"