Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-020
/
e12fd62d75f3dc1c5f881f2a00525d35b6fa4d7f
commit
e12fd62d75f3dc1c5f881f2a00525d35b6fa4d7f
[
log
]
[
tgz
]
author
Baburaj <teche.raj2019@gmail.com>
Mon May 31 15:42:01 2021 +0530
committer
Baburaj <teche.raj2019@gmail.com>
Mon May 31 15:42:01 2021 +0530
tree
00c676d32381dfe6efe6b26b265c608ca775ba8c
parent
6e4866b1a2d547f4353e9f3e98abbbcb1e397d55
[
diff
]
Instantiated PWM Module
verilog/rtl/user_proj_example.v
[
diff
]
1 file changed
tree: 00c676d32381dfe6efe6b26b265c608ca775ba8c
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.