)]}'
{
  "commit": "e12fd62d75f3dc1c5f881f2a00525d35b6fa4d7f",
  "tree": "00c676d32381dfe6efe6b26b265c608ca775ba8c",
  "parents": [
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  "author": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Mon May 31 15:42:01 2021 +0530"
  },
  "committer": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Mon May 31 15:42:01 2021 +0530"
  },
  "message": "Instantiated PWM Module\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
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}