zeeshanrafique23 | dcd1995 | 2021-06-01 16:45:51 +0500 | [diff] [blame] | 1 | |
| 2 | module spi_top( |
| 3 | |
| 4 | input clk_i, |
| 5 | input rst_ni, |
| 6 | |
| 7 | input tlul_pkg::tl_h2d_t tl_i, |
| 8 | output tlul_pkg::tl_d2h_t tl_o, |
| 9 | |
| 10 | // SPI signals |
| 11 | output intr_rx_o, |
| 12 | output intr_tx_o, |
| 13 | output [`SPI_SS_NB-1:0] ss_o, |
| 14 | output sclk_o, |
| 15 | output sd_o, |
| 16 | output sd_oe, |
| 17 | input sd_i |
| 18 | |
| 19 | ); |
| 20 | |
| 21 | localparam int AW = 8; |
| 22 | localparam int DW = 32; |
| 23 | |
| 24 | logic re; |
| 25 | logic we; |
| 26 | logic [7:0] addr; |
| 27 | logic [31:0] wdata; |
| 28 | logic [3:0] be; |
| 29 | logic [31:0] rdata; |
| 30 | logic err; |
| 31 | |
| 32 | spi_core spi_host( |
| 33 | // tlul signals |
| 34 | .clk_i, |
| 35 | .rst_ni, |
| 36 | .addr_i (addr), |
| 37 | .wdata_i (wdata), |
| 38 | .rdata_o (rdata), |
| 39 | .be_i (be), |
| 40 | .we_i (we), |
| 41 | .re_i (re), |
| 42 | .error_o (err), |
| 43 | |
| 44 | .intr_rx_o (intr_rx_o), |
| 45 | .intr_tx_o (intr_tx_o), |
| 46 | |
| 47 | // SPI signals |
| 48 | .ss_o (ss_o), // slave select |
| 49 | .sclk_o (sclk_o), // serial clock |
| 50 | .sd_o (sd_o), // master out slave in |
| 51 | .sd_oe (sd_oe), |
| 52 | .sd_i (sd_i) // master in slave out |
| 53 | ); |
| 54 | |
| 55 | |
| 56 | tlul_adapter_reg #( |
| 57 | .RegAw(AW), |
| 58 | .RegDw(DW) |
| 59 | ) u_reg_if ( |
| 60 | .clk_i, |
| 61 | .rst_ni, |
| 62 | |
| 63 | .tl_i (tl_i), |
| 64 | .tl_o (tl_o), |
| 65 | |
| 66 | .we_o (we), |
| 67 | .re_o (re), |
| 68 | .addr_o (addr), |
| 69 | .wdata_o (wdata), |
| 70 | .be_o (be), |
| 71 | .rdata_i (rdata), |
| 72 | .error_i (err) |
| 73 | ); |
| 74 | |
| 75 | endmodule |