commit	4b10c63442b7ce14d6ad2c6c97598389e7e74226	[log] [tgz]
author	nguyendao-uom <nguyen.dao@manchester.ac.uk>	Thu Nov 25 11:23:15 2021 +0000
committer	nguyendao-uom <nguyen.dao@manchester.ac.uk>	Thu Nov 25 11:23:15 2021 +0000
tree	fcca37aac1bb3fb91483fc0d19645ece872941b0
parent	c5da9e9885e361d05dee2aa6303a69fc26423c8e [diff]

add rtl/gds/lef

docs/source/fuserisc_ver2.png[Added - diff]
gds/eFPGA_CPU_top.gds[Added - diff]
info.yaml[Added - diff]
lef/eFPGA_CPU_top.lef[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
setenv.src[Added - diff]
verilog/rtl/Config.v[Added - diff]
verilog/rtl/ConfigFSM.v[Added - diff]
verilog/rtl/Config_access.v[Added - diff]
verilog/rtl/DSP_bot_ConfigMem.v[Added - diff]
verilog/rtl/DSP_bot_switch_matrix.v[Added - diff]
verilog/rtl/DSP_bot_tile.v[Added - diff]
verilog/rtl/DSP_tile.v[Added - diff]
verilog/rtl/DSP_top_ConfigMem.v[Added - diff]
verilog/rtl/DSP_top_switch_matrix.v[Added - diff]
verilog/rtl/DSP_top_tile.v[Added - diff]
verilog/rtl/E_CPU_IO_ConfigMem.v[Added - diff]
verilog/rtl/E_CPU_IO_bot_ConfigMem.v[Added - diff]
verilog/rtl/E_CPU_IO_bot_switch_matrix.v[Added - diff]
verilog/rtl/E_CPU_IO_bot_tile.v[Added - diff]
verilog/rtl/E_CPU_IO_switch_matrix.v[Added - diff]
verilog/rtl/E_CPU_IO_tile.v[Added - diff]
verilog/rtl/Frame_Data_Reg_Pack.v[Added - diff]
verilog/rtl/Frame_Select_Pack.v[Added - diff]
verilog/rtl/IO_1_bidirectional_frame_config_pass.v[Added - diff]
verilog/rtl/InPass4_frame_config_mux.v[Added - diff]
verilog/rtl/LUT4AB_ConfigMem.v[Added - diff]
verilog/rtl/LUT4AB_switch_matrix.v[Added - diff]
verilog/rtl/LUT4AB_tile.v[Added - diff]
verilog/rtl/LUT4c_frame_config_dffesr.v[Added - diff]
verilog/rtl/MULADD.v[Added - diff]
verilog/rtl/MUX8LUT_frame_config_mux.v[Added - diff]
verilog/rtl/N_term_DSP_switch_matrix.v[Added - diff]
verilog/rtl/N_term_DSP_tile.v[Added - diff]
verilog/rtl/N_term_RAM_IO_switch_matrix.v[Added - diff]
verilog/rtl/N_term_RAM_IO_tile.v[Added - diff]
verilog/rtl/N_term_single2_switch_matrix.v[Added - diff]
verilog/rtl/N_term_single2_tile.v[Added - diff]
verilog/rtl/N_term_single_switch_matrix.v[Added - diff]
verilog/rtl/N_term_single_tile.v[Added - diff]
verilog/rtl/OutPass4_frame_config_mux.v[Added - diff]
verilog/rtl/RAM_IO_ConfigMem.v[Added - diff]
verilog/rtl/RAM_IO_switch_matrix.v[Added - diff]
verilog/rtl/RAM_IO_tile.v[Added - diff]
verilog/rtl/RegFile_32x4.v[Added - diff]
verilog/rtl/RegFile_ConfigMem.v[Added - diff]
verilog/rtl/RegFile_switch_matrix.v[Added - diff]
verilog/rtl/RegFile_tile.v[Added - diff]
verilog/rtl/S_term_DSP_switch_matrix.v[Added - diff]
verilog/rtl/S_term_DSP_tile.v[Added - diff]
verilog/rtl/S_term_RAM_IO_switch_matrix.v[Added - diff]
verilog/rtl/S_term_RAM_IO_tile.v[Added - diff]
verilog/rtl/S_term_single2_switch_matrix.v[Added - diff]
verilog/rtl/S_term_single2_tile.v[Added - diff]
verilog/rtl/S_term_single_switch_matrix.v[Added - diff]
verilog/rtl/S_term_single_tile.v[Added - diff]
verilog/rtl/W_CPU_IO_ConfigMem.v[Added - diff]
verilog/rtl/W_CPU_IO_bot_ConfigMem.v[Added - diff]
verilog/rtl/W_CPU_IO_bot_switch_matrix.v[Added - diff]
verilog/rtl/W_CPU_IO_bot_tile.v[Added - diff]
verilog/rtl/W_CPU_IO_switch_matrix.v[Added - diff]
verilog/rtl/W_CPU_IO_tile.v[Added - diff]
verilog/rtl/W_IO_ConfigMem.v[Added - diff]
verilog/rtl/W_IO_switch_matrix.v[Added - diff]
verilog/rtl/W_IO_tile.v[Added - diff]
verilog/rtl/arbiter.v[Added - diff]
verilog/rtl/axi_uart.v[Added - diff]
verilog/rtl/bitbang.v[Added - diff]
verilog/rtl/config_UART.v[Added - diff]
verilog/rtl/eFPGA_CPU_top.synthesis.v[Added - diff]
verilog/rtl/eFPGA_CPU_top.v[Added - diff]
verilog/rtl/fabric_DSP_tile.v[Added - diff]
verilog/rtl/forte_soc_top.v[Added - diff]
verilog/rtl/ibex_alu.v[Added - diff]
verilog/rtl/ibex_compressed_decoder.v[Added - diff]
verilog/rtl/ibex_controller.v[Added - diff]
verilog/rtl/ibex_core.v[Added - diff]
verilog/rtl/ibex_cs_registers.v[Added - diff]
verilog/rtl/ibex_decoder.v[Added - diff]
verilog/rtl/ibex_defines.sv[Added - diff]
verilog/rtl/ibex_defines.v[Added - diff]
verilog/rtl/ibex_eFPGA.v[Added - diff]
verilog/rtl/ibex_ex_block.v[Added - diff]
verilog/rtl/ibex_fetch_fifo.v[Added - diff]
verilog/rtl/ibex_id_stage.v[Added - diff]
verilog/rtl/ibex_if_stage.v[Added - diff]
verilog/rtl/ibex_int_controller.v[Added - diff]
verilog/rtl/ibex_load_store_unit.v[Added - diff]
verilog/rtl/ibex_multdiv_fast.v[Added - diff]
verilog/rtl/ibex_multdiv_slow.v[Added - diff]
verilog/rtl/ibex_prefetch_buffer.v[Added - diff]
verilog/rtl/ibex_register_file.v[Added - diff]
verilog/rtl/inter.v[Added - diff]
verilog/rtl/inter_read.v[Added - diff]
verilog/rtl/models_pack.v[Added - diff]
verilog/rtl/peripheral.v[Added - diff]
verilog/rtl/prim_clock_gating.v[Added - diff]
verilog/rtl/ram.v[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/uart.v[Added - diff]
verilog/rtl/uart_rx.v[Added - diff]
verilog/rtl/uart_to_mem.v[Added - diff]
verilog/rtl/uart_tx.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

106 files changed

tree: fcca37aac1bb3fb91483fc0d19645ece872941b0

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.