Merge pull request #10 from mattvenn/patch-1

typo

docs/source/index.rst

diff --git a/docs/source/index.rst b/docs/source/index.rst
index 76f0c39..08244b7 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -131,7 +131,7 @@
 -  The LA probes for supplying an optional reset and clock signals and
    for setting an initial value for the count register.
 
--  The wishbeone port for reading/writing the count value through the
+-  The wishbone port for reading/writing the count value through the
    management SoC.
 
 Refer to `user\_project\_wrapper <verilog/rtl/user_project_wrapper.v>`__