commit	f95aba73858365a121e7489af4b1d47966b898eb	[log] [tgz]
author	Abdullah YILDIZ <abdullahyildiz@users.noreply.github.com>	Mon Jun 14 10:03:39 2021 +0300
committer	GitHub <noreply@github.com>	Mon Jun 14 10:03:39 2021 +0300
tree	b114d0a7d3f6a909ac78c7523b1e77281623da8d
parent	05fa12101358e59a8c0b669730853d20f19affa2 [diff]

tree: b114d0a7d3f6a909ac78c7523b1e77281623da8d

README.md

YONGA-LZ4 Decoder

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

export PDK_ROOT=<pdk-installation-path>
export OPENLANE_ROOT=<openlane-installation-path>
cd $UPRJ_ROOT
export CARAVEL_ROOT=$(pwd)/caravel

This test is meant to verify that we can read and write to the YONGA-LZ4 Decoder through the WISHBONE port. The firmware first writes a compressed data stream to input FIFO of the YONGA-LZ4 Decoder, then reads decoded data stream from output FIFO of the YONGA-LZ4 Decoder.

To run RTL simulation,

cd $UPRJ_ROOT
make verify-wb_test

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

[x] The project repo adheres to the same directory structure in this repo
[x] The project repo contain info.yaml at the project root
[x] Top level macro is named user_project_wrapper
[x] Full Chip Simulation passes for RTL and GL (gate-level)
[x] The hardened Macros are LVS and DRC clean
[x] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
[x] XOR check passes with zero total difference.
[x] Openlane summary reports are retained under ./signoff/