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foss-eda-tools / third_party / shuttle / sky130 / mpw-002 / slot-010 / 05fa12101358e59a8c0b669730853d20f19affa2
commit05fa12101358e59a8c0b669730853d20f19affa2[log] [tgz]
authorAbdullah YILDIZ <abdullahyildiz@users.noreply.github.com>Mon Jun 14 09:40:45 2021 +0300
committerGitHub <noreply@github.com>Mon Jun 14 09:40:45 2021 +0300
treec885297f49e13bfabbfb779c17c87646405df249
parent634684b5c3d90d6f1c3cb2c131862a7cc921c1b0 [diff]
Update README.md
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  8. openlane/
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  16. LICENSE
  17. Makefile
  18. README.md
README.md

YONGA-LZ4 Decoder

License UPRJ_CI Caravel Build

Table of contents

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Setup

export PDK_ROOT=<pdk-installation-path>
export OPENLANE_ROOT=<openlane-installation-path>
cd $UPRJ_ROOT
export CARAVEL_ROOT=$(pwd)/caravel

Running Simulation

WISHBONE Test

  • This test is meant to verify that we can read and write to the YONGA-LZ4 Decoder through the WISHBONE port. The firmware first writes a compressed data stream to input FIFO of the YONGA-LZ4 Decoder, then reads decoded data stream from output FIFO of the YONGA-LZ4 Decoder.

To run RTL simulation,

cd $UPRJ_ROOT
make verify-wb_test

Checklist for Open-MPW Two Submission

  • [x] The project repo adheres to the same directory structure in this repo
  • [x] The project repo contain info.yaml at the project root
  • [x] Top level macro is named user_project_wrapper
  • [x] Full Chip Simulation passes for RTL and GL (gate-level)
  • [x] The hardened Macros are LVS and DRC clean
  • [x] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
  • [x] XOR check passes with zero total difference.
  • [x] Openlane summary reports are retained under ./signoff/