Update config.tcl
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
old mode 100755
new mode 100644
index 4ea25c6..a0c3381
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -21,12 +21,12 @@
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
-set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
+set ::env(CLOCK_PERIOD) "20"
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
+set ::env(DIE_AREA) "0 0 1000 1000"
set ::env(DESIGN_IS_CORE) 0
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
@@ -34,8 +34,10 @@
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.5
+
+set ::env(DIODE_INSERTION_STRATEGY) "2"
# If you're going to use multiple power domains, then keep this disabled.
set ::env(RUN_CVC) 0
