| commit | b6122c80e076e3e3c9912cee67bca169d316c2b9 | [log] [tgz] |
|---|---|---|
| author | abdullahyildiz <abdullah.yildiz@yongatek.com> | Mon Jun 07 20:49:11 2021 +0300 |
| committer | abdullahyildiz <abdullah.yildiz@yongatek.com> | Mon Jun 07 20:49:11 2021 +0300 |
| tree | a32b0f15ec53793676d242e166b4e851fb86bdaf | |
| parent | 78b96fb06eb5656dc9c27a0bbfe1997d06098115 [diff] |
Update Makefile
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index d87238f..81f6ada 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus +PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus wb_test all: ${PATTERNS} for i in ${PATTERNS}; do \