Update user_proj_example.v

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index d78bbe8..b313fd5 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -95,8 +95,11 @@
 assign la_data_out = {{(88){1'b0}}, decompressed_data1,{(32){1'b0}}}; 
 assign compressed_data1 = la_data_in[7:0];
 
-assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
-assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+// assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+// assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+
+assign clk = wb_clk_i;
+assign rst = wb_rst_i;
 
 assign irq = 3'b000;