Create list_ch04_11_mod_m_counter.v

verilog/rtl/list_ch04_11_mod_m_counter.v

diff --git a/verilog/rtl/list_ch04_11_mod_m_counter.v b/verilog/rtl/list_ch04_11_mod_m_counter.v
new file mode 100644
index 0000000..6b7236c
--- /dev/null
+++ b/verilog/rtl/list_ch04_11_mod_m_counter.v
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+// Listing 4.11

+module mod_m_counter

+   #(

+    parameter N=4, // number of bits in counter

+              M=10 // mod-M

+   )

+   (

+    input wire clk, reset,

+    output wire max_tick,

+    output wire [N-1:0] q

+   );

+

+   //signal declaration

+   reg [N-1:0] r_reg;

+   wire [N-1:0] r_next;

+

+   // body

+   // register

+   always @(posedge clk, posedge reset)

+      if (reset)

+         r_reg <= 0;

+      else

+         r_reg <= r_next;

+

+   // next-state logic

+   assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1;

+   // output logic

+   assign q = r_reg;

+   assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0;

+

+endmodule
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