final gds & signoff results
diff --git a/checks/klayout_drc_total.txt b/checks/klayout_drc_total.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/checks/klayout_drc_total.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/checks/met_min_ca_density_check.xml b/checks/met_min_ca_density_check.xml
new file mode 100644
index 0000000..a7ec35a
--- /dev/null
+++ b/checks/met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/klayout_drc_checks/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/checks/met_min_ca_density_total.txt b/checks/met_min_ca_density_total.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/checks/met_min_ca_density_total.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/checks/offgrid_check.xml b/checks/offgrid_check.xml
new file mode 100644
index 0000000..2c3bbba
--- /dev/null
+++ b/checks/offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/klayout_drc_checks/offgrid.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/checks/offgrid_total.txt b/checks/offgrid_total.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/checks/offgrid_total.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/checks/user_project_wrapper.magic.drc.mag b/checks/user_project_wrapper.magic.drc.mag
index f5e3ece..3ad5076 100644
--- a/checks/user_project_wrapper.magic.drc.mag
+++ b/checks/user_project_wrapper.magic.drc.mag
Binary files differ
diff --git a/checks/user_project_wrapper.xor.gds b/checks/user_project_wrapper.xor.gds
index 7a4be40..0e38ebb 100644
--- a/checks/user_project_wrapper.xor.gds
+++ b/checks/user_project_wrapper.xor.gds
Binary files differ
diff --git a/checks/user_project_wrapper.xor.gds.png b/checks/user_project_wrapper.xor.gds.png
deleted file mode 100644
index cd63482..0000000
--- a/checks/user_project_wrapper.xor.gds.png
+++ /dev/null
Binary files differ
diff --git a/checks/user_project_wrapper.xor.xml b/checks/user_project_wrapper.xor.xml
deleted file mode 100644
index 0ba8947..0000000
--- a/checks/user_project_wrapper.xor.xml
+++ /dev/null
@@ -1,63 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<report-database>
- <description>XOR /home/edaman/Desktop/openlane_workspace/caravel_yonga-lz4-decoder-efabless/checks/user_project_wrapper_empty_erased.gds vs. /home/edaman/Desktop/openlane_workspace/caravel_yonga-lz4-decoder-efabless/checks/user_project_wrapper_erased.gds</description>
- <original-file/>
- <generator>drc: script='/usr/local/bin/xor_checks/xor.drc'</generator>
- <top-cell>user_project_wrapper</top-cell>
- <tags>
- </tags>
- <categories>
- <category>
- <name>235/4</name>
- <description>XOR results for layer 235/4 </description>
- <categories>
- </categories>
- </category>
- <category>
- <name>69/20</name>
- <description>XOR results for layer 69/20 </description>
- <categories>
- </categories>
- </category>
- <category>
- <name>70/20</name>
- <description>XOR results for layer 70/20 </description>
- <categories>
- </categories>
- </category>
- <category>
- <name>71/20</name>
- <description>XOR results for layer 71/20 </description>
- <categories>
- </categories>
- </category>
- <category>
- <name>71/44</name>
- <description>XOR results for layer 71/44 </description>
- <categories>
- </categories>
- </category>
- <category>
- <name>72/20</name>
- <description>XOR results for layer 72/20 </description>
- <categories>
- </categories>
- </category>
- <category>
- <name>81/14</name>
- <description>XOR results for layer 81/14 </description>
- <categories>
- </categories>
- </category>
- </categories>
- <cells>
- <cell>
- <name>user_project_wrapper</name>
- <variant/>
- <references>
- </references>
- </cell>
- </cells>
- <items>
- </items>
-</report-database>
diff --git a/checks/user_project_wrapper_empty_erased.gds b/checks/user_project_wrapper_empty_erased.gds
index 4782b1f..bf2a69f 100644
--- a/checks/user_project_wrapper_empty_erased.gds
+++ b/checks/user_project_wrapper_empty_erased.gds
Binary files differ
diff --git a/checks/user_project_wrapper_erased.gds b/checks/user_project_wrapper_erased.gds
index 1965843..fe5b601 100644
--- a/checks/user_project_wrapper_erased.gds
+++ b/checks/user_project_wrapper_erased.gds
Binary files differ
diff --git a/checks/user_project_wrapper_klayout_drc.xml b/checks/user_project_wrapper_klayout_drc.xml
new file mode 100644
index 0000000..94bf212
--- /dev/null
+++ b/checks/user_project_wrapper_klayout_drc.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/drc_checks/../tech-files/sky130A_mr.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be mnually merge if less : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1b/c</name>
+ <description>licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. m2 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via2 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via2 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/gds/.magicrc b/gds/.magicrc
new file mode 100644
index 0000000..67cdbf8
--- /dev/null
+++ b/gds/.magicrc
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+ path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
new file mode 100644
index 0000000..b2f9746
--- /dev/null
+++ b/gds/caravel.gds.gz
Binary files differ
diff --git a/gds/caravel_0002000a.gds.gz.00.split b/gds/caravel_0002000a.gds.gz.00.split
new file mode 100644
index 0000000..8a9e16a
--- /dev/null
+++ b/gds/caravel_0002000a.gds.gz.00.split
Binary files differ
diff --git a/gds/caravel_0002000a.gds.gz.01.split b/gds/caravel_0002000a.gds.gz.01.split
new file mode 100644
index 0000000..edad9fb
--- /dev/null
+++ b/gds/caravel_0002000a.gds.gz.01.split
Binary files differ
diff --git a/gds/caravel_0002000a.gds.gz.02.split b/gds/caravel_0002000a.gds.gz.02.split
new file mode 100644
index 0000000..a18f0ee
--- /dev/null
+++ b/gds/caravel_0002000a.gds.gz.02.split
Binary files differ
diff --git a/gds/caravel_0002000a.gds.gz.03.split b/gds/caravel_0002000a.gds.gz.03.split
new file mode 100644
index 0000000..1be335a
--- /dev/null
+++ b/gds/caravel_0002000a.gds.gz.03.split
Binary files differ
diff --git a/gds/caravel_0002000a.gds.gz.04.split b/gds/caravel_0002000a.gds.gz.04.split
new file mode 100644
index 0000000..f708018
--- /dev/null
+++ b/gds/caravel_0002000a.gds.gz.04.split
Binary files differ
diff --git a/gds/caravel_0002000a.gds.gz.05.split b/gds/caravel_0002000a.gds.gz.05.split
new file mode 100644
index 0000000..44b9557
--- /dev/null
+++ b/gds/caravel_0002000a.gds.gz.05.split
Binary files differ
diff --git a/gds/caravel_0002000a_fill_pattern.gds.gz.00.split b/gds/caravel_0002000a_fill_pattern.gds.gz.00.split
new file mode 100644
index 0000000..80043b6
--- /dev/null
+++ b/gds/caravel_0002000a_fill_pattern.gds.gz.00.split
Binary files differ
diff --git a/gds/caravel_0002000a_fill_pattern.gds.gz.01.split b/gds/caravel_0002000a_fill_pattern.gds.gz.01.split
new file mode 100644
index 0000000..6ee8aea
--- /dev/null
+++ b/gds/caravel_0002000a_fill_pattern.gds.gz.01.split
Binary files differ
diff --git a/gds/caravel_0002000a_fill_pattern.gds.gz.02.split b/gds/caravel_0002000a_fill_pattern.gds.gz.02.split
new file mode 100644
index 0000000..765a6bd
--- /dev/null
+++ b/gds/caravel_0002000a_fill_pattern.gds.gz.02.split
Binary files differ
diff --git a/gds/caravel_0002000a_fill_pattern.gds.gz.03.split b/gds/caravel_0002000a_fill_pattern.gds.gz.03.split
new file mode 100644
index 0000000..23f7fd0
--- /dev/null
+++ b/gds/caravel_0002000a_fill_pattern.gds.gz.03.split
Binary files differ
diff --git a/gds/caravel_0002000a_fill_pattern.gds.gz.04.split b/gds/caravel_0002000a_fill_pattern.gds.gz.04.split
new file mode 100644
index 0000000..0043a9b
--- /dev/null
+++ b/gds/caravel_0002000a_fill_pattern.gds.gz.04.split
Binary files differ
diff --git a/gds/caravel_0002000a_fill_pattern.gds.gz.05.split b/gds/caravel_0002000a_fill_pattern.gds.gz.05.split
new file mode 100644
index 0000000..155cc25
--- /dev/null
+++ b/gds/caravel_0002000a_fill_pattern.gds.gz.05.split
Binary files differ
diff --git a/gds/user_id_prog_zero.gds.gz b/gds/user_id_prog_zero.gds.gz
new file mode 100644
index 0000000..fd7f8c8
--- /dev/null
+++ b/gds/user_id_prog_zero.gds.gz
Binary files differ
diff --git a/gds/user_id_programming.gds.gz b/gds/user_id_programming.gds.gz
new file mode 100644
index 0000000..f50983d
--- /dev/null
+++ b/gds/user_id_programming.gds.gz
Binary files differ
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index a6a5c4d..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
deleted file mode 100644
index 7ed7685..0000000
--- a/gds/user_proj_example.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index 6f1c162..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 5e816f0..29ccdbb 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/info.yaml b/info.yaml
index 51e3cb4..ae0f8f3 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,20 +1,20 @@
----
project:
- description: "An implementation of the decoder of the popular LZ4 compression algorithm."
- foundry: "SkyWater"
- git_url: "https://github.com/yongatek/caravel_yonga-lz4-decoder.git"
- organization: "Yonga Technology Microelectronics R&D"
- organization_url: "https://yongatek.com/"
- owner: "Rifat Demircioglu"
- process: "SKY130"
- project_name: "Caravel"
- project_id: "00000000"
+ category: Test Harness
+ cover_image: docs/logo.png
+ description: An implementation of the decoder of the popular LZ4 compression algorithm.
+ foundry: SkyWater
+ git_url: https://github.com/yongatek/caravel_yonga-lz4-decoder.git
+ organization: Yonga Technology Microelectronics R&D
+ organization_url: https://yongatek.com/
+ owner: Rifat Demircioglu
+ process: SKY130
+ project_id: 0002000a
+ project_name: Caravel
+ shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-010.git
tags:
- - "Open MPW"
- - "Test Harness"
- - "LZ4"
- category: "Test Harness"
- top_level_netlist: "caravel/verilog/gl/caravel.v"
- user_level_netlist: "verilog/gl/user_project_wrapper.v"
- version: "1.00"
- cover_image: "docs/logo.png"
+ - Open MPW
+ - Test Harness
+ - LZ4
+ top_level_netlist: caravel/verilog/gl/caravel.v
+ user_level_netlist: verilog/gl/user_project_wrapper.v
+ version: '1.00'
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 100644
index 0000000..12328c6
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1,97 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+ path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+addpath ../subcells/simple_por/mag
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/compose_final.tcl b/mag/compose_final.tcl
new file mode 100644
index 0000000..13e1e4d
--- /dev/null
+++ b/mag/compose_final.tcl
@@ -0,0 +1,28 @@
+#!/bin/env wish
+drc off
+random seed 131082
+load caravel -dereference
+property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/gds/caravel.gds
+property GDS_START 0
+select top cell
+set bbox [box values]
+load caravel_0002000a_fill_pattern -quiet
+snap internal
+box values {*}$bbox
+paint comment
+property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/gds/caravel_0002000a_fill_pattern.gds
+property GDS_START 0
+property FIXED_BBOX "$bbox"
+load caravel_0002000a -quiet
+box values 0 0 0 0
+box position 6um 6um
+getcell caravel child 0 0
+getcell caravel_0002000a_fill_pattern child 0 0
+box position 0 0
+getcell advSeal_6um_gen
+puts stdout "Writing final GDS. . . "
+flush stdout
+gds undefined allow
+cif *hier write disable
+gds write /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/gds/caravel_0002000a.gds
+quit -noprompt
diff --git a/mag/mag2gds_caravel.tcl b/mag/mag2gds_caravel.tcl
new file mode 100644
index 0000000..684b88a
--- /dev/null
+++ b/mag/mag2gds_caravel.tcl
@@ -0,0 +1 @@
+ random seed 131082; drc off; crashbackups stop; gds readonly true; gds rescale false; cif *hier write disable; cif *array write disable; gds read /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/gds/user_project_wrapper.gds; load caravel -dereference; cellname list filepath user_id_programming /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/mag; cellname list filepath user_id_textblock /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/mag; flush user_id_programming; flush user_id_textblock; select top cell; gds write /mnt/shuttles/shuttle/mpw-two/slot-010/yonga-lz4_decoder/gds/caravel.gds; exit;
diff --git a/mag/user_id_programming.mag b/mag/user_id_programming.mag
new file mode 100644
index 0000000..12006b5
--- /dev/null
+++ b/mag/user_id_programming.mag
@@ -0,0 +1,3159 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606755340
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1961 3553 1995 3587
+rect 2697 3553 2731 3587
+rect 3157 3553 3191 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< metal1 >>
+rect 1104 6010 5980 6032
+rect 1104 5958 2607 6010
+rect 2659 5958 2671 6010
+rect 2723 5958 2735 6010
+rect 2787 5958 2799 6010
+rect 2851 5958 4232 6010
+rect 4284 5958 4296 6010
+rect 4348 5958 4360 6010
+rect 4412 5958 4424 6010
+rect 4476 5958 5980 6010
+rect 1104 5936 5980 5958
+rect 1104 5466 5980 5488
+rect 1104 5414 1794 5466
+rect 1846 5414 1858 5466
+rect 1910 5414 1922 5466
+rect 1974 5414 1986 5466
+rect 2038 5414 3420 5466
+rect 3472 5414 3484 5466
+rect 3536 5414 3548 5466
+rect 3600 5414 3612 5466
+rect 3664 5414 5045 5466
+rect 5097 5414 5109 5466
+rect 5161 5414 5173 5466
+rect 5225 5414 5237 5466
+rect 5289 5414 5980 5466
+rect 1104 5392 5980 5414
+rect 4062 5108 4068 5160
+rect 4120 5148 4126 5160
+rect 4157 5148 4215 5157
+rect 4341 5151 4399 5157
+rect 4341 5148 4353 5151
+rect 4120 5120 4353 5148
+rect 4120 5108 4126 5120
+rect 4157 5111 4215 5120
+rect 4341 5117 4353 5120
+rect 4387 5117 4399 5151
+rect 4341 5111 4399 5117
+rect 4614 5108 4620 5160
+rect 4672 5148 4678 5160
+rect 5077 5148 5135 5157
+rect 5261 5151 5319 5157
+rect 5261 5148 5273 5151
+rect 4672 5120 5273 5148
+rect 4672 5108 4678 5120
+rect 5077 5111 5135 5120
+rect 5261 5117 5273 5120
+rect 5307 5117 5319 5151
+rect 5261 5111 5319 5117
+rect 1104 4922 5980 4944
+rect 1104 4870 2607 4922
+rect 2659 4870 2671 4922
+rect 2723 4870 2735 4922
+rect 2787 4870 2799 4922
+rect 2851 4870 4232 4922
+rect 4284 4870 4296 4922
+rect 4348 4870 4360 4922
+rect 4412 4870 4424 4922
+rect 4476 4870 5980 4922
+rect 1104 4848 5980 4870
+rect 1949 4672 2007 4681
+rect 2133 4675 2191 4681
+rect 2133 4672 2145 4675
+rect 1949 4644 2145 4672
+rect 1949 4635 2007 4644
+rect 2133 4641 2145 4644
+rect 2179 4672 2191 4675
+rect 2958 4672 2964 4684
+rect 2179 4644 2964 4672
+rect 2179 4641 2191 4644
+rect 2133 4635 2191 4641
+rect 2958 4632 2964 4644
+rect 3016 4632 3022 4684
+rect 3050 4672 3114 4684
+rect 3234 4672 3240 4684
+rect 3050 4644 3240 4672
+rect 3050 4632 3114 4644
+rect 3234 4632 3240 4644
+rect 3292 4632 3298 4684
+rect 3418 4672 3482 4684
+rect 3602 4675 3666 4684
+rect 3602 4672 3617 4675
+rect 3418 4644 3617 4672
+rect 3418 4632 3482 4644
+rect 3602 4641 3617 4644
+rect 3651 4641 3666 4675
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+rect 4362 2692 4366 2748
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+rect 4362 2688 4426 2692
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+rect 4442 2692 4446 2748
+rect 4446 2692 4502 2748
+rect 4502 2692 4506 2748
+rect 4442 2688 4506 2692
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+rect 1824 2148 1828 2204
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+rect 1904 2148 1908 2204
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+rect 3450 2148 3454 2204
+rect 3390 2144 3454 2148
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+rect 3470 2148 3474 2204
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+rect 3530 2148 3534 2204
+rect 3470 2144 3534 2148
+rect 3550 2204 3614 2208
+rect 3550 2148 3554 2204
+rect 3554 2148 3610 2204
+rect 3610 2148 3614 2204
+rect 3550 2144 3614 2148
+rect 3630 2204 3694 2208
+rect 3630 2148 3634 2204
+rect 3634 2148 3690 2204
+rect 3690 2148 3694 2204
+rect 3630 2144 3694 2148
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+rect 5015 2148 5019 2204
+rect 5019 2148 5075 2204
+rect 5075 2148 5079 2204
+rect 5015 2144 5079 2148
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+rect 5095 2148 5099 2204
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+rect 5235 2148 5239 2204
+rect 5175 2144 5239 2148
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+rect 5255 2148 5259 2204
+rect 5259 2148 5315 2204
+rect 5315 2148 5319 2204
+rect 5255 2144 5319 2148
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+rect 2637 1604 2641 1660
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+rect 2657 1604 2661 1660
+rect 2661 1604 2717 1660
+rect 2717 1604 2721 1660
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+rect 2737 1660 2801 1664
+rect 2737 1604 2741 1660
+rect 2741 1604 2797 1660
+rect 2797 1604 2801 1660
+rect 2737 1600 2801 1604
+rect 2817 1660 2881 1664
+rect 2817 1604 2821 1660
+rect 2821 1604 2877 1660
+rect 2877 1604 2881 1660
+rect 2817 1600 2881 1604
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+rect 4206 1604 4262 1660
+rect 4262 1604 4266 1660
+rect 4202 1600 4266 1604
+rect 4282 1660 4346 1664
+rect 4282 1604 4286 1660
+rect 4286 1604 4342 1660
+rect 4342 1604 4346 1660
+rect 4282 1600 4346 1604
+rect 4362 1660 4426 1664
+rect 4362 1604 4366 1660
+rect 4366 1604 4422 1660
+rect 4422 1604 4426 1660
+rect 4362 1600 4426 1604
+rect 4442 1660 4506 1664
+rect 4442 1604 4446 1660
+rect 4446 1604 4502 1660
+rect 4502 1604 4506 1660
+rect 4442 1600 4506 1604
+rect 1764 1116 1828 1120
+rect 1764 1060 1768 1116
+rect 1768 1060 1824 1116
+rect 1824 1060 1828 1116
+rect 1764 1056 1828 1060
+rect 1844 1116 1908 1120
+rect 1844 1060 1848 1116
+rect 1848 1060 1904 1116
+rect 1904 1060 1908 1116
+rect 1844 1056 1908 1060
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+rect 1924 1060 1928 1116
+rect 1928 1060 1984 1116
+rect 1984 1060 1988 1116
+rect 1924 1056 1988 1060
+rect 2004 1116 2068 1120
+rect 2004 1060 2008 1116
+rect 2008 1060 2064 1116
+rect 2064 1060 2068 1116
+rect 2004 1056 2068 1060
+rect 3390 1116 3454 1120
+rect 3390 1060 3394 1116
+rect 3394 1060 3450 1116
+rect 3450 1060 3454 1116
+rect 3390 1056 3454 1060
+rect 3470 1116 3534 1120
+rect 3470 1060 3474 1116
+rect 3474 1060 3530 1116
+rect 3530 1060 3534 1116
+rect 3470 1056 3534 1060
+rect 3550 1116 3614 1120
+rect 3550 1060 3554 1116
+rect 3554 1060 3610 1116
+rect 3610 1060 3614 1116
+rect 3550 1056 3614 1060
+rect 3630 1116 3694 1120
+rect 3630 1060 3634 1116
+rect 3634 1060 3690 1116
+rect 3690 1060 3694 1116
+rect 3630 1056 3694 1060
+rect 5015 1116 5079 1120
+rect 5015 1060 5019 1116
+rect 5019 1060 5075 1116
+rect 5075 1060 5079 1116
+rect 5015 1056 5079 1060
+rect 5095 1116 5159 1120
+rect 5095 1060 5099 1116
+rect 5099 1060 5155 1116
+rect 5155 1060 5159 1116
+rect 5095 1056 5159 1060
+rect 5175 1116 5239 1120
+rect 5175 1060 5179 1116
+rect 5179 1060 5235 1116
+rect 5235 1060 5239 1116
+rect 5175 1056 5239 1060
+rect 5255 1116 5319 1120
+rect 5255 1060 5259 1116
+rect 5259 1060 5315 1116
+rect 5315 1060 5319 1116
+rect 5255 1056 5319 1060
+<< metal4 >>
+rect 1756 5472 2076 6032
+rect 1756 5408 1764 5472
+rect 1828 5408 1844 5472
+rect 1908 5408 1924 5472
+rect 1988 5408 2004 5472
+rect 2068 5408 2076 5472
+rect 1756 5238 2076 5408
+rect 1756 5002 1798 5238
+rect 2034 5002 2076 5238
+rect 1756 4384 2076 5002
+rect 1756 4320 1764 4384
+rect 1828 4320 1844 4384
+rect 1908 4320 1924 4384
+rect 1988 4320 2004 4384
+rect 2068 4320 2076 4384
+rect 1756 3606 2076 4320
+rect 1756 3370 1798 3606
+rect 2034 3370 2076 3606
+rect 1756 3296 2076 3370
+rect 1756 3232 1764 3296
+rect 1828 3232 1844 3296
+rect 1908 3232 1924 3296
+rect 1988 3232 2004 3296
+rect 2068 3232 2076 3296
+rect 1756 2208 2076 3232
+rect 1756 2144 1764 2208
+rect 1828 2144 1844 2208
+rect 1908 2144 1924 2208
+rect 1988 2144 2004 2208
+rect 2068 2144 2076 2208
+rect 1756 1974 2076 2144
+rect 1756 1738 1798 1974
+rect 2034 1738 2076 1974
+rect 1756 1120 2076 1738
+rect 1756 1056 1764 1120
+rect 1828 1056 1844 1120
+rect 1908 1056 1924 1120
+rect 1988 1056 2004 1120
+rect 2068 1056 2076 1120
+rect 1756 1040 2076 1056
+rect 2569 6016 2889 6032
+rect 2569 5952 2577 6016
+rect 2641 5952 2657 6016
+rect 2721 5952 2737 6016
+rect 2801 5952 2817 6016
+rect 2881 5952 2889 6016
+rect 2569 4928 2889 5952
+rect 2569 4864 2577 4928
+rect 2641 4864 2657 4928
+rect 2721 4864 2737 4928
+rect 2801 4864 2817 4928
+rect 2881 4864 2889 4928
+rect 2569 4422 2889 4864
+rect 2569 4186 2611 4422
+rect 2847 4186 2889 4422
+rect 2569 3840 2889 4186
+rect 2569 3776 2577 3840
+rect 2641 3776 2657 3840
+rect 2721 3776 2737 3840
+rect 2801 3776 2817 3840
+rect 2881 3776 2889 3840
+rect 2569 2790 2889 3776
+rect 2569 2752 2611 2790
+rect 2847 2752 2889 2790
+rect 2569 2688 2577 2752
+rect 2881 2688 2889 2752
+rect 2569 2554 2611 2688
+rect 2847 2554 2889 2688
+rect 2569 1664 2889 2554
+rect 2569 1600 2577 1664
+rect 2641 1600 2657 1664
+rect 2721 1600 2737 1664
+rect 2801 1600 2817 1664
+rect 2881 1600 2889 1664
+rect 2569 1040 2889 1600
+rect 3382 5472 3702 6032
+rect 3382 5408 3390 5472
+rect 3454 5408 3470 5472
+rect 3534 5408 3550 5472
+rect 3614 5408 3630 5472
+rect 3694 5408 3702 5472
+rect 3382 5238 3702 5408
+rect 3382 5002 3424 5238
+rect 3660 5002 3702 5238
+rect 3382 4384 3702 5002
+rect 3382 4320 3390 4384
+rect 3454 4320 3470 4384
+rect 3534 4320 3550 4384
+rect 3614 4320 3630 4384
+rect 3694 4320 3702 4384
+rect 3382 3606 3702 4320
+rect 3382 3370 3424 3606
+rect 3660 3370 3702 3606
+rect 3382 3296 3702 3370
+rect 3382 3232 3390 3296
+rect 3454 3232 3470 3296
+rect 3534 3232 3550 3296
+rect 3614 3232 3630 3296
+rect 3694 3232 3702 3296
+rect 3382 2208 3702 3232
+rect 3382 2144 3390 2208
+rect 3454 2144 3470 2208
+rect 3534 2144 3550 2208
+rect 3614 2144 3630 2208
+rect 3694 2144 3702 2208
+rect 3382 1974 3702 2144
+rect 3382 1738 3424 1974
+rect 3660 1738 3702 1974
+rect 3382 1120 3702 1738
+rect 3382 1056 3390 1120
+rect 3454 1056 3470 1120
+rect 3534 1056 3550 1120
+rect 3614 1056 3630 1120
+rect 3694 1056 3702 1120
+rect 3382 1040 3702 1056
+rect 4194 6016 4514 6032
+rect 4194 5952 4202 6016
+rect 4266 5952 4282 6016
+rect 4346 5952 4362 6016
+rect 4426 5952 4442 6016
+rect 4506 5952 4514 6016
+rect 4194 4928 4514 5952
+rect 4194 4864 4202 4928
+rect 4266 4864 4282 4928
+rect 4346 4864 4362 4928
+rect 4426 4864 4442 4928
+rect 4506 4864 4514 4928
+rect 4194 4422 4514 4864
+rect 4194 4186 4236 4422
+rect 4472 4186 4514 4422
+rect 4194 3840 4514 4186
+rect 4194 3776 4202 3840
+rect 4266 3776 4282 3840
+rect 4346 3776 4362 3840
+rect 4426 3776 4442 3840
+rect 4506 3776 4514 3840
+rect 4194 2790 4514 3776
+rect 4194 2752 4236 2790
+rect 4472 2752 4514 2790
+rect 4194 2688 4202 2752
+rect 4506 2688 4514 2752
+rect 4194 2554 4236 2688
+rect 4472 2554 4514 2688
+rect 4194 1664 4514 2554
+rect 4194 1600 4202 1664
+rect 4266 1600 4282 1664
+rect 4346 1600 4362 1664
+rect 4426 1600 4442 1664
+rect 4506 1600 4514 1664
+rect 4194 1040 4514 1600
+rect 5007 5472 5327 6032
+rect 5007 5408 5015 5472
+rect 5079 5408 5095 5472
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+rect 5239 5408 5255 5472
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+rect 5007 4384 5327 5002
+rect 5007 4320 5015 4384
+rect 5079 4320 5095 4384
+rect 5159 4320 5175 4384
+rect 5239 4320 5255 4384
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+rect 5007 3296 5327 3370
+rect 5007 3232 5015 3296
+rect 5079 3232 5095 3296
+rect 5159 3232 5175 3296
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+rect 5007 2208 5327 3232
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+rect 5159 2144 5175 2208
+rect 5239 2144 5255 2208
+rect 5319 2144 5327 2208
+rect 5007 1974 5327 2144
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+rect 5285 1738 5327 1974
+rect 5007 1120 5327 1738
+rect 5007 1056 5015 1120
+rect 5079 1056 5095 1120
+rect 5159 1056 5175 1120
+rect 5239 1056 5255 1120
+rect 5319 1056 5327 1120
+rect 5007 1040 5327 1056
+<< via4 >>
+rect 1798 5002 2034 5238
+rect 1798 3370 2034 3606
+rect 1798 1738 2034 1974
+rect 2611 4186 2847 4422
+rect 2611 2752 2847 2790
+rect 2611 2688 2641 2752
+rect 2641 2688 2657 2752
+rect 2657 2688 2721 2752
+rect 2721 2688 2737 2752
+rect 2737 2688 2801 2752
+rect 2801 2688 2817 2752
+rect 2817 2688 2847 2752
+rect 2611 2554 2847 2688
+rect 3424 5002 3660 5238
+rect 3424 3370 3660 3606
+rect 3424 1738 3660 1974
+rect 4236 4186 4472 4422
+rect 4236 2752 4472 2790
+rect 4236 2688 4266 2752
+rect 4266 2688 4282 2752
+rect 4282 2688 4346 2752
+rect 4346 2688 4362 2752
+rect 4362 2688 4426 2752
+rect 4426 2688 4442 2752
+rect 4442 2688 4472 2752
+rect 4236 2554 4472 2688
+rect 5049 5002 5285 5238
+rect 5049 3370 5285 3606
+rect 5049 1738 5285 1974
+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
+rect 1104 4422 5980 4464
+rect 1104 4186 2611 4422
+rect 2847 4186 4236 4422
+rect 4472 4186 5980 4422
+rect 1104 4144 5980 4186
+rect 1104 3606 5980 3648
+rect 1104 3370 1798 3606
+rect 2034 3370 3424 3606
+rect 3660 3370 5049 3606
+rect 5285 3370 5980 3606
+rect 1104 3328 5980 3370
+rect 1104 2790 5980 2832
+rect 1104 2554 2611 2790
+rect 2847 2554 4236 2790
+rect 4472 2554 5980 2790
+rect 1104 2512 5980 2554
+rect 1104 1974 5980 2016
+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__decap_3 PHY_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_2
+timestamp 1606755340
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_1_6
+timestamp 1606755340
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[27\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[28\]
+timestamp 1606755340
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[3\]
+timestamp 1606755340
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_12 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_15
+timestamp 1606755340
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[0\]
+timestamp 1606755340
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[11\]
+timestamp 1606755340
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[1\]
+timestamp 1606755340
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[20\]
+timestamp 1606755340
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_20
+timestamp 1606755340
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_21
+timestamp 1606755340
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_6 FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[15\]
+timestamp 1606755340
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[7\]
+timestamp 1606755340
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_29
+timestamp 1606755340
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1606755340
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1606755340
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_47
+timestamp 1606755340
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[4\]
+timestamp 1606755340
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_39
+timestamp 1606755340
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_45
+timestamp 1606755340
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1606755340
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1606755340
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[13\]
+timestamp 1606755340
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19
+timestamp 1606755340
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_27
+timestamp 1606755340
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_32
+timestamp 1606755340
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1606755340
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[9\]
+timestamp 1606755340
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_44
+timestamp 1606755340
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_6
+timestamp 1606755340
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[31\]
+timestamp 1606755340
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_6
+timestamp 1606755340
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_18
+timestamp 1606755340
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_30
+timestamp 1606755340
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 PHY_7
+timestamp 1606755340
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_3_42
+timestamp 1606755340
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 PHY_8
+timestamp 1606755340
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[17\]
+timestamp 1606755340
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[24\]
+timestamp 1606755340
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_10
+timestamp 1606755340
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[14\]
+timestamp 1606755340
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[25\]
+timestamp 1606755340
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[8\]
+timestamp 1606755340
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_14
+timestamp 1606755340
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_18
+timestamp 1606755340
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3 FILLER_4_35
+timestamp 1606755340
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[16\]
+timestamp 1606755340
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[22\]
+timestamp 1606755340
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_30
+timestamp 1606755340
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20
+timestamp 1606755340
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_26
+timestamp 1606755340
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3 PHY_9
+timestamp 1606755340
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[26\]
+timestamp 1606755340
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_41
+timestamp 1606755340
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_46
+timestamp 1606755340
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3 PHY_10
+timestamp 1606755340
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[2\]
+timestamp 1606755340
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[6\]
+timestamp 1606755340
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_5_6
+timestamp 1606755340
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_5_11
+timestamp 1606755340
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8 FILLER_5_23
+timestamp 1606755340
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_5_31
+timestamp 1606755340
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[10\]
+timestamp 1606755340
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[18\]
+timestamp 1606755340
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_11
+timestamp 1606755340
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[29\]
+timestamp 1606755340
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_5_49
+timestamp 1606755340
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6 FILLER_5_40
+timestamp 1606755340
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_12
+timestamp 1606755340
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_14
+timestamp 1606755340
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[19\]
+timestamp 1606755340
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_12
+timestamp 1606755340
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_6 FILLER_6_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_3
+timestamp 1606755340
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[21\]
+timestamp 1606755340
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[30\]
+timestamp 1606755340
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_20
+timestamp 1606755340
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_24
+timestamp 1606755340
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_15
+timestamp 1606755340
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 FILLER_6_28
+timestamp 1606755340
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[12\]
+timestamp 1606755340
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[5\]
+timestamp 1606755340
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_36
+timestamp 1606755340
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21
+timestamp 1606755340
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_6_32
+timestamp 1606755340
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_27
+timestamp 1606755340
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_36
+timestamp 1606755340
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_13
+timestamp 1606755340
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_15
+timestamp 1606755340
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[23\]
+timestamp 1606755340
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_7_42
+timestamp 1606755340
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_40
+timestamp 1606755340
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_6_48
+timestamp 1606755340
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_7_46
+timestamp 1606755340
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3 PHY_16
+timestamp 1606755340
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_15
+timestamp 1606755340
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22
+timestamp 1606755340
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_8_27
+timestamp 1606755340
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_32
+timestamp 1606755340
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 PHY_17
+timestamp 1606755340
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6 FILLER_8_44
+timestamp 1606755340
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+string GDS_FILE ../gds/user_id_programming.gds
+string GDS_START 0
+<< end >>
diff --git a/mag/user_id_textblock.mag b/mag/user_id_textblock.mag
new file mode 100644
index 0000000..132a28c
--- /dev/null
+++ b/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_0 alphaX_7 hexdigits
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_6 hexdigits
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_5 hexdigits
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_2 alphaX_4 hexdigits
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_3 hexdigits
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_2 hexdigits
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_A alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
new file mode 100644
index 0000000..a3f32bc
--- /dev/null
+++ b/verilog/rtl/caravel.v
@@ -0,0 +1,817 @@
+// `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+module caravel (
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb,
+
+ // Note that only two pins are available on the flash so dual and
+ // quad flash modes are not available.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h0002000a;
+
+ // These pins are overlaid on mprj_io space. They have the function
+ // below when the management processor is in reset, or in the default
+ // configuration. They are assigned to uses in the user space by the
+ // configuration program running off of the SPI flash. Note that even
+ // when the user has taken control of these pins, they can be restored
+ // to the original use by setting the resetb pin low. The SPI pins and
+ // UART pins can be connected directly to an FTDI chip as long as the
+ // FTDI chip sets these lines to high impedence (input function) at
+ // all times except when holding the chip in reset.
+
+ // JTAG = mprj_io[0] (inout)
+ // SDO = mprj_io[1] (output)
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ // These pins are reserved for any project that wants to incorporate
+ // its own processor and flash controller. While a user project can
+ // technically use any available I/O pins for the purpose, these
+ // four pins connect to a pass-through mode from the SPI slave (pins
+ // 1-4 above) so that any SPI flash connected to these specific pins
+ // can be accessed through the SPI slave even when the processor is in
+ // reset.
+
+ // user_flash_csb = mprj_io[8]
+ // user_flash_sck = mprj_io[9]
+ // user_flash_io0 = mprj_io[10]
+ // user_flash_io1 = mprj_io[11]
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // User Project Control (pad-facing)
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+ // User Project Control (user-facing)
+ wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;
+ wire jtag_out, sdo_out;
+ wire jtag_outenb, sdo_outenb;
+ wire gpio_flash_io2_out, gpio_flash_io3_out;
+
+ wire [1:0] mgmt_io_nc; /* no-connects */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+
+ chip_io padframe(
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ `endif
+ // Core Side Pins
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_core),
+ .flash_clk_core(flash_clk_core),
+ .flash_csb_oeb_core(flash_csb_oeb_core),
+ .flash_clk_oeb_core(flash_clk_oeb_core),
+ .flash_io0_oeb_core(flash_io0_oeb_core),
+ .flash_io1_oeb_core(flash_io1_oeb_core),
+ .flash_csb_ieb_core(flash_csb_ieb_core),
+ .flash_clk_ieb_core(flash_clk_ieb_core),
+ .flash_io0_ieb_core(flash_io0_ieb_core),
+ .flash_io1_ieb_core(flash_io1_ieb_core),
+ .flash_io0_do_core(flash_io0_do_core),
+ .flash_io1_do_core(flash_io1_do_core),
+ .flash_io0_di_core(flash_io0_di_core),
+ .flash_io1_di_core(flash_io1_di_core),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(user_analog_io)
+ );
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ wire [7:0] spi_ro_config_core;
+
+ // LA signals
+ wire [127:0] la_data_in_user; // From CPU to MPRJ
+ wire [127:0] la_data_in_mprj; // From MPRJ to CPU
+ wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+ wire [127:0] la_data_out_user; // From MPRJ to CPU
+ wire [127:0] la_oenb_user; // From CPU to MPRJ
+ wire [127:0] la_oenb_mprj; // From CPU to MPRJ
+ wire [127:0] la_iena_mprj; // From CPU only
+ wire [2:0] user_irq; // From MRPJ to CPU
+ wire [2:0] user_irq_core;
+ wire [2:0] user_irq_ena;
+
+ // WB MI A (User Project)
+ wire mprj_cyc_o_core;
+ wire mprj_stb_o_core;
+ wire mprj_we_o_core;
+ wire [3:0] mprj_sel_o_core;
+ wire [31:0] mprj_adr_o_core;
+ wire [31:0] mprj_dat_o_core;
+ wire mprj_ack_i_core;
+ wire [31:0] mprj_dat_i_core;
+
+ // WB MI B (xbar)
+ wire xbar_cyc_o_core;
+ wire xbar_stb_o_core;
+ wire xbar_we_o_core;
+ wire [3:0] xbar_sel_o_core;
+ wire [31:0] xbar_adr_o_core;
+ wire [31:0] xbar_dat_o_core;
+ wire xbar_ack_i_core;
+ wire [31:0] xbar_dat_i_core;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+ // Storage area
+ // Management R/W interface
+ wire [`RAM_BLOCKS-1:0] mgmt_ena;
+ wire [`RAM_BLOCKS-1:0] mgmt_wen;
+ wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
+ wire [7:0] mgmt_addr;
+ wire [31:0] mgmt_wdata;
+ wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
+ // Management RO interface
+ wire mgmt_ena_ro;
+ wire [7:0] mgmt_addr_ro;
+ wire [31:0] mgmt_rdata_ro;
+
+ mgmt_core soc (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_csb_oeb(flash_csb_oeb_core),
+ .flash_clk_oeb(flash_clk_oeb_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_csb_ieb(flash_csb_ieb_core),
+ .flash_clk_ieb(flash_clk_ieb_core),
+ .flash_io0_ieb(flash_io0_ieb_core),
+ .flash_io1_ieb(flash_io1_ieb_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io1_di(flash_io1_di_core),
+ // Master Reset
+ .resetb(rstb_l),
+ .porb(porb_l),
+ // Clocks and reset
+ .clock(clock_core),
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .core_rstn(caravel_rstn),
+ // IRQ
+ .user_irq(user_irq),
+ .user_irq_ena(user_irq_ena),
+ // Logic Analyzer
+ .la_input(la_data_in_mprj),
+ .la_output(la_data_out_mprj),
+ .la_oenb(la_oenb_mprj),
+ .la_iena(la_iena_mprj),
+ // User Project IO Control
+ .mprj_vcc_pwrgood(mprj_vcc_pwrgood),
+ .mprj2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .mprj_vdd_pwrgood(mprj_vdd_pwrgood),
+ .mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
+ .mprj_io_loader_resetn(mprj_io_loader_resetn),
+ .mprj_io_loader_clock(mprj_io_loader_clock),
+ .mprj_io_loader_data_1(mprj_io_loader_data_1),
+ .mprj_io_loader_data_2(mprj_io_loader_data_2),
+ .mgmt_in_data(mgmt_io_in),
+ .mgmt_out_data({gpio_flash_io3_out, gpio_flash_io2_out,
+ mgmt_io_in[(`MPRJ_IO_PADS-3):2], mgmt_io_nc}),
+ .pwr_ctrl_out(pwr_ctrl_out),
+ .sdo_out(sdo_out),
+ .sdo_outenb(sdo_outenb),
+ .jtag_out(jtag_out),
+ .jtag_outenb(jtag_outenb),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ // User Project Slave ports (WB MI A)
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_we_o(mprj_we_o_core),
+ .mprj_sel_o(mprj_sel_o_core),
+ .mprj_adr_o(mprj_adr_o_core),
+ .mprj_dat_o(mprj_dat_o_core),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_dat_i(mprj_dat_i_core),
+ // mask data
+ .mask_rev(mask_rev),
+ // MGMT area R/W interface
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // MGMT area RO interface
+ .mgmt_ena_ro(mgmt_ena_ro),
+ .mgmt_addr_ro(mgmt_addr_ro),
+ .mgmt_rdata_ro(mgmt_rdata_ro)
+ );
+
+ /* Clock and reset to user space are passed through a tristate */
+ /* buffer like the above, but since they are intended to be */
+ /* always active, connect the enable to the logic-1 output from */
+ /* the vccd1 domain. */
+
+ mgmt_protect mgmt_buffers (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ .vccd2(vccd2_core),
+ .vssd2(vssd2_core),
+ .vdda1(vdda1_core),
+ .vssa1(vssa1_core),
+ .vdda2(vdda2_core),
+ .vssa2(vssa2_core),
+ `endif
+ .caravel_clk(caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+ .user_irq_core(user_irq_core),
+ .la_data_out_core(la_data_out_user),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_data_in_core(la_data_in_user),
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_oenb_core(la_oenb_user),
+ .la_iena_mprj(la_iena_mprj),
+ .user_irq_ena(user_irq_ena),
+
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_reset(mprj_reset),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user(mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+ .user_irq(user_irq),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood)
+ );
+
+
+ /*----------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*----------------------------------------------*/
+
+ user_project_wrapper mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+ // MGMT SoC Wishbone Slave
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user),
+ .wbs_sel_i(mprj_sel_o_user),
+ .wbs_adr_i(mprj_adr_o_user),
+ .wbs_dat_i(mprj_dat_o_user),
+ .wbs_ack_o(mprj_ack_i_core),
+ .wbs_dat_o(mprj_dat_i_core),
+ // Logic Analyzer
+ .la_data_in(la_data_in_user),
+ .la_data_out(la_data_out_user),
+ .la_oenb(la_oenb_user),
+ // IO Pads
+ .io_in (user_io_in),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .analog_io(user_analog_io),
+ // Independent clock
+ .user_clock2(mprj_clock2),
+ // IRQ
+ .user_irq(user_irq_core)
+ );
+
+ /*--------------------------------------*/
+ /* End user project instantiation */
+ /*--------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+ gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+ gpio_control_block #(
+ .DM_INIT(`DM_INIT), // Mode = output, strong up/down
+ .OENB_INIT(`OENB_INIT) // Enable output signaling from wire
+ ) gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out({sdo_out, jtag_out}),
+ .mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 0 to 18) */
+ wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):2]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):2]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):2]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):2]),
+ .mgmt_gpio_oeb(one_loop1),
+
+ .one(one_loop1),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):2]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):2]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):6]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):2])
+ );
+
+ /* Last two GPIOs (flash_io2 and flash_io3) */
+ gpio_control_block #(
+ .DM_INIT(`DM_INIT), // Mode = output, strong up/down
+ .OENB_INIT(`OENB_INIT) // Enable output signaling from wire
+ ) gpio_control_bidir_2 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .mgmt_gpio_out({gpio_flash_io3_out, gpio_flash_io2_out}),
+ .mgmt_gpio_oeb({flash_io3_oeb_core, flash_io2_oeb_core}),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-6)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 37) */
+ wire [`MPRJ_IO_PADS_2-3:0] one_loop2;
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-3):0]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-3):0]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-3):0]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-3):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_oeb(one_loop2),
+
+ .one(one_loop2),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-3):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-3):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-7):(`MPRJ_IO_PADS_1*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss(vssio_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+ // Storage area
+ storage storage(
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mgmt_clk(caravel_clk),
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // Management RO interface
+ .mgmt_ena_ro(mgmt_ena_ro),
+ .mgmt_addr_ro(mgmt_addr_ro),
+ .mgmt_rdata_ro(mgmt_rdata_ro)
+ );
+
+endmodule
+// `default_nettype wire
