Updated license header
diff --git a/verilog/rtl/yonga_lz4_decoder_controller.v b/verilog/rtl/yonga_lz4_decoder_controller.v
index 02c1ad3..9b442d9 100644
--- a/verilog/rtl/yonga_lz4_decoder_controller.v
+++ b/verilog/rtl/yonga_lz4_decoder_controller.v
@@ -1,23 +1,16 @@
-`timescale 1ns / 1ps
-// =====================================================================================
-// (C) COPYRIGHT 2021 YongaTek (Yonga Technology Microelectronics)
-// All rights reserved.
-// This file contains confidential and proprietary information of YongaTek and
-// is protected under international copyright and other intellectual property laws.
-// =====================================================================================
-// Project : lz4_decompress
-// File ID : %%
-// Design Unit Name : yonga_lz4_decoder_controller.v
-// Description :
-// Comments :
-// Revision : %%
-// Last Changed Date : %%
-// Last Changed By :
-// Designer
-// Name : Bahadir TÜRKOGLU
-// E-mail : bahadir.turkoglu@yongatek.com
-// =====================================================================================
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+`timescale 1ns / 1ps
module yonga_lz4_decoder_controller(
input wire clk,
