Update yonga_lz4_decoder_top.v

verilog/rtl/yonga_lz4_decoder_top.v

diff --git a/verilog/rtl/yonga_lz4_decoder_top.v b/verilog/rtl/yonga_lz4_decoder_top.v
index d2600a9..149421d 100644
--- a/verilog/rtl/yonga_lz4_decoder_top.v
+++ b/verilog/rtl/yonga_lz4_decoder_top.v
@@ -49,7 +49,6 @@
 wire decompress_fifo_empty1;
 
 wire o_in_fifo_full1;
-wire [7:0] decompress_data1;
 wire idle1;
 
 reg lz4_o_fifo_read_request1;
@@ -101,7 +100,7 @@
          )
         U5(
             .clk(clk),
-            .reset(!rstn),
+            .reset(rst),
             .tx(tx),
             .rx(rx),
             .rd_uart(rx_fifo_not_empty1),