commit: 162cf0fe64236b19956af0e2d3d22cdad1ef6c85
[log] [tgz]
author: abdullahyildiz <abdullah.yildiz@yongatek.com>
Fri Jun 11 17:14:14 2021 +0300
committer: abdullahyildiz <abdullah.yildiz@yongatek.com>
Fri Jun 11 17:14:14 2021 +0300
tree: 12c37867134b2fda34cee8ae602b598705cc4c91
parent: 270b3e024098ac9d948ea84a0259fb681a35c3f2 [diff]

Update yonga_lz4_decoder_top.v

verilog/rtl/yonga_lz4_decoder_top.v[diff]

1 file changed

tree: 12c37867134b2fda34cee8ae602b598705cc4c91

README.md

YONGA-LZ4 Decoder

Table of contents

Overview
Simulation
Checklist for Open-MPW Submission

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Simulation

TBA

Checklist for Open-MPW Submission

[x] The project repo adheres to the same directory structure in this repo
[x] The project repo contain info.yaml at the project root
[x] Top level macro is named user_project_wrapper
[ ] Full Chip Simulation passes for RTL and GL (gate-level)
[ ] The hardened Macros are LVS and DRC clean
[ ] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
[ ] XOR check passes with zero total difference.
[ ] Openlane summary reports are retained under ./signoff/