commit 13b9483180a1b26695e4ebe94d3c923d33a5cd9b
author abdullahyildiz <abdullah.yildiz@yongatek.com> Tue Jun 08 18:39:48 2021 +0300
committer abdullahyildiz <abdullah.yildiz@yongatek.com> Tue Jun 08 18:39:48 2021 +0300
tree 26be7a0302363a30c07c1c08d9ddbb63edf25add
parent f527929cfefb29ac47798f4218c8ecadf04171dd

Update user_proj_example.v

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 4089cd3..d78bbe8 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -95,8 +95,8 @@
 assign la_data_out = {{(88){1'b0}}, decompressed_data1,{(32){1'b0}}}; 
 assign compressed_data1 = la_data_in[7:0];
 
-assign clk = (~la_oenb[32]) ? la_data_in[64]: wb_clk_i;
-assign rst = (~la_oenb[33]) ? la_data_in[65]: wb_rst_i;
+assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
 
 assign irq = 3'b000;