Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
e004c292748188600e00833befa4fb49d45f70ae
commit
e004c292748188600e00833befa4fb49d45f70ae
[
log
]
author
mrg <mrg@ucsc.edu>
Sun Jun 13 17:07:00 2021 -0700
committer
mrg <mrg@ucsc.edu>
Sun Jun 13 17:07:00 2021 -0700
tree
6c587cb36266f9f6b5d3c64e404f4a1b3cbc36ec
parent
0c951e161605c444662a9d9ae9634863286e5cce
[
diff
]
Update so 0..7 is dual and 8..15 is single
verilog/rtl/user_project_wrapper.v
[
diff
]
1 file changed
tree: 6c587cb36266f9f6b5d3c64e404f4a1b3cbc36ec
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.