)]}'
{
  "commit": "e004c292748188600e00833befa4fb49d45f70ae",
  "tree": "6c587cb36266f9f6b5d3c64e404f4a1b3cbc36ec",
  "parents": [
    "0c951e161605c444662a9d9ae9634863286e5cce"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 17:07:00 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 17:07:00 2021 -0700"
  },
  "message": "Update so 0..7 is dual and 8..15 is single\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "02edbb4919f8161d8974a0809fe4703cadce9ebd",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "986b5430437fea083505b5fce2f69f27050c594c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}