Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
0c951e161605c444662a9d9ae9634863286e5cce
commit
0c951e161605c444662a9d9ae9634863286e5cce
[
log
]
author
mrg <mrg@ucsc.edu>
Sun Jun 13 17:02:00 2021 -0700
committer
mrg <mrg@ucsc.edu>
Sun Jun 13 17:02:00 2021 -0700
tree
ddf8c376b92a1596c44b403a081ed0d9b796a311
parent
763d54621a5f567db102abddb9e901a6757d92e2
[
diff
]
Use defines in the design
verilog/rtl/openram_testchip.v
[
diff
]
1 file changed
tree: ddf8c376b92a1596c44b403a081ed0d9b796a311
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.