Use defines in the design
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v index 1bc29df..d363874 100644 --- a/verilog/rtl/openram_testchip.v +++ b/verilog/rtl/openram_testchip.v
@@ -1,3 +1,11 @@ +`define WMASK_SIZE 4 +`define ADDR_SIZE 16 +`define DATA_SIZE 32 +`define SELECT_SIZE 4 +`define MAX_CHIPS 16 +`define PORT_SIZE `DATA_SIZE+`DATA_SIZE+`WMASK_SIZE+2 +`define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE + module openram_testchip( `ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply @@ -17,7 +25,7 @@ input la_sram_clk, input la_in_load, input la_sram_load, - input [111:0] la_data_in, + input [`TOTAL_SIZE-1:0] la_data_in, // GPIO bit to clock control register input gpio_clk, input gpio_in, @@ -26,51 +34,51 @@ input gpio_sram_load, // SRAM data outputs to be captured - input [31:0] sram0_dout0, - input [31:0] sram0_dout1, - input [31:0] sram1_dout0, - input [31:0] sram1_dout1, - input [31:0] sram2_dout0, - input [31:0] sram2_dout1, - input [31:0] sram3_dout0, - input [31:0] sram3_dout1, - input [31:0] sram4_dout0, - input [31:0] sram4_dout1, - input [31:0] sram5_dout0, - input [31:0] sram5_dout1, - input [31:0] sram6_dout0, - input [31:0] sram6_dout1, - input [31:0] sram7_dout0, - input [31:0] sram7_dout1, - input [31:0] sram8_dout0, - input [31:0] sram8_dout1, - input [31:0] sram9_dout0, - input [31:0] sram9_dout1, - input [31:0] sram10_dout0, - input [31:0] sram10_dout1, - input [31:0] sram11_dout0, - input [31:0] sram11_dout1, - input [31:0] sram12_dout0, - input [31:0] sram12_dout1, - input [31:0] sram13_dout0, - input [31:0] sram13_dout1, - input [31:0] sram14_dout0, - input [31:0] sram14_dout1, - input [31:0] sram15_dout0, - input [31:0] sram15_dout1, + input [`DATA_SIZE-1:0] sram0_dout0, + input [`DATA_SIZE-1:0] sram0_dout1, + input [`DATA_SIZE-1:0] sram1_dout0, + input [`DATA_SIZE-1:0] sram1_dout1, + input [`DATA_SIZE-1:0] sram2_dout0, + input [`DATA_SIZE-1:0] sram2_dout1, + input [`DATA_SIZE-1:0] sram3_dout0, + input [`DATA_SIZE-1:0] sram3_dout1, + input [`DATA_SIZE-1:0] sram4_dout0, + input [`DATA_SIZE-1:0] sram4_dout1, + input [`DATA_SIZE-1:0] sram5_dout0, + input [`DATA_SIZE-1:0] sram5_dout1, + input [`DATA_SIZE-1:0] sram6_dout0, + input [`DATA_SIZE-1:0] sram6_dout1, + input [`DATA_SIZE-1:0] sram7_dout0, + input [`DATA_SIZE-1:0] sram7_dout1, + input [`DATA_SIZE-1:0] sram8_dout0, + input [`DATA_SIZE-1:0] sram8_dout1, + input [`DATA_SIZE-1:0] sram9_dout0, + input [`DATA_SIZE-1:0] sram9_dout1, + input [`DATA_SIZE-1:0] sram10_dout0, + input [`DATA_SIZE-1:0] sram10_dout1, + input [`DATA_SIZE-1:0] sram11_dout0, + input [`DATA_SIZE-1:0] sram11_dout1, + input [`DATA_SIZE-1:0] sram12_dout0, + input [`DATA_SIZE-1:0] sram12_dout1, + input [`DATA_SIZE-1:0] sram13_dout0, + input [`DATA_SIZE-1:0] sram13_dout1, + input [`DATA_SIZE-1:0] sram14_dout0, + input [`DATA_SIZE-1:0] sram14_dout1, + input [`DATA_SIZE-1:0] sram15_dout0, + input [`DATA_SIZE-1:0] sram15_dout1, // Shared control/data to the SRAMs - output reg [15:0] addr0, - output reg [31:0] din0, + output reg [`ADDR_SIZE-1:0] addr0, + output reg [`DATA_SIZE-1:0] din0, output reg web0, - output reg [3:0] wmask0, - output reg [15:0] addr1, - output reg [31:0] din1, + output reg [`WMASK_SIZE-1:0] wmask0, + output reg [`ADDR_SIZE-1:0] addr1, + output reg [`DATA_SIZE-1:0] din1, output reg web1, - output reg [3:0] wmask1, + output reg [`WMASK_SIZE-1:0] wmask1, // One CSB for each SRAM - output reg [15:0] csb0, - output reg [15:0] csb1, + output reg [`ADDR_SIZE-1:0] csb0, + output reg [`ADDR_SIZE-1:0] csb1, // Clocks for each SRAM output reg sram0_clk, @@ -89,7 +97,7 @@ output reg sram13_clk, output reg sram14_clk, output reg sram15_clk, - output reg [111:0] la_data_out, + output reg [`TOTAL_SIZE-1:0] la_data_out, output reg gpio_out ); @@ -97,52 +105,52 @@ reg sram_clk; // Store input instruction - reg [111:0] sram_register; - reg csb0_temp; - reg csb1_temp; + reg [`TOTAL_SIZE-1:0] sram_register; + reg csb0_temp; + reg csb1_temp; // Hold dout from SRAM // clocked by SRAM clk - reg [31:0] sram0_data0; - reg [31:0] sram0_data1; - reg [31:0] sram1_data0; - reg [31:0] sram1_data1; - reg [31:0] sram2_data0; - reg [31:0] sram2_data1; - reg [31:0] sram3_data0; - reg [31:0] sram3_data1; - reg [31:0] sram4_data0; - reg [31:0] sram4_data1; - reg [31:0] sram5_data0; - reg [31:0] sram5_data1; - reg [31:0] sram6_data0; - reg [31:0] sram6_data1; - reg [31:0] sram7_data0; - reg [31:0] sram7_data1; - reg [31:0] sram8_data0; - reg [31:0] sram8_data1; - reg [31:0] sram9_data0; - reg [31:0] sram9_data1; - reg [31:0] sram10_data0; - reg [31:0] sram10_data1; - reg [31:0] sram11_data0; - reg [31:0] sram11_data1; - reg [31:0] sram12_data0; - reg [31:0] sram12_data1; - reg [31:0] sram13_data0; - reg [31:0] sram13_data1; - reg [31:0] sram14_data0; - reg [31:0] sram14_data1; - reg [31:0] sram15_data0; - reg [31:0] sram15_data1; + reg [`DATA_SIZE-1:0] sram0_data0; + reg [`DATA_SIZE-1:0] sram0_data1; + reg [`DATA_SIZE-1:0] sram1_data0; + reg [`DATA_SIZE-1:0] sram1_data1; + reg [`DATA_SIZE-1:0] sram2_data0; + reg [`DATA_SIZE-1:0] sram2_data1; + reg [`DATA_SIZE-1:0] sram3_data0; + reg [`DATA_SIZE-1:0] sram3_data1; + reg [`DATA_SIZE-1:0] sram4_data0; + reg [`DATA_SIZE-1:0] sram4_data1; + reg [`DATA_SIZE-1:0] sram5_data0; + reg [`DATA_SIZE-1:0] sram5_data1; + reg [`DATA_SIZE-1:0] sram6_data0; + reg [`DATA_SIZE-1:0] sram6_data1; + reg [`DATA_SIZE-1:0] sram7_data0; + reg [`DATA_SIZE-1:0] sram7_data1; + reg [`DATA_SIZE-1:0] sram8_data0; + reg [`DATA_SIZE-1:0] sram8_data1; + reg [`DATA_SIZE-1:0] sram9_data0; + reg [`DATA_SIZE-1:0] sram9_data1; + reg [`DATA_SIZE-1:0] sram10_data0; + reg [`DATA_SIZE-1:0] sram10_data1; + reg [`DATA_SIZE-1:0] sram11_data0; + reg [`DATA_SIZE-1:0] sram11_data1; + reg [`DATA_SIZE-1:0] sram12_data0; + reg [`DATA_SIZE-1:0] sram12_data1; + reg [`DATA_SIZE-1:0] sram13_data0; + reg [`DATA_SIZE-1:0] sram13_data1; + reg [`DATA_SIZE-1:0] sram14_data0; + reg [`DATA_SIZE-1:0] sram14_data1; + reg [`DATA_SIZE-1:0] sram15_data0; + reg [`DATA_SIZE-1:0] sram15_data1; // Mux output to connect final output data // into sram_register - reg [31:0] read_data0; - reg [31:0] read_data1; + reg [`DATA_SIZE-1:0] read_data0; + reg [`DATA_SIZE-1:0] read_data1; // SRAM input connections - reg [3:0] chip_select; + reg [`SELECT_SIZE-1:0] chip_select; //Selecting clock pin always @(*) begin @@ -168,11 +176,11 @@ always @ (posedge clk) begin if(reset) begin - sram_register <= 112'd1; + sram_register <= {`TOTAL_SIZE{1'b0}}; end // GPIO scanning for transfer else if(gpio_scan) begin - sram_register <= {sram_register[110:0], gpio_in}; + sram_register <= {sram_register[`TOTAL_SIZE-2:0], gpio_in}; end // LA parallel load else if(la_in_load) begin @@ -180,26 +188,32 @@ end // Store results for read out else if(gpio_sram_load || la_sram_load) begin - sram_register <= {sram_register[111:92], read_data0, sram_register[59:38], read_data1, sram_register[5:0]}; + sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE-1], + read_data0, + sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+5:`DATA_SIZE+`WMASK_SIZE+3], + read_data1, + sram_register[`WMASK_SIZE+3:0]}; end end // Splitting register bits into fields -always @(sram_register) begin - chip_select = sram_register[111:108]; - - addr0 = sram_register[107:92]; - din0 = sram_register[91:60]; - csb0_temp = sram_register[59]; - web0 = sram_register[58]; - wmask0 = sram_register[57:54]; +always @(*) begin - addr1 = sram_register[53:38]; - din1 = sram_register[37:6]; - csb1_temp = sram_register[5]; - web1 = sram_register[4]; - wmask1 = sram_register[3:0]; -end // always @ (sram_register) + // TODO: Use defines for these + chip_select = sram_register[`TOTAL_SIZE-1:108]; + + addr0 = sram_register[107:92]; + din0 = sram_register[91:60]; + csb0_temp = sram_register[59]; + web0 = sram_register[58]; + wmask0 = sram_register[57:54]; + + addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2]; + din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2]; + csb1_temp = sram_register[`WMASK_SIZE+1]; + web1 = sram_register[`WMASK_SIZE]; + wmask1 = sram_register[`WMASK_SIZE-1:0]; +end // Apply the correct CSB always @(*) begin @@ -209,40 +223,40 @@ // Store dout of each SRAM -always @ (posedge sram_clk) begin +always @(posedge sram_clk) begin if(reset) begin - sram0_data0 <= 32'd0; - sram0_data1 <= 32'd0; - sram1_data0 <= 32'd0; - sram1_data1 <= 32'd0; - sram2_data0 <= 32'd0; - sram2_data1 <= 32'd0; - sram3_data0 <= 32'd0; - sram3_data1 <= 32'd0; - sram4_data0 <= 32'd0; - sram4_data1 <= 32'd0; - sram5_data0 <= 32'd0; - sram5_data1 <= 32'd0; - sram6_data0 <= 32'd0; - sram6_data1 <= 32'd0; - sram7_data0 <= 32'd0; - sram7_data1 <= 32'd0; - sram8_data0 <= 32'd0; - sram8_data1 <= 32'd0; - sram9_data0 <= 32'd0; - sram9_data1 <= 32'd0; - sram10_data0 <= 32'd0; - sram10_data1 <= 32'd0; - sram11_data0 <= 32'd0; - sram11_data1 <= 32'd0; - sram12_data0 <= 32'd0; - sram12_data1 <= 32'd0; - sram13_data0 <= 32'd0; - sram13_data1 <= 32'd0; - sram14_data0 <= 32'd0; - sram14_data1 <= 32'd0; - sram15_data0 <= 32'd0; - sram15_data1 <= 32'd0; + sram0_data0 <= 0; + sram0_data1 <= 0; + sram1_data0 <= 0; + sram1_data1 <= 0; + sram2_data0 <= 0; + sram2_data1 <= 0; + sram3_data0 <= 0; + sram3_data1 <= 0; + sram4_data0 <= 0; + sram4_data1 <= 0; + sram5_data0 <= 0; + sram5_data1 <= 0; + sram6_data0 <= 0; + sram6_data1 <= 0; + sram7_data0 <= 0; + sram7_data1 <= 0; + sram8_data0 <= 0; + sram8_data1 <= 0; + sram9_data0 <= 0; + sram9_data1 <= 0; + sram10_data0 <= 0; + sram10_data1 <= 0; + sram11_data0 <= 0; + sram11_data1 <= 0; + sram12_data0 <= 0; + sram12_data1 <= 0; + sram13_data0 <= 0; + sram13_data1 <= 0; + sram14_data0 <= 0; + sram14_data1 <= 0; + sram15_data0 <= 0; + sram15_data1 <= 0; end else begin sram0_data0 <= sram0_dout0; @@ -353,7 +367,7 @@ // Output logic always @ (*) begin - gpio_out = sram_register[111]; + gpio_out = sram_register[`TOTAL_SIZE-1]; la_data_out = {16'd0, sram_register}; end