commit: caefc5838f8a00ad83331eb62bbcc3e04f73ceb2
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Sat Jun 12 11:36:41 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sat Jun 12 11:36:41 2021 -0700
tree: 948dc5ba9db4293703f63c9a498c9f68f9c67b0f
parent: a83e12c9840ef3200b9e26b9f251c573f253e329 [diff]

Set proper bits. Compiles without errors, need to test

verilog/rtl/openram_testchip.v[diff]

1 file changed

tree: 948dc5ba9db4293703f63c9a498c9f68f9c67b0f

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.