)]}'
{
  "commit": "caefc5838f8a00ad83331eb62bbcc3e04f73ceb2",
  "tree": "948dc5ba9db4293703f63c9a498c9f68f9c67b0f",
  "parents": [
    "a83e12c9840ef3200b9e26b9f251c573f253e329"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 11:36:41 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 11:36:41 2021 -0700"
  },
  "message": "Set proper bits. Compiles without errors, need to test\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2018741a689552abdee3110f217439f2b0f6df5e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "b86c2f7d5287f9918b73aff44b276a9674c54a7b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}