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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
2d08cd654daa0d3796142c9dc1f099fcbeca049d
commit
2d08cd654daa0d3796142c9dc1f099fcbeca049d
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log
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[
tgz
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author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 17 17:51:36 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 17 17:51:36 2021 -0700
tree
6cc3c32367c6a6267ab23d6b49e03dbf0f58fe7b
parent
d07f5ba611118f44aac875d6322ef451c9d218d5
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diff
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Compiles without error
verilog/rtl/user_project_wrapper.v
[
diff
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1 file changed
tree: 6cc3c32367c6a6267ab23d6b49e03dbf0f58fe7b
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.