commit 2d08cd654daa0d3796142c9dc1f099fcbeca049d
author AmoghLonkar <alonkar@ucsc.edu> Thu Jun 17 17:51:36 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Thu Jun 17 17:51:36 2021 -0700
tree 6cc3c32367c6a6267ab23d6b49e03dbf0f58fe7b
parent d07f5ba611118f44aac875d6322ef451c9d218d5

Compiles without error

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 90c187a..8af964a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -504,18 +504,12 @@
       end
    end
 
-   wire [`DATA_SIZE-1:0] sram8_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram9_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram10_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram11_data1 = 0;
-
    wire [`DATA_SIZE-1:0] sram5_data0 = 0;
    wire [`DATA_SIZE-1:0] sram5_data1 = 0;
    wire [`DATA_SIZE-1:0] sram6_data0 = 0;
    wire [`DATA_SIZE-1:0] sram6_data1 = 0;
    wire [`DATA_SIZE-1:0] sram7_data0 = 0;
    wire [`DATA_SIZE-1:0] sram7_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram7_data1 = 0;
    wire [`DATA_SIZE-1:0] sram8_data1 = 0;
    wire [`DATA_SIZE-1:0] sram9_data1 = 0;
    wire [`DATA_SIZE-1:0] sram10_data1 = 0;