)]}'
{
  "commit": "2d08cd654daa0d3796142c9dc1f099fcbeca049d",
  "tree": "6cc3c32367c6a6267ab23d6b49e03dbf0f58fe7b",
  "parents": [
    "d07f5ba611118f44aac875d6322ef451c9d218d5"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu Jun 17 17:51:36 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu Jun 17 17:51:36 2021 -0700"
  },
  "message": "Compiles without error\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "90c187ae04e48a664c9d8ca00f9233c8e949e6ec",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "8af964afbb180a0a43edadcdfa2f02dcbb03cb8f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}