Simulation clean up and wishbone interconnect added
42 files changed
tree: 75c03bc559d00988e7eb79e2afb7b43bff66f7fc
  1. openlane/
  2. verilog/
  3. info.yaml
  4. LICENSE
  5. Makefile
  6. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

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