i2cm integrated and share same uart io
diff --git a/def/uart_i2cm.def.gz b/def/uart_i2cm.def.gz
new file mode 100644
index 0000000..27af1e4
--- /dev/null
+++ b/def/uart_i2cm.def.gz
Binary files differ
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 971ff12..da26aa3 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ
diff --git a/def/wb_host.def.gz b/def/wb_host.def.gz
index 3c4a47e..fc0af2b 100644
--- a/def/wb_host.def.gz
+++ b/def/wb_host.def.gz
Binary files differ
diff --git a/gds/uart_i2cm.gds.gz b/gds/uart_i2cm.gds.gz
new file mode 100644
index 0000000..867b570
--- /dev/null
+++ b/gds/uart_i2cm.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 0554256..00184b4 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
index 159245a..fb51154 100644
--- a/gds/wb_host.gds.gz
+++ b/gds/wb_host.gds.gz
Binary files differ
diff --git a/lef/uart_i2cm.lef.gz b/lef/uart_i2cm.lef.gz
new file mode 100644
index 0000000..59295e8
--- /dev/null
+++ b/lef/uart_i2cm.lef.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 67d7b2e..44a8c07 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz
index 301b7b7..ab0dcf5 100644
--- a/lef/wb_host.lef.gz
+++ b/lef/wb_host.lef.gz
Binary files differ
diff --git a/mag/uart_i2cm.mag.gz b/mag/uart_i2cm.mag.gz
new file mode 100644
index 0000000..849e312
--- /dev/null
+++ b/mag/uart_i2cm.mag.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 3d0e96f..4769de2 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/mag/wb_host.mag.gz b/mag/wb_host.mag.gz
index f7a6d2a..18aab16 100644
--- a/mag/wb_host.mag.gz
+++ b/mag/wb_host.mag.gz
Binary files differ
diff --git a/maglef/uart_i2cm.mag.gz b/maglef/uart_i2cm.mag.gz
new file mode 100644
index 0000000..a2d5265
--- /dev/null
+++ b/maglef/uart_i2cm.mag.gz
Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index d7dfa7b..689a733 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ
diff --git a/maglef/wb_host.mag.gz b/maglef/wb_host.mag.gz
index 2262f4f..a8d65db 100644
--- a/maglef/wb_host.mag.gz
+++ b/maglef/wb_host.mag.gz
Binary files differ
diff --git a/openlane/uart_i2cm/base.sdc b/openlane/uart_i2cm/base.sdc
new file mode 100644
index 0000000..5a0d2fe
--- /dev/null
+++ b/openlane/uart_i2cm/base.sdc
@@ -0,0 +1,74 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set_units -time ns
+set ::env(CORE_CLOCK_PERIOD) "10"
+set ::env(CORE_CLOCK_PORT)   "app_clk"
+set ::env(CORE_CLOCK_NAME)   "app_clk"
+
+set ::env(LINE_CLOCK_PERIOD) "100"
+set ::env(LINE_CLOCK_PORT)   "u_lineclk_buf/X"
+set ::env(LINE_CLOCK_NAME)   "line_clk"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
+create_clock [get_pins  $::env(LINE_CLOCK_PORT)]  -name $::env(LINE_CLOCK_NAME)  -period $::env(LINE_CLOCK_PERIOD)
+
+set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+
+set line_input_delay_value  [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
+set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_rstn}
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {i2c_rstn}
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_i2c_sel}
+
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*]
+
+
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*]
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*]
+
+set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*]
+set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*]
+set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*]
+
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] 
+
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -setup 0.400
+set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -setup 0.400
+
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -hold 0.050
+set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -hold 0.050
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
diff --git a/openlane/uart_i2cm/config.tcl b/openlane/uart_i2cm/config.tcl
new file mode 100644
index 0000000..088a579
--- /dev/null
+++ b/openlane/uart_i2cm/config.tcl
@@ -0,0 +1,95 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) uart_i2c_top
+
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "app_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+    $script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
+    $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
+    $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+    $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
+    $script_dir/../../verilog/rtl/lib/async_fifo_th.sv   \
+    $script_dir/../../verilog/rtl/lib/reset_sync.sv      \
+    $script_dir/../../verilog/rtl/lib/double_sync_low.v  \
+    $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
+    $script_dir/../../verilog/rtl/lib/registers.v        \
+    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v      \
+    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v     \
+    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v           \
+    $script_dir/../../verilog/rtl/uart_i2c/src/uart_i2c_top.sv       \
+    "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes ]
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) [list 0.0 0.0 300.0 400.0]
+
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/uart_i2cm/pdn.tcl b/openlane/uart_i2cm/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/uart_i2cm/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/uart_i2cm/pin_order.cfg b/openlane/uart_i2cm/pin_order.cfg
new file mode 100644
index 0000000..870fa34
--- /dev/null
+++ b/openlane/uart_i2cm/pin_order.cfg
@@ -0,0 +1,40 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#S
+app_clk                0000 0
+uart_rstn    
+i2c_rstn 
+uart_i2c_sel            
+io_in\[1\]             
+io_out\[1\]             
+io_oeb\[1\]             
+io_in\[0\]             
+io_out\[0\]             
+io_oeb\[0\]             
+
+#N
+reg_cs                 0000 0
+reg_wr                 0000 1
+reg_addr\[3\]          0000 4
+reg_addr\[2\]          0000 5
+reg_addr\[1\]          0000 6
+reg_addr\[0\]          0000 7
+reg_be                 0000 10
+reg_wdata\[7\]         0000 11
+reg_wdata\[6\]         0000 12
+reg_wdata\[5\]         0000 13
+reg_wdata\[4\]         0000 14
+reg_wdata\[3\]         0000 15
+reg_wdata\[2\]         0000 16
+reg_wdata\[1\]         0000 17
+reg_wdata\[0\]         0000 18
+reg_rdata\[7\]         0000 19
+reg_rdata\[6\]         0000 20
+reg_rdata\[5\]         0000 21
+reg_rdata\[4\]         0000 22
+reg_rdata\[3\]         0000 23
+reg_rdata\[2\]         0000 24
+reg_rdata\[1\]         0000 25
+reg_rdata\[0\]         0000 26
+reg_ack                0000 27
diff --git a/openlane/uart_i2cm/sta.tcl b/openlane/uart_i2cm/sta.tcl
new file mode 100644
index 0000000..ef1ab52
--- /dev/null
+++ b/openlane/uart_i2cm/sta.tcl
@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) /project/openlane/uart_i2cm/runs/uart_i2cm/results/lvs/uart_i2c_top.lvs.powered.v
+set ::env(DESIGN_NAME) "uart_i2c_top"
+set ::env(CURRENT_SPEF) /project/openlane/uart_i2cm/runs/uart_i2cm/results/routing/uart_i2c_top.spef
+set ::env(BASE_SDC_FILE) "/project/openlane/uart_i2cm/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+#check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type bc_wc
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01 
+
+
+
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 9c9e20a..acb43f8 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -59,7 +59,7 @@
         $script_dir/../../verilog/gl/spi_master.v \
         $script_dir/../../verilog/gl/wb_interconnect.v \
         $script_dir/../../verilog/gl/glbl_cfg.v     \
-        $script_dir/../../verilog/gl/uart.v     \
+        $script_dir/../../verilog/gl/uart_i2cm.v     \
 	$script_dir/../../verilog/gl/sdram.v \
 	$script_dir/../../verilog/gl/wb_host.v \
 	$script_dir/../../verilog/gl/clk_skew_adjust.v \
@@ -71,7 +71,7 @@
 	$lef_root/glbl_cfg.lef \
 	$lef_root/wb_interconnect.lef \
 	$lef_root/sdram.lef \
-	$lef_root/uart.lef \
+	$lef_root/uart_i2cm.lef \
 	$lef_root/wb_host.lef \
 	$lef_root/clk_skew_adjust.lef \
 	$lef_root/syntacore.lef \
@@ -81,7 +81,7 @@
 	$gds_root/spi_master.gds \
 	$gds_root/glbl_cfg.gds \
 	$gds_root/wb_interconnect.gds \
-	$gds_root/uart.gds \
+	$gds_root/uart_i2cm.gds \
 	$gds_root/sdram.gds \
 	$gds_root/wb_host.gds \
 	$gds_root/clk_skew_adjust.gds \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 7a9c10f..0d6ef5c 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -2,7 +2,7 @@
 u_sdram_ctrl            1000            2700            N
 u_glbl_cfg              2000            2700            N
 u_riscv_top	        500	        800	        N
-u_uart_core             2200            1600            N
+u_uart_i2c              2200            1600            N
 u_intercon              300             2300            N
 u_wb_host               300             300             N
 u_skew_wi               2600            2300            N
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 6b90110..41f63b5 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -17,7 +17,7 @@
 
 
 #S
-user_clock2     
+user_clock2         0000 0  2
 user_clock1     
 wbm_clk_i       
 wbm_rst_i       
@@ -140,7 +140,6 @@
 wbs_clk_out   
 cpu_clk
 rtc_clk
-wbd_int_rst_n
 
 #N
 wbs_stb_o        0000 0 2
@@ -302,3 +301,7 @@
 cfg_clk_ctrl2\[1\]
 cfg_clk_ctrl2\[0\]
 
+uart_rst_n
+i2cm_rst_n
+uart_i2c_sel
+wbd_int_rst_n
diff --git a/signoff/uart_i2cm/OPENLANE_VERSION b/signoff/uart_i2cm/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/uart_i2cm/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/uart_i2cm/PDK_SOURCES b/signoff/uart_i2cm/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/uart_i2cm/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart_i2cm/final_summary_report.csv b/signoff/uart_i2cm/final_summary_report.csv
new file mode 100644
index 0000000..6a4c74e
--- /dev/null
+++ b/signoff/uart_i2cm/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/uart_i2cm,uart_i2c_top,uart_i2cm,Flow_completed,0h5m42s,0h3m37s,59350.0,0.12,29675.0,47,561.56,3561,0,0,0,0,0,0,0,0,0,-1,0,124117,27523,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,81974377,0.0,25.57,25.46,0.33,-1,-1,3562,3582,623,643,0,0,0,3561,98,10,58,70,423,155,27,836,589,556,17,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index b467fd5..cca124b 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h41m39s,0h4m37s,3.3079078455790785,10.2784,1.6539539227895392,0,552.52,17,0,0,0,0,0,0,0,0,1,-1,-1,1190352,4009,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.26,4.32,0.78,1.93,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h41m53s,0h4m38s,3.3079078455790785,10.2784,1.6539539227895392,0,553.94,17,0,0,0,0,0,0,0,0,1,-1,-1,1198068,3955,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.28,4.34,0.79,1.93,-1,851,1469,851,1469,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 02deb7d..2002da3 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h6m19s,0h4m12s,61400.0,0.1,30700.0,49,584.38,3070,0,0,0,0,0,0,0,1,0,-1,0,172826,26248,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,140873672,0.0,49.1,23.43,16.91,-1,-1,2926,3180,551,805,0,0,0,3070,78,0,3,11,50,27,10,799,605,775,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m27s,0h3m34s,61460.0,0.1,30730.0,49,592.54,3073,0,0,0,0,0,0,0,4,0,-1,0,173324,26294,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,139681646,0.0,48.89,23.41,17.83,-1,-1,2929,3183,554,808,0,0,0,3073,77,0,3,11,49,26,11,799,605,775,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/spi/lvs/uart_i2cm.spice.gz b/spi/lvs/uart_i2cm.spice.gz
new file mode 100644
index 0000000..7da4b58
--- /dev/null
+++ b/spi/lvs/uart_i2cm.spice.gz
Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 4a1e3ca..b182d49 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
diff --git a/spi/lvs/wb_host.spice.gz b/spi/lvs/wb_host.spice.gz
index 6fb1da2..02a8557 100644
--- a/spi/lvs/wb_host.spice.gz
+++ b/spi/lvs/wb_host.spice.gz
Binary files differ
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index db261ec..4076ba9 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart user_spi
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart user_spi user_i2cm
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/model/i2c_slave_model.v b/verilog/dv/model/i2c_slave_model.v
new file mode 100755
index 0000000..1271127
--- /dev/null
+++ b/verilog/dv/model/i2c_slave_model.v
@@ -0,0 +1,356 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant synthesizable I2C Slave model    ////
+////                                                             ////
+////                                                             ////
+////  Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
+////           John Sheahan (jrsheahan@optushome.com.au)         ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001,2002 Richard Herveille                   ////
+////                         richard@asics.ws                    ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $
+//
+//  $Date: 2006-09-04 09:08:51 $
+//  $Revision: 1.7 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.6  2005/02/28 11:33:48  rherveille
+//               Fixed Tsu:sta timing check.
+//               Added Thd:sta timing check.
+//
+//               Revision 1.5  2003/12/05 11:05:19  rherveille
+//               Fixed slave address MSB='1' bug
+//
+//               Revision 1.4  2003/09/11 08:25:37  rherveille
+//               Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
+//
+//               Revision 1.3  2002/10/30 18:11:06  rherveille
+//               Added timing tests to i2c_model.
+//               Updated testbench.
+//
+//               Revision 1.2  2002/03/17 10:26:38  rherveille
+//               Fixed some race conditions in the i2c-slave model.
+//               Added debug information.
+//               Added headers.
+//
+
+
+module i2c_slave_model (scl, sda);
+
+	//
+	// parameters
+	//
+	parameter I2C_ADR = 7'b001_0000;
+
+	//
+	// input && outpus
+	//
+	input scl;
+	inout sda;
+
+	//
+	// Variable declaration
+	//
+	wire debug = 1'b1;
+
+	reg [7:0] mem [255:0]; // initiate memory
+	reg [7:0] mem_adr;   // memory address
+	reg [7:0] mem_do;    // memory data output
+
+	reg sta, d_sta;
+	reg sto, d_sto;
+
+	reg [7:0] sr;        // 8bit shift register
+	reg       rw;        // read/write direction
+
+	wire      my_adr;    // my address called ??
+	wire      i2c_reset; // i2c-statemachine reset
+	reg [2:0] bit_cnt;   // 3bit downcounter
+	wire      acc_done;  // 8bits transfered
+	reg       ld;        // load downcounter
+
+	reg       sda_o;     // sda-drive level
+	wire      sda_dly;   // delayed version of sda
+
+	// statemachine declaration
+	parameter idle        = 3'b000;
+	parameter slave_ack   = 3'b001;
+	parameter get_mem_adr = 3'b010;
+	parameter gma_ack     = 3'b011;
+	parameter data        = 3'b100;
+	parameter data_ack    = 3'b101;
+
+	reg [2:0] state; // synopsys enum_state
+
+	//
+	// module body
+	//
+
+	initial
+	begin
+	   sda_o = 1'b1;
+	   state = idle;
+	end
+
+	// generate shift register
+	always @(posedge scl)
+	  sr <= #1 {sr[6:0],sda};
+
+	//detect my_address
+	assign my_adr = (sr[7:1] == I2C_ADR);
+	// FIXME: This should not be a generic assign, but rather
+	// qualified on address transfer phase and probably reset by stop
+
+	//generate bit-counter
+	always @(posedge scl)
+	  if(ld)
+	    bit_cnt <= #1 3'b111;
+	  else
+	    bit_cnt <= #1 bit_cnt - 3'h1;
+
+	//generate access done signal
+	assign acc_done = !(|bit_cnt);
+
+	// generate delayed version of sda
+	// this model assumes a hold time for sda after the falling edge of scl.
+	// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
+	// with regards to scl. If the data changes coincident with the clock, the
+	// acknowledge is missed
+	// Fix by Michael Sosnoski
+	assign #1 sda_dly = sda;
+
+
+	//detect start condition
+	always @(negedge sda)
+	  if(scl)
+	    begin
+	        sta   <= #1 1'b1;
+		d_sta <= #1 1'b0;
+		sto   <= #1 1'b0;
+
+	        if(debug)
+	          $display("DEBUG i2c_slave; start condition detected at %t", $time);
+	    end
+	  else
+	    sta <= #1 1'b0;
+
+	always @(posedge scl)
+	  d_sta <= #1 sta;
+
+	// detect stop condition
+	always @(posedge sda)
+	  if(scl)
+	    begin
+	       sta <= #1 1'b0;
+	       sto <= #1 1'b1;
+
+	       if(debug)
+	         $display("DEBUG i2c_slave; stop condition detected at %t", $time);
+	    end
+	  else
+	    sto <= #1 1'b0;
+
+	//generate i2c_reset signal
+	assign i2c_reset = sta || sto;
+
+	// generate statemachine
+	always @(negedge scl or posedge sto)
+	  if (sto || (sta && !d_sta) )
+	    begin
+	        state <= #1 idle; // reset statemachine
+
+	        sda_o <= #1 1'b1;
+	        ld    <= #1 1'b1;
+	    end
+	  else
+	    begin
+	        // initial settings
+	        sda_o <= #1 1'b1;
+	        ld    <= #1 1'b0;
+
+	        case(state) // synopsys full_case parallel_case
+	            idle: // idle state
+	              if (acc_done && my_adr)
+	                begin
+	                    state <= #1 slave_ack;
+	                    rw <= #1 sr[0];
+	                    sda_o <= #1 1'b0; // generate i2c_ack
+
+	                    #2;
+	                    if(debug && rw)
+	                      $display("DEBUG i2c_slave; command byte received (read) at %t", $time);
+	                    if(debug && !rw)
+	                      $display("DEBUG i2c_slave; command byte received (write) at %t", $time);
+
+	                    if(rw)
+	                      begin
+	                          mem_do <= #1 mem[mem_adr];
+
+	                          if(debug)
+	                            begin
+	                                #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
+	                                #2 $display("DEBUG i2c_slave; memcheck [%x]=%x", mem_adr, mem[mem_adr]);
+	                            end
+	                      end
+	                end
+
+	            slave_ack:
+	              begin
+	                  if(rw)
+	                    begin
+	                        state <= #1 data;
+	                        sda_o <= #1 mem_do[7];
+	                    end
+	                  else
+	                    state <= #1 get_mem_adr;
+
+	                  ld    <= #1 1'b1;
+	              end
+
+	            get_mem_adr: // wait for memory address
+	              if(acc_done)
+	                begin
+	                    state <= #1 gma_ack;
+	                    mem_adr <= #1 sr; // store memory address
+	                    sda_o <= #1 !(sr <= 255); // generate i2c_ack, for valid address
+
+	                    if(debug)
+	                      #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
+	                end
+
+	            gma_ack:
+	              begin
+	                  state <= #1 data;
+	                  ld    <= #1 1'b1;
+	              end
+
+	            data: // receive or drive data
+	              begin
+	                  if(rw)
+	                    sda_o <= #1 mem_do[7];
+
+	                  if(acc_done)
+	                    begin
+	                        state <= #1 data_ack;
+	                        mem_adr <= #2 mem_adr + 8'h1;
+	                        sda_o <= #1 (rw && (mem_adr <= 255) ); // send ack on write, receive ack on read
+
+	                        if(rw)
+	                          begin
+	                              #3 mem_do <= mem[mem_adr];
+
+	                              if(debug)
+	                                #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
+	                          end
+
+	                        if(!rw)
+	                          begin
+	                              mem[ mem_adr ] <= #1 sr; // store data in memory
+
+	                              if(debug)
+	                                #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
+	                          end
+	                    end
+	              end
+
+	            data_ack:
+	              begin
+	                  ld <= #1 1'b1;
+
+	                  if(rw)
+	                    if(sr[0]) // read operation && master send NACK
+	                      begin
+	                          state <= #1 idle;
+	                          sda_o <= #1 1'b1;
+	                      end
+	                    else
+	                      begin
+	                          state <= #1 data;
+	                          sda_o <= #1 mem_do[7];
+	                      end
+	                  else
+	                    begin
+	                        state <= #1 data;
+	                        sda_o <= #1 1'b1;
+	                    end
+	              end
+
+	        endcase
+	    end
+
+	// read data from memory
+	always @(posedge scl)
+	  if(!acc_done && rw)
+	    mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
+
+	// generate tri-states
+	assign sda = sda_o ? 1'bz : 1'b0;
+
+
+	//
+	// Timing checks
+	//
+
+	wire tst_sto = sto;
+	wire tst_sta = sta;
+
+	specify
+	  specparam normal_scl_low  = 4700,
+	            normal_scl_high = 4000,
+	            normal_tsu_sta  = 4700,
+	            normal_thd_sta  = 4000,
+	            normal_tsu_sto  = 4000,
+	            normal_tbuf     = 4700,
+
+	            fast_scl_low  = 1300,
+	            fast_scl_high =  600,
+	            fast_tsu_sta  = 1300,
+	            fast_thd_sta  =  600,
+	            fast_tsu_sto  =  600,
+	            fast_tbuf     = 1300;
+
+	  $width(negedge scl, normal_scl_low);  // scl low time
+	  $width(posedge scl, normal_scl_high); // scl high time
+
+	  $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start
+	  $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start
+	  $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop
+
+	  $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time
+	endspecify
+
+endmodule
+
+
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index 635b188..5289713 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -30,6 +30,7 @@
 UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
 
 ## SYNTACORE FIRMWARE
 SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -65,7 +66,7 @@
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH)  \
 	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
 	$< -o $@ 
 else  
 	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index dadfcab..e5253b2 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -180,7 +180,7 @@
     reg_mprj_globl_reg4  = 0x2F172242;
 
     // Remove All Reset
-    reg_mprj_wbhost_reg0 = 0xF;
+    reg_mprj_wbhost_reg0 = 0x1F;
 
 
     // configure the user uart
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 169f2a8..6d503fc 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -437,10 +437,10 @@
 	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
 	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
           
-	force uut.mprj.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force uut.mprj.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -462,6 +462,21 @@
 	force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
 	force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
 
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VNB = VSS;
+
 	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_clkbuf_sdram.VGND =VSS;
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
new file mode 100644
index 0000000..7955725
--- /dev/null
+++ b/verilog/dv/user_i2cm/Makefile
@@ -0,0 +1,97 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = user_i2cm
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_uart.c -o user_uart.o
+	riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+	riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+	riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex
+	riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump
+	rm crt_tcm.o user_uart.o
+ifeq ($(SIM),RTL)
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+else  
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
+
+%.bin: %.elf
+	${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_i2cm/run_iverilog b/verilog/dv/user_i2cm/run_iverilog
new file mode 100755
index 0000000..3ae1ffd
--- /dev/null
+++ b/verilog/dv/user_i2cm/run_iverilog
@@ -0,0 +1,37 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_uart.c -o user_uart.o
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+
+riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+
+riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex
+
+riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump
+
+rm crt_tcm.o user_uart.o
+
+#iverilog with waveform dump
+iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_i2cm_tb.v -o user_i2cm_tb.vvp
+
+
+
+vvp user_i2cm_tb.vvp | tee test.log
+
+\rm -rf user_i2cm_tb.vvp
diff --git a/verilog/dv/user_i2cm/uprj_netlists.v b/verilog/dv/user_i2cm/uprj_netlists.v
new file mode 100644
index 0000000..bea5a49
--- /dev/null
+++ b/verilog/dv/user_i2cm/uprj_netlists.v
@@ -0,0 +1,130 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads 
+`include "defines.v"
+       `define USE_POWER_PINS
+       `define UNIT_DELAY #0.1
+
+`ifdef GL
+       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+       `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
+
+        `include "glbl_cfg.v"
+        `include "sdram.v"
+        `include "spi_master.v"
+        `include "uart_i2cm.v"
+        `include "wb_interconnect.v"
+        `include "user_project_wrapper.v"
+        `include "syntacore.v"
+        `include "wb_host.v"
+	`include "clk_skew_adjust.v"
+	`include "clk_buf.v"
+
+`else
+     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+
+     `include "spi_master/src/spim_top.sv"
+     `include "spi_master/src/spim_if.sv"
+     `include "spi_master/src/spim_fifo.sv"
+     `include "spi_master/src/spim_regs.sv"
+     `include "spi_master/src/spim_clkgen.sv"
+     `include "spi_master/src/spim_ctrl.sv"
+     `include "spi_master/src/spim_rx.sv"
+     `include "spi_master/src/spim_tx.sv"
+
+     `include "uart/src/uart_core.sv"
+     `include "uart/src/uart_cfg.sv"
+     `include "uart/src/uart_rxfsm.sv"
+     `include "uart/src/uart_txfsm.sv"
+     `include "lib/async_fifo_th.sv"  
+     `include "lib/reset_sync.sv"  
+     `include "lib/double_sync_low.v"  
+     `include "lib/clk_buf.v"  
+
+     `include "i2cm/src/core/i2cm_bit_ctrl.v"
+     `include "i2cm/src/core/i2cm_byte_ctrl.v"
+     `include "i2cm/src/core/i2cm_top.v"
+
+     `include "uart_i2c/src/uart_i2c_top.sv"
+
+     `include "sdram_ctrl/src/top/sdrc_top.v" 
+     `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
+     `include "lib/async_fifo.sv"  
+     `include "sdram_ctrl/src/core/sdrc_core.v"
+     `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
+     `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
+     `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
+     `include "sdram_ctrl/src/core/sdrc_req_gen.v"
+     `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
+
+     `include "lib/registers.v"
+     `include "lib/clk_ctl.v"
+     `include "digital_core/src/glbl_cfg.sv"
+
+     `include "wb_host/src/wb_host.sv"
+     `include "lib/async_wb.sv"
+
+     `include "lib/wb_stagging.sv"
+     `include "wb_interconnect/src/wb_arb.sv"
+     `include "wb_interconnect/src/wb_interconnect.sv"
+
+
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
+     `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
+     `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
+     `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
+     `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
+     `include "syntacore/scr1/src/core/scr1_tapc.sv"
+     `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
+     `include "syntacore/scr1/src/core/scr1_core_top.sv"
+     `include "syntacore/scr1/src/core/scr1_dm.sv"
+     `include "syntacore/scr1/src/core/scr1_dmi.sv"
+     `include "syntacore/scr1/src/core/scr1_scu.sv"
+      
+     `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
+     `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
+     `include "syntacore/scr1/src/top/scr1_tcm.sv"
+     `include "syntacore/scr1/src/top/scr1_timer.sv"
+     `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_intf.sv"
+     `include "syntacore/scr1/src/top/scr1_top_wb.sv"
+     `include "lib/sync_fifo.sv"
+
+     `include "user_project_wrapper.v"
+     // we are using netlist file for clk_skew_adjust as it has 
+     // standard cell + power pin
+     `include "gl/clk_skew_adjust.v"
+`endif
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
new file mode 100644
index 0000000..b518419
--- /dev/null
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -0,0 +1,700 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   i2c Master .                                               ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "s25fl256s.sv"
+`include "uprj_netlists.v"
+`include "mt48lc8m8a2.v"
+`include "i2c_slave_model.v"
+
+
+`define ADDR_SPACE_UART  32'h3001_0000
+`define ADDR_SPACE_I2CM  32'h3001_0000
+
+
+module tb_top;
+
+reg            clock         ;
+reg            wb_rst_i      ;
+reg            power1, power2;
+reg            power3, power4;
+
+reg            wbd_ext_cyc_i;  // strobe/request
+reg            wbd_ext_stb_i;  // strobe/request
+reg [31:0]     wbd_ext_adr_i;  // address
+reg            wbd_ext_we_i;  // write
+reg [31:0]     wbd_ext_dat_i;  // data output
+reg [3:0]      wbd_ext_sel_i;  // byte enable
+
+wire [31:0]    wbd_ext_dat_o;  // data input
+wire           wbd_ext_ack_o;  // acknowlegement
+wire           wbd_ext_err_o;  // error
+
+// User I/O
+wire [37:0]    io_oeb        ;
+wire [37:0]    io_out        ;
+wire [37:0]    io_in         ;
+
+wire [37:0]    mprj_io       ;
+wire [7:0]     mprj_io_0     ;
+reg            test_fail     ;
+reg [31:0]     read_data     ;
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+
+integer i,j;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("tb_top.vcd");
+	   	$dumpvars(0, tb_top);
+	   end
+       `endif
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+initial
+begin
+   test_fail = 0;
+
+   #200; // Wait for reset removal
+   repeat (10) @(posedge clock);
+   $display("############################################");
+   $display("   Testing I2CM Read/Write Access           ");
+   $display("############################################");
+   
+
+   repeat (10) @(posedge clock);
+   #1;
+   // Enable I2M Block & WB Reset and Enable I2CM Mux Select
+   wb_user_core_write('h3080_0000,'hA1);
+
+   repeat (100) @(posedge clock);  
+
+    @(posedge  clock);
+    $display("---------- Initialize I2C Master ----------"); 
+
+    //Wrire Prescale registers
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7);  
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),8'h00);  
+    // Core Enable
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h2<<2),8'h80);  
+    
+    // Writing Data
+
+    $display("---------- Writing Data ----------"); 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h20); // Slave Addr + WR  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+     
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h66);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);  
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+   
+   /* Byte1: 12 */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h12);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10); // No Stop + Write  
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+   
+   /* Byte1: 34 */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h34);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10); // No Stop + Write 
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+   /* Byte1: 56 */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h56);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10); // No Stop + Write 
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+   /* Byte1: 78 */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h78);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h50); // Stop + Write 
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+    //Reading Data
+    
+    //Wrire Address
+    $display("---------- Writing Data ----------"); 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h20);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+     
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h66);  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h50);  
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+    //Generate Read
+    $display("---------- Writing Data ----------"); 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h21); // Slave Addr + RD  
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+    /* BYTE-1 : 0x12  */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h20);  // RD + ACK
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+    //Compare received data
+    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h12);  
+     
+    /* BYTE-2 : 0x34  */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h20);  // RD + ACK
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+    //Compare received data
+    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h34);  
+
+    /* BYTE-3 : 0x56  */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4 <<2),8'h20);  // RD + ACK
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
+
+    //Compare received data
+    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h56);  
+
+    /* BYTE-4 : 0x78  */ 
+    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h68);  // STOP + RD + NACK 
+
+    read_data[1] = 1'b1;
+    while(read_data[1]==1)
+      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4 <<2),read_data);  
+
+    //Compare received data
+    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3 <<2),8'h78);  
+
+    repeat(100)@(posedge clock);
+
+
+
+     $display("###################################################");
+     if(test_fail == 0) begin
+        `ifdef GL
+            $display("Monitor: Standalone User I2M Test (GL) Passed");
+        `else
+            $display("Monitor: Standalone User I2M Test (RTL) Passed");
+        `endif
+     end else begin
+         `ifdef GL
+             $display("Monitor: Standalone User I2M Test (GL) Failed");
+         `else
+             $display("Monitor: Standalone User I2M Test (RTL) Failed");
+         `endif
+      end
+     $display("###################################################");
+     #100
+     $finish;
+end
+
+
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('0) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+          
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VNB = VSS;
+
+	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
+	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
+
+	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+
+    end
+`endif    
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[30];
+   wire flash_csb = io_out[31];
+   // Creating Pad Delay
+   wire #1 io_oeb_32 = io_oeb[32];
+   wire #1 io_oeb_33 = io_oeb[33];
+   wire #1 io_oeb_34 = io_oeb[34];
+   wire #1 io_oeb_35 = io_oeb[35];
+   tri  flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+   tri  flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+   tri  flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+   tri  flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+
+   assign io_in[32] = flash_io0;
+   assign io_in[33] = flash_io1;
+   assign io_in[34] = flash_io2;
+   assign io_in[35] = flash_io3;
+
+
+   // Quard flash
+     s25fl256s #(.mem_file_name("user_uart.hex"),
+	         .otp_file_name("none"), 
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb
+       (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+
+
+//------------------------------------------------
+// Integrate the SDRAM 8 BIT Memory
+// -----------------------------------------------
+
+wire [7:0]    Dq                 ; // SDRAM Read/Write Data Bus
+wire [0:0]    sdr_dqm            ; // SDRAM DATA Mask
+wire [1:0]    sdr_ba             ; // SDRAM Bank Select
+wire [12:0]   sdr_addr           ; // SDRAM ADRESS
+wire          sdr_cs_n           ; // chip select
+wire          sdr_cke            ; // clock gate
+wire          sdr_ras_n          ; // ras
+wire          sdr_cas_n          ; // cas
+wire          sdr_we_n           ; // write enable        
+wire          sdram_clk         ;      
+
+assign  Dq[7:0]           =  (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
+assign  sdr_addr[12:0]    =    io_out [20:8]     ;
+assign  sdr_ba[1:0]       =    io_out [22:21]    ;
+assign  sdr_dqm[0]        =    io_out [23]       ;
+assign  sdr_we_n          =    io_out [24]       ;
+assign  sdr_cas_n         =    io_out [25]       ;
+assign  sdr_ras_n         =    io_out [26]       ;
+assign  sdr_cs_n          =    io_out [27]       ;
+assign  sdr_cke           =    io_out [28]       ;
+assign  sdram_clk         =    io_out [29]       ;
+assign  io_in[29]         =    sdram_clk;
+assign  #(1) io_in[7:0]   =    Dq;
+
+// to fix the sdram interface timing issue
+wire #(1) sdram_clk_d   = sdram_clk;
+
+	// SDRAM 8bit
+mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
+          .Dq                 (Dq                 ) , 
+          .Addr               (sdr_addr[11:0]     ), 
+          .Ba                 (sdr_ba             ), 
+          .Clk                (sdram_clk_d        ), 
+          .Cke                (sdr_cke            ), 
+          .Cs_n               (sdr_cs_n           ), 
+          .Ras_n              (sdr_ras_n          ), 
+          .Cas_n              (sdr_cas_n          ), 
+          .We_n               (sdr_we_n           ), 
+          .Dqm                (sdr_dqm            )
+     );
+
+
+//---------------------------
+//  UART Agent integration
+// --------------------------
+tri scl,sda;
+
+assign scl   = (io_oeb[36] == 1'b0) ? io_out[36]: 1'bz;
+assign sda  =  (io_oeb[37] == 1'b0) ? io_out[37] : 1'bz;
+assign io_in[37]  =  sda;
+assign io_in[36]  =  scl;
+
+pullup p1(scl); // pullup scl line
+pullup p2(sda); // pullup sda line
+
+ 
+i2c_slave_model u_i2c_slave (
+	.scl   (scl), 
+	.sda   (sda)
+       );
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  //$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_cmp;
+input [31:0] address;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data === cmp_data) begin
+     $display("STATUS: DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  end else begin
+     $display("ERROR: DEBUG WB USER ACCESS READ Address : %x, Exp Data : %x Rxd Data: ",address,cmp_data,data);
+     test_fail= 1;
+     #100
+     $finish;
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+
+wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c.u_uart_core.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c.u_uart_core.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c.u_uart_core.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c.u_uart_core.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c.u_uart_core.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c.u_uart_core.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c.u_uart_core.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_i2cm/user_uart.c b/verilog/dv/user_i2cm/user_uart.c
new file mode 100644
index 0000000..b60311c
--- /dev/null
+++ b/verilog/dv/user_i2cm/user_uart.c
@@ -0,0 +1,59 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t  long
+
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x30000004)
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x30000008)
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x3000000C)
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x30000010)
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x30000014)
+#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x30000018)
+#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x3000001C)
+#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x30000020)
+#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x30000024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+
+#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
+#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
+#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
+#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
+#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
+#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
+#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
+#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
+#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
+
+int main()
+{
+
+    while(1) {
+       // Check UART RX fifo has data, if available loop back the data
+       if(reg_mprj_uart_reg8 != 0) { 
+	   reg_mprj_uart_reg5 = reg_mprj_uart_reg6;
+       }
+    }
+
+    return 0;
+}
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index a3a1ac8..79260aa 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -31,6 +31,7 @@
 UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
 
 ## SYNTACORE FIRMWARE
 SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -66,7 +67,7 @@
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
 	$< -o $@ 
 else  
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index ea393bf..bea5a49 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -15,11 +15,10 @@
 
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
-`define USE_POWER_PINS
-`define UNIT_DELAY #0.1
+       `define USE_POWER_PINS
+       `define UNIT_DELAY #0.1
 
 `ifdef GL
-
        `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
        `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
        `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
@@ -29,7 +28,7 @@
         `include "glbl_cfg.v"
         `include "sdram.v"
         `include "spi_master.v"
-        `include "uart.v"
+        `include "uart_i2cm.v"
         `include "wb_interconnect.v"
         `include "user_project_wrapper.v"
         `include "syntacore.v"
@@ -38,7 +37,6 @@
 	`include "clk_buf.v"
 
 `else
-
      `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
      `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
      `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
@@ -63,6 +61,12 @@
      `include "lib/double_sync_low.v"  
      `include "lib/clk_buf.v"  
 
+     `include "i2cm/src/core/i2cm_bit_ctrl.v"
+     `include "i2cm/src/core/i2cm_byte_ctrl.v"
+     `include "i2cm/src/core/i2cm_top.v"
+
+     `include "uart_i2c/src/uart_i2c_top.sv"
+
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
      `include "lib/async_fifo.sv"  
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index e11cffd..0f0cf53 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -307,10 +307,10 @@
 	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
 	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -332,6 +332,21 @@
 	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
 
+	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VNB = VSS;
+
 	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
@@ -509,13 +524,13 @@
 wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
 wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
 
-wire        wbd_uart_stb_i  = u_top.u_uart_core.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_core.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_core.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_core.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_core.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_core.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_core.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c.u_uart_core.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c.u_uart_core.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c.u_uart_core.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c.u_uart_core.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c.u_uart_core.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c.u_uart_core.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c.u_uart_core.reg_be;
 
 `endif
 
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index 7fca4c3..04cb921 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -31,6 +31,7 @@
 UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
 
 ## SYNTACORE FIRMWARE
 SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -66,7 +67,7 @@
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
 	$< -o $@ 
 else  
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
index ea393bf..bea5a49 100644
--- a/verilog/dv/user_spi/uprj_netlists.v
+++ b/verilog/dv/user_spi/uprj_netlists.v
@@ -15,11 +15,10 @@
 
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
-`define USE_POWER_PINS
-`define UNIT_DELAY #0.1
+       `define USE_POWER_PINS
+       `define UNIT_DELAY #0.1
 
 `ifdef GL
-
        `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
        `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
        `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
@@ -29,7 +28,7 @@
         `include "glbl_cfg.v"
         `include "sdram.v"
         `include "spi_master.v"
-        `include "uart.v"
+        `include "uart_i2cm.v"
         `include "wb_interconnect.v"
         `include "user_project_wrapper.v"
         `include "syntacore.v"
@@ -38,7 +37,6 @@
 	`include "clk_buf.v"
 
 `else
-
      `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
      `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
      `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
@@ -63,6 +61,12 @@
      `include "lib/double_sync_low.v"  
      `include "lib/clk_buf.v"  
 
+     `include "i2cm/src/core/i2cm_bit_ctrl.v"
+     `include "i2cm/src/core/i2cm_byte_ctrl.v"
+     `include "i2cm/src/core/i2cm_top.v"
+
+     `include "uart_i2c/src/uart_i2c_top.sv"
+
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
      `include "lib/async_fifo.sv"  
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 17d3292..ca0fd97 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -1169,10 +1169,10 @@
 	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
 	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -1194,6 +1194,21 @@
 	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
 
+	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VNB = VSS;
+
 	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
@@ -1405,13 +1420,13 @@
 wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
 wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
 
-wire        wbd_uart_stb_i  = u_top.u_uart_core.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_core.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_core.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_core.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_core.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_core.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_core.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c.reg_be;
 
 `endif
 
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 1f5b0c3..c9afd5e 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -31,6 +31,7 @@
 UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
 
 ## SYNTACORE FIRMWARE
 SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -66,7 +67,7 @@
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
 	$< -o $@ 
 else  
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/user_uart/run_iverilog b/verilog/dv/user_uart/run_iverilog
index 15548a4..3ce562e 100755
--- a/verilog/dv/user_uart/run_iverilog
+++ b/verilog/dv/user_uart/run_iverilog
@@ -28,7 +28,7 @@
 rm crt_tcm.o user_uart.o
 
 #iverilog with waveform dump
-iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
 
 
 #iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I  ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index aedc4d8..bea5a49 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -28,7 +28,7 @@
         `include "glbl_cfg.v"
         `include "sdram.v"
         `include "spi_master.v"
-        `include "uart.v"
+        `include "uart_i2cm.v"
         `include "wb_interconnect.v"
         `include "user_project_wrapper.v"
         `include "syntacore.v"
@@ -61,6 +61,12 @@
      `include "lib/double_sync_low.v"  
      `include "lib/clk_buf.v"  
 
+     `include "i2cm/src/core/i2cm_bit_ctrl.v"
+     `include "i2cm/src/core/i2cm_byte_ctrl.v"
+     `include "i2cm/src/core/i2cm_top.v"
+
+     `include "uart_i2c/src/uart_i2c_top.sv"
+
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
      `include "lib/async_fifo.sv"  
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 85c0aa7..c3efb15 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -150,7 +150,7 @@
 	   initial begin
 	   	$dumpfile("risc_boot.vcd");
 	   	$dumpvars(1, user_uart_tb);
-	   	$dumpvars(0, user_uart_tb.u_top.u_riscv_top);
+	   	$dumpvars(0, user_uart_tb.u_top);
 	   end
        `endif
 
@@ -189,7 +189,7 @@
    repeat (2) @(posedge clock);
    #1;
    // Remove all the reset
-   wb_user_core_write('h3080_0000,'hF);
+   wb_user_core_write('h3080_0000,'h1F);
 
    repeat (16000) @(posedge clock);  // wait for Processor Get Ready
    tb_uart.uart_init;
@@ -347,10 +347,10 @@
 	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
 	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -372,6 +372,21 @@
 	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
 
+	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VGND =VSS;
+	force u_top.u_wb_host.u_buf_uart_i2c_sel.VNB = VSS;
+
 	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
@@ -565,13 +580,13 @@
 wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
 wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
 
-wire        wbd_uart_stb_i  = u_top.u_uart_core.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_core.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_core.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_core.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_core.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_core.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_core.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c.reg_be;
 
 `endif
 
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index d156539..cb66907 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -29,6 +29,7 @@
 UPRJ_BEHAVIOURAL_MODELS = ../
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
 
 ## RISCV GCC 
 GCC_PATH?=/ef/apps/bin
@@ -53,7 +54,7 @@
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
 	$< -o $@ 
 else  
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 7b12e0e..80538fe 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -221,10 +221,10 @@
 	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
 	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
           
-	force uut.mprj.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force uut.mprj.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force uut.mprj.u_uart_i2c.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -246,6 +246,21 @@
 	force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
 	force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
 
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_uart_i2c_sel.VNB = VSS;
+
 	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_clkbuf_sdram.VGND =VSS;
diff --git a/verilog/gl/uart_i2cm.v b/verilog/gl/uart_i2cm.v
new file mode 100644
index 0000000..832efaf
--- /dev/null
+++ b/verilog/gl/uart_i2cm.v
@@ -0,0 +1,70275 @@
+module uart_i2c_top (app_clk,
+    i2c_rstn,
+    reg_ack,
+    reg_be,
+    reg_cs,
+    reg_wr,
+    uart_i2c_sel,
+    uart_rstn,
+    vccd1,
+    vssd1,
+    io_in,
+    io_oeb,
+    io_out,
+    reg_addr,
+    reg_rdata,
+    reg_wdata);
+ input app_clk;
+ input i2c_rstn;
+ output reg_ack;
+ input reg_be;
+ input reg_cs;
+ input reg_wr;
+ input uart_i2c_sel;
+ input uart_rstn;
+ input vccd1;
+ input vssd1;
+ input [1:0] io_in;
+ output [1:0] io_oeb;
+ output [1:0] io_out;
+ input [3:0] reg_addr;
+ output [7:0] reg_rdata;
+ input [7:0] reg_wdata;
+
+ sky130_fd_sc_hd__inv_2 _2939_ (.A(\u_i2cm.cr[1] ),
+    .Y(_0541_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2940_ (.A(reg_addr[0]),
+    .Y(_0542_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2941_ (.A(psn_net_108),
+    .X(_0543_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2942_ (.A(reg_addr[1]),
+    .X(_0544_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2943_ (.A(_0544_),
+    .Y(_0545_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2944_ (.A(psn_net_137),
+    .X(_0546_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2945_ (.A(reg_addr[2]),
+    .X(_0547_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _2946_ (.A(psn_net_176),
+    .B(_0546_),
+    .C(_0547_),
+    .X(_0548_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2947_ (.A(_0548_),
+    .X(_0549_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2948_ (.A(_0549_),
+    .X(_0550_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2949_ (.A(reg_wr),
+    .Y(_0551_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2950_ (.A(\u_i2cm.wb_ack_o ),
+    .Y(_0552_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2951_ (.A(_0551_),
+    .B(_0552_),
+    .X(_0553_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2952_ (.A(_0553_),
+    .X(_0554_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2953_ (.A(_0554_),
+    .X(_0555_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _2954_ (.A1(\u_i2cm.core_en ),
+    .A2(_0550_),
+    .B1(_0555_),
+    .X(_0556_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2955_ (.A(reg_wdata[1]),
+    .X(_0557_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2956_ (.A(_0557_),
+    .X(_0558_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _2957_ (.A(reg_wr),
+    .B(\u_i2cm.wb_ack_o ),
+    .C(\u_i2cm.core_en ),
+    .D(_0550_),
+    .X(_0559_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2958_ (.A(_0559_),
+    .X(_0560_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _2959_ (.A1_N(_0541_),
+    .A2_N(_0556_),
+    .B1(_0558_),
+    .B2(_0560_),
+    .X(_0531_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2960_ (.A(\u_i2cm.cr[0] ),
+    .Y(_0561_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2961_ (.A(reg_wdata[0]),
+    .X(_0562_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2962_ (.A(_0562_),
+    .X(_0563_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _2963_ (.A1_N(_0561_),
+    .A2_N(_0556_),
+    .B1(_0563_),
+    .B2(_0560_),
+    .X(_0530_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2964_ (.A(\u_i2cm.cr[7] ),
+    .Y(_0564_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2965_ (.A(\u_i2cm.i2c_al ),
+    .X(_0565_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2966_ (.A(_0565_),
+    .X(_0566_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2967_ (.A(\u_i2cm.done ),
+    .B(_0566_),
+    .X(_0567_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _2968_ (.A1(_0555_),
+    .A2(_0567_),
+    .B1(_0559_),
+    .X(_0568_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2969_ (.A(reg_wdata[7]),
+    .X(_0569_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2970_ (.A(_0569_),
+    .X(_0570_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2971_ (.A(_0559_),
+    .X(_0571_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _2972_ (.A1_N(_0564_),
+    .A2_N(_0568_),
+    .B1(_0570_),
+    .B2(_0571_),
+    .X(_0529_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2973_ (.A(\u_i2cm.cr[6] ),
+    .Y(_0572_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2974_ (.A(reg_wdata[6]),
+    .X(_0573_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2975_ (.A(_0573_),
+    .X(_0574_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _2976_ (.A1_N(_0572_),
+    .A2_N(_0568_),
+    .B1(_0574_),
+    .B2(_0571_),
+    .X(_0528_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2977_ (.A(\u_i2cm.cr[5] ),
+    .Y(_0575_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2978_ (.A(reg_wdata[5]),
+    .X(_0576_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2979_ (.A(_0576_),
+    .X(_0577_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _2980_ (.A1_N(_0575_),
+    .A2_N(_0568_),
+    .B1(_0577_),
+    .B2(_0571_),
+    .X(_0527_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2981_ (.A(\u_i2cm.cr[4] ),
+    .Y(_0578_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2982_ (.A(reg_wdata[4]),
+    .X(_0579_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2983_ (.A(_0579_),
+    .X(_0580_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _2984_ (.A1_N(_0578_),
+    .A2_N(_0568_),
+    .B1(_0580_),
+    .B2(_0571_),
+    .X(_0526_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2985_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.clk_en ),
+    .Y(_0581_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _2986_ (.A1(\u_i2cm.u_byte_ctrl.core_cmd[3] ),
+    .A2(_0581_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cmd_stop ),
+    .B2(\u_i2cm.u_byte_ctrl.u_bit_ctrl.clk_en ),
+    .X(_0525_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _2987_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[13] ),
+    .Y(_0582_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _2988_ (.A(_0582_),
+    .X(_0583_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _2989_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[1] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[0] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[2] ),
+    .X(_0584_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2990_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[3] ),
+    .B(_0584_),
+    .X(_0585_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2991_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[4] ),
+    .B(_0585_),
+    .X(_0586_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2992_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[5] ),
+    .B(_0586_),
+    .X(_0587_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2993_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[6] ),
+    .B(_0587_),
+    .X(_0588_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2994_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[7] ),
+    .B(_0588_),
+    .X(_0589_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2995_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[8] ),
+    .B(_0589_),
+    .X(_0590_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2996_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[9] ),
+    .B(_0590_),
+    .X(_0591_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2997_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[10] ),
+    .B(_0591_),
+    .X(_0592_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2998_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[11] ),
+    .B(_0592_),
+    .X(_0593_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _2999_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[12] ),
+    .B(_0593_),
+    .X(_0594_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3000_ (.A(_0594_),
+    .Y(_0595_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3001_ (.A(_0595_),
+    .X(_0596_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3002_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.filter_cnt[13] ),
+    .B(_0594_),
+    .X(_0597_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3003_ (.A(_0597_),
+    .X(_0598_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3004_ (.A(_0598_),
+    .X(_0599_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3005_ (.A1(_0583_),
+    .A2(_0596_),
+    .A3(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSCL[1] ),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSCL[2] ),
+    .B2(_0599_),
+    .X(_0524_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3006_ (.A1(_0583_),
+    .A2(_0596_),
+    .A3(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSCL[0] ),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSCL[1] ),
+    .B2(_0599_),
+    .X(_0523_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3007_ (.A1(_0583_),
+    .A2(_0596_),
+    .A3(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cSCL[1] ),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSCL[0] ),
+    .B2(_0599_),
+    .X(_0522_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3008_ (.A1(_0583_),
+    .A2(_0596_),
+    .A3(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSDA[1] ),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSDA[2] ),
+    .B2(_0599_),
+    .X(_0521_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3009_ (.A(_0595_),
+    .X(_0600_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3010_ (.A1(_0582_),
+    .A2(_0600_),
+    .A3(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSDA[0] ),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSDA[1] ),
+    .B2(_0598_),
+    .X(_0520_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3011_ (.A1(_0582_),
+    .A2(_0600_),
+    .A3(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cSDA[1] ),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.fSDA[0] ),
+    .B2(_0598_),
+    .X(_0519_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3012_ (.A(\u_uart_core.txd ),
+    .Y(_0601_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3013_ (.A(\u_uart_core.u_txfsm.divcnt[0] ),
+    .B(\u_uart_core.u_txfsm.divcnt[1] ),
+    .C(\u_uart_core.u_txfsm.divcnt[3] ),
+    .D(\u_uart_core.u_txfsm.divcnt[2] ),
+    .X(_0602_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3014_ (.A(_0602_),
+    .X(_0603_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3015_ (.A(\u_uart_core.cfg_tx_enable ),
+    .Y(_0604_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3016_ (.A1(_0604_),
+    .A2(\u_uart_core.tx_fifo_rd_empty ),
+    .B1(\u_uart_core.u_txfsm.txstate[0] ),
+    .X(_0605_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3017_ (.A(\u_uart_core.u_txfsm.txstate[4] ),
+    .Y(_0606_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3018_ (.A(\u_uart_core.u_txfsm.txstate[1] ),
+    .Y(_0607_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3019_ (.A(\u_uart_core.u_txfsm.txstate[2] ),
+    .Y(_0608_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3020_ (.A(\u_uart_core.u_txfsm.txstate[3] ),
+    .Y(_0609_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3021_ (.A(\u_uart_core.u_txfsm.txstate[0] ),
+    .Y(_0610_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3022_ (.A(_0609_),
+    .B(_0610_),
+    .X(_0611_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _3023_ (.A(_0606_),
+    .B(_0607_),
+    .C(_0608_),
+    .D(_0611_),
+    .X(_0612_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3024_ (.A(_0603_),
+    .B(_0605_),
+    .C(_0612_),
+    .X(_0613_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3025_ (.A(_0613_),
+    .Y(_0614_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3026_ (.A(\u_uart_core.u_txfsm.cnt[2] ),
+    .X(_0615_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3027_ (.A(\u_uart_core.u_txfsm.cnt[1] ),
+    .Y(_0616_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3028_ (.A(\u_uart_core.u_txfsm.cnt[0] ),
+    .Y(_0617_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3029_ (.A(\u_uart_core.u_txfsm.txdata[1] ),
+    .B(_0617_),
+    .X(_0618_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3030_ (.A(\u_uart_core.u_txfsm.txdata[0] ),
+    .B(\u_uart_core.u_txfsm.cnt[0] ),
+    .X(_0619_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3031_ (.A(_0616_),
+    .B(_0618_),
+    .C(_0619_),
+    .X(_0620_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3032_ (.A(\u_uart_core.u_txfsm.cnt[1] ),
+    .X(_0621_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3033_ (.A(\u_uart_core.u_txfsm.cnt[0] ),
+    .X(_0622_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3034_ (.A(\u_uart_core.u_txfsm.txdata[2] ),
+    .B(_0622_),
+    .X(_0623_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3035_ (.A(\u_uart_core.u_txfsm.txdata[3] ),
+    .B(_0617_),
+    .X(_0624_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3036_ (.A(_0621_),
+    .B(_0623_),
+    .C(_0624_),
+    .X(_0625_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3037_ (.A(_0615_),
+    .B(_0620_),
+    .C(_0625_),
+    .X(_0626_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3038_ (.A(\u_uart_core.u_txfsm.cnt[2] ),
+    .Y(_0627_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3039_ (.A(\u_uart_core.u_txfsm.txdata[7] ),
+    .B(_0617_),
+    .X(_0628_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3040_ (.A(\u_uart_core.u_txfsm.txdata[6] ),
+    .B(_0622_),
+    .X(_0629_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3041_ (.A(_0621_),
+    .B(_0628_),
+    .C(_0629_),
+    .X(_0630_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3042_ (.A(\u_uart_core.u_txfsm.txdata[4] ),
+    .B(_0622_),
+    .X(_0631_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3043_ (.A(_0617_),
+    .X(_0632_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3044_ (.A(\u_uart_core.u_txfsm.txdata[5] ),
+    .B(_0632_),
+    .X(_0633_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3045_ (.A(_0616_),
+    .B(_0631_),
+    .C(_0633_),
+    .X(_0634_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3046_ (.A(_0627_),
+    .B(_0630_),
+    .C(_0634_),
+    .X(_0635_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3047_ (.A(\u_uart_core.u_txfsm.txstate[3] ),
+    .B(_0626_),
+    .C(_0635_),
+    .X(_0636_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3048_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_be0.gen_bit_reg[4].u_bit_reg.data_out ),
+    .Y(_0637_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3049_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_be0.gen_bit_reg[3].u_bit_reg.data_out ),
+    .X(_0638_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3050_ (.A(\u_uart_core.u_txfsm.txdata[7] ),
+    .Y(_0639_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3051_ (.A1_N(_0639_),
+    .A2_N(\u_uart_core.u_txfsm.txdata[6] ),
+    .B1(_0639_),
+    .B2(\u_uart_core.u_txfsm.txdata[6] ),
+    .X(_0640_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3052_ (.A1_N(\u_uart_core.u_txfsm.txdata[3] ),
+    .A2_N(\u_uart_core.u_txfsm.txdata[2] ),
+    .B1(\u_uart_core.u_txfsm.txdata[3] ),
+    .B2(\u_uart_core.u_txfsm.txdata[2] ),
+    .X(_0641_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3053_ (.A1_N(_0640_),
+    .A2_N(_0641_),
+    .B1(_0640_),
+    .B2(_0641_),
+    .X(_0642_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3054_ (.A1_N(\u_uart_core.u_txfsm.txdata[5] ),
+    .A2_N(\u_uart_core.u_txfsm.txdata[4] ),
+    .B1(\u_uart_core.u_txfsm.txdata[5] ),
+    .B2(\u_uart_core.u_txfsm.txdata[4] ),
+    .X(_0643_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3055_ (.A1_N(\u_uart_core.u_txfsm.txdata[1] ),
+    .A2_N(\u_uart_core.u_txfsm.txdata[0] ),
+    .B1(\u_uart_core.u_txfsm.txdata[1] ),
+    .B2(\u_uart_core.u_txfsm.txdata[0] ),
+    .X(_0644_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3056_ (.A1_N(_0643_),
+    .A2_N(_0644_),
+    .B1(_0643_),
+    .B2(_0644_),
+    .X(_0645_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3057_ (.A1_N(_0642_),
+    .A2_N(_0645_),
+    .B1(_0642_),
+    .B2(_0645_),
+    .X(_0646_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3058_ (.A(_0637_),
+    .B(_0638_),
+    .C(_0646_),
+    .X(_0647_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _3059_ (.A1(_0637_),
+    .A2(_0638_),
+    .B1(_0646_),
+    .Y(_0648_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3060_ (.A(\u_uart_core.u_txfsm.txstate[2] ),
+    .B(_0647_),
+    .C(_0648_),
+    .X(_0649_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3061_ (.A(\u_uart_core.u_txfsm.txstate[4] ),
+    .B(\u_uart_core.u_txfsm.txstate[1] ),
+    .C(_0636_),
+    .D(_0649_),
+    .X(_0650_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3062_ (.A1_N(_0601_),
+    .A2_N(_0614_),
+    .B1(_0614_),
+    .B2(_0650_),
+    .X(_0518_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3063_ (.A(\u_uart_core.tx_fifo_rd ),
+    .X(_0651_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3064_ (.A(_0651_),
+    .X(_0652_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3065_ (.A(_0603_),
+    .Y(_0653_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3066_ (.A(_0611_),
+    .B(_0605_),
+    .X(_0654_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3067_ (.A(_0609_),
+    .X(_0655_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3068_ (.A(_0604_),
+    .B(\u_uart_core.tx_fifo_rd_empty ),
+    .C(_0602_),
+    .X(_0656_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3069_ (.A(_0610_),
+    .B(_0656_),
+    .X(_0657_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3070_ (.A(_0657_),
+    .Y(_0658_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3071_ (.A1(_0652_),
+    .A2(_0653_),
+    .A3(_0654_),
+    .B1(_0655_),
+    .B2(_0658_),
+    .X(_0517_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3072_ (.A(\u_uart_core.u_txfsm.txstate[0] ),
+    .X(_0659_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3073_ (.A(_0656_),
+    .Y(_0660_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3074_ (.A(_0660_),
+    .X(_0661_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3075_ (.A(\u_uart_core.u_txfifo.rd_ptr[3] ),
+    .X(_0662_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3076_ (.A(\u_uart_core.u_txfifo.rd_ptr[1] ),
+    .X(_0663_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3077_ (.A(_0663_),
+    .X(_0664_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3078_ (.A(\u_uart_core.u_txfifo.rd_ptr[0] ),
+    .Y(_0665_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3079_ (.A(_0665_),
+    .X(_0666_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3080_ (.A(_0666_),
+    .X(_0667_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3081_ (.A(_0667_),
+    .B(\u_uart_core.u_txfifo.mem[11][7] ),
+    .X(_0668_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3082_ (.A(\u_uart_core.u_txfifo.rd_ptr[0] ),
+    .X(_0669_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3083_ (.A(_0669_),
+    .X(_0670_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3084_ (.A(_0670_),
+    .X(_0671_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3085_ (.A(_0671_),
+    .B(\u_uart_core.u_txfifo.mem[10][7] ),
+    .X(_0672_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3086_ (.A(_0664_),
+    .B(_0668_),
+    .C(_0672_),
+    .X(_0673_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3087_ (.A(\u_uart_core.u_txfifo.rd_ptr[1] ),
+    .Y(_0674_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3088_ (.A(_0674_),
+    .X(_0675_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3089_ (.A(_0675_),
+    .X(_0676_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3090_ (.A(_0665_),
+    .X(_0677_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3091_ (.A(_0677_),
+    .X(_0678_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3092_ (.A(_0678_),
+    .B(\u_uart_core.u_txfifo.mem[9][7] ),
+    .X(_0679_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3093_ (.A(_0670_),
+    .X(_0680_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3094_ (.A(_0680_),
+    .B(\u_uart_core.u_txfifo.mem[8][7] ),
+    .X(_0681_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3095_ (.A(_0676_),
+    .B(_0679_),
+    .C(_0681_),
+    .X(_0682_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3096_ (.A(\u_uart_core.u_txfifo.rd_ptr[2] ),
+    .X(_0683_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3097_ (.A(_0683_),
+    .X(_0684_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3098_ (.A(_0673_),
+    .B(_0682_),
+    .C(_0684_),
+    .X(_0685_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3099_ (.A(_0674_),
+    .X(_0686_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3100_ (.A(_0686_),
+    .X(_0687_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3101_ (.A(_0687_),
+    .X(_0688_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3102_ (.A(_0665_),
+    .X(_0689_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3103_ (.A(_0689_),
+    .X(_0690_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3104_ (.A(_0690_),
+    .X(_0691_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3105_ (.A(_0691_),
+    .B(\u_uart_core.u_txfifo.mem[13][7] ),
+    .X(_0692_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3106_ (.A(\u_uart_core.u_txfifo.rd_ptr[0] ),
+    .X(_0693_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3107_ (.A(_0693_),
+    .X(_0694_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3108_ (.A(_0694_),
+    .X(_0695_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3109_ (.A(_0695_),
+    .B(\u_uart_core.u_txfifo.mem[12][7] ),
+    .X(_0696_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3110_ (.A(_0688_),
+    .B(_0692_),
+    .C(_0696_),
+    .X(_0697_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3111_ (.A(_0663_),
+    .X(_0698_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3112_ (.A(_0689_),
+    .X(_0699_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3113_ (.A(_0699_),
+    .X(_0700_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3114_ (.A(_0700_),
+    .B(\u_uart_core.u_txfifo.mem[15][7] ),
+    .X(_0701_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3115_ (.A(_0693_),
+    .X(_0702_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3116_ (.A(_0702_),
+    .X(_0703_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3117_ (.A(_0703_),
+    .B(\u_uart_core.u_txfifo.mem[14][7] ),
+    .X(_0704_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3118_ (.A(_0698_),
+    .B(_0701_),
+    .C(_0704_),
+    .X(_0705_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3119_ (.A(\u_uart_core.u_txfifo.rd_ptr[2] ),
+    .Y(_0706_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3120_ (.A(_0706_),
+    .X(_0707_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3121_ (.A(_0707_),
+    .X(_0708_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3122_ (.A(_0708_),
+    .X(_0709_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3123_ (.A(_0697_),
+    .B(_0705_),
+    .C(_0709_),
+    .X(_0710_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3124_ (.A(_0687_),
+    .X(_0711_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3125_ (.A(_0690_),
+    .X(_0712_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3126_ (.A(_0712_),
+    .B(\u_uart_core.u_txfifo.mem[5][7] ),
+    .X(_0713_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3127_ (.A(_0693_),
+    .X(_0714_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3128_ (.A(_0714_),
+    .X(_0715_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3129_ (.A(_0715_),
+    .B(\u_uart_core.u_txfifo.mem[4][7] ),
+    .X(_0716_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3130_ (.A(_0711_),
+    .B(_0713_),
+    .C(_0716_),
+    .X(_0717_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3131_ (.A(\u_uart_core.u_txfifo.rd_ptr[1] ),
+    .X(_0718_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3132_ (.A(_0718_),
+    .X(_0719_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3133_ (.A(_0719_),
+    .X(_0720_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3134_ (.A(_0690_),
+    .X(_0721_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3135_ (.A(_0721_),
+    .B(\u_uart_core.u_txfifo.mem[7][7] ),
+    .X(_0722_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3136_ (.A(_0714_),
+    .X(_0723_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3137_ (.A(_0723_),
+    .B(\u_uart_core.u_txfifo.mem[6][7] ),
+    .X(_0724_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3138_ (.A(_0720_),
+    .B(_0722_),
+    .C(_0724_),
+    .X(_0725_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3139_ (.A(_0708_),
+    .X(_0726_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3140_ (.A(_0717_),
+    .B(_0725_),
+    .C(_0726_),
+    .X(_0727_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3141_ (.A(\u_uart_core.u_txfifo.rd_ptr[3] ),
+    .Y(_0728_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3142_ (.A(_0728_),
+    .X(_0729_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3143_ (.A(_0729_),
+    .X(_0730_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3144_ (.A(_0718_),
+    .X(_0731_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3145_ (.A(_0689_),
+    .X(_0732_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3146_ (.A(_0732_),
+    .B(\u_uart_core.u_txfifo.mem[3][7] ),
+    .X(_0733_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3147_ (.A(_0694_),
+    .B(\u_uart_core.u_txfifo.mem[2][7] ),
+    .X(_0734_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3148_ (.A(_0731_),
+    .B(_0733_),
+    .C(_0734_),
+    .X(_0735_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3149_ (.A(_0699_),
+    .B(\u_uart_core.u_txfifo.mem[1][7] ),
+    .X(_0736_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3150_ (.A(_0669_),
+    .X(_0737_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3151_ (.A(_0737_),
+    .B(\u_uart_core.u_txfifo.mem[0][7] ),
+    .X(_0738_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3152_ (.A(_0687_),
+    .B(_0736_),
+    .C(_0738_),
+    .X(_0739_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3153_ (.A(\u_uart_core.u_txfifo.rd_ptr[2] ),
+    .X(_0740_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3154_ (.A(_0735_),
+    .B(_0739_),
+    .C(_0740_),
+    .X(_0741_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3155_ (.A(_0730_),
+    .B(_0741_),
+    .X(_0742_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3156_ (.A1(_0662_),
+    .A2(_0685_),
+    .A3(_0710_),
+    .B1(_0727_),
+    .B2(_0742_),
+    .X(_0743_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3157_ (.A(_0657_),
+    .X(_0744_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3158_ (.A1(_0659_),
+    .A2(_0661_),
+    .A3(_0743_),
+    .B1(\u_uart_core.u_txfsm.txdata[7] ),
+    .B2(_0744_),
+    .X(_0516_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3159_ (.A(_0677_),
+    .X(_0745_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3160_ (.A(_0745_),
+    .B(\u_uart_core.u_txfifo.mem[11][6] ),
+    .X(_0746_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3161_ (.A(_0670_),
+    .X(_0747_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3162_ (.A(_0747_),
+    .B(\u_uart_core.u_txfifo.mem[10][6] ),
+    .X(_0748_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3163_ (.A(_0664_),
+    .B(_0746_),
+    .C(_0748_),
+    .X(_0749_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3164_ (.A(_0686_),
+    .X(_0750_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3165_ (.A(_0677_),
+    .X(_0751_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3166_ (.A(_0751_),
+    .B(\u_uart_core.u_txfifo.mem[9][6] ),
+    .X(_0752_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3167_ (.A(_0670_),
+    .X(_0753_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3168_ (.A(_0753_),
+    .B(\u_uart_core.u_txfifo.mem[8][6] ),
+    .X(_0754_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3169_ (.A(_0750_),
+    .B(_0752_),
+    .C(_0754_),
+    .X(_0755_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3170_ (.A(_0749_),
+    .B(_0755_),
+    .C(_0684_),
+    .X(_0756_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3171_ (.A(_0687_),
+    .X(_0757_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3172_ (.A(_0732_),
+    .X(_0758_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3173_ (.A(_0758_),
+    .B(\u_uart_core.u_txfifo.mem[13][6] ),
+    .X(_0759_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3174_ (.A(_0694_),
+    .X(_0760_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3175_ (.A(_0760_),
+    .B(\u_uart_core.u_txfifo.mem[12][6] ),
+    .X(_0761_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3176_ (.A(_0757_),
+    .B(_0759_),
+    .C(_0761_),
+    .X(_0762_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3177_ (.A(_0699_),
+    .X(_0763_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3178_ (.A(_0763_),
+    .B(\u_uart_core.u_txfifo.mem[15][6] ),
+    .X(_0764_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3179_ (.A(_0702_),
+    .X(_0765_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3180_ (.A(_0765_),
+    .B(\u_uart_core.u_txfifo.mem[14][6] ),
+    .X(_0766_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3181_ (.A(_0698_),
+    .B(_0764_),
+    .C(_0766_),
+    .X(_0767_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3182_ (.A(_0762_),
+    .B(_0767_),
+    .C(_0709_),
+    .X(_0768_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3183_ (.A(_0686_),
+    .X(_0769_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3184_ (.A(_0769_),
+    .X(_0770_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3185_ (.A(_0677_),
+    .X(_0771_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3186_ (.A(_0771_),
+    .X(_0772_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3187_ (.A(_0772_),
+    .B(\u_uart_core.u_txfifo.mem[5][6] ),
+    .X(_0773_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3188_ (.A(_0714_),
+    .X(_0774_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3189_ (.A(_0774_),
+    .B(\u_uart_core.u_txfifo.mem[4][6] ),
+    .X(_0775_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3190_ (.A(_0770_),
+    .B(_0773_),
+    .C(_0775_),
+    .X(_0776_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3191_ (.A(_0719_),
+    .X(_0777_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3192_ (.A(_0690_),
+    .X(_0778_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3193_ (.A(_0778_),
+    .B(\u_uart_core.u_txfifo.mem[7][6] ),
+    .X(_0779_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3194_ (.A(_0714_),
+    .X(_0780_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3195_ (.A(_0780_),
+    .B(\u_uart_core.u_txfifo.mem[6][6] ),
+    .X(_0781_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3196_ (.A(_0777_),
+    .B(_0779_),
+    .C(_0781_),
+    .X(_0782_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3197_ (.A(_0776_),
+    .B(_0782_),
+    .C(_0726_),
+    .X(_0783_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3198_ (.A(_0732_),
+    .B(\u_uart_core.u_txfifo.mem[3][6] ),
+    .X(_0784_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3199_ (.A(_0694_),
+    .B(\u_uart_core.u_txfifo.mem[2][6] ),
+    .X(_0785_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3200_ (.A(_0731_),
+    .B(_0784_),
+    .C(_0785_),
+    .X(_0786_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3201_ (.A(_0674_),
+    .X(_0787_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3202_ (.A(_0665_),
+    .X(_0788_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3203_ (.A(_0788_),
+    .B(\u_uart_core.u_txfifo.mem[1][6] ),
+    .X(_0789_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3204_ (.A(_0737_),
+    .B(\u_uart_core.u_txfifo.mem[0][6] ),
+    .X(_0790_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3205_ (.A(_0787_),
+    .B(_0789_),
+    .C(_0790_),
+    .X(_0791_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3206_ (.A(_0786_),
+    .B(_0791_),
+    .C(_0740_),
+    .X(_0792_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3207_ (.A(_0730_),
+    .B(_0792_),
+    .X(_0793_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3208_ (.A1(_0662_),
+    .A2(_0756_),
+    .A3(_0768_),
+    .B1(_0783_),
+    .B2(_0793_),
+    .X(_0794_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3209_ (.A1(_0659_),
+    .A2(_0661_),
+    .A3(_0794_),
+    .B1(\u_uart_core.u_txfsm.txdata[6] ),
+    .B2(_0744_),
+    .X(_0515_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3210_ (.A(_0745_),
+    .B(\u_uart_core.u_txfifo.mem[11][5] ),
+    .X(_0795_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3211_ (.A(_0747_),
+    .B(\u_uart_core.u_txfifo.mem[10][5] ),
+    .X(_0796_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3212_ (.A(_0664_),
+    .B(_0795_),
+    .C(_0796_),
+    .X(_0797_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3213_ (.A(_0751_),
+    .B(\u_uart_core.u_txfifo.mem[9][5] ),
+    .X(_0798_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3214_ (.A(_0753_),
+    .B(\u_uart_core.u_txfifo.mem[8][5] ),
+    .X(_0799_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3215_ (.A(_0750_),
+    .B(_0798_),
+    .C(_0799_),
+    .X(_0800_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3216_ (.A(_0683_),
+    .X(_0801_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3217_ (.A(_0797_),
+    .B(_0800_),
+    .C(_0801_),
+    .X(_0802_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3218_ (.A(_0758_),
+    .B(\u_uart_core.u_txfifo.mem[13][5] ),
+    .X(_0803_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3219_ (.A(_0760_),
+    .B(\u_uart_core.u_txfifo.mem[12][5] ),
+    .X(_0804_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3220_ (.A(_0757_),
+    .B(_0803_),
+    .C(_0804_),
+    .X(_0805_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3221_ (.A(_0763_),
+    .B(\u_uart_core.u_txfifo.mem[15][5] ),
+    .X(_0806_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3222_ (.A(_0765_),
+    .B(\u_uart_core.u_txfifo.mem[14][5] ),
+    .X(_0807_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3223_ (.A(_0698_),
+    .B(_0806_),
+    .C(_0807_),
+    .X(_0808_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3224_ (.A(_0805_),
+    .B(_0808_),
+    .C(_0709_),
+    .X(_0809_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3225_ (.A(_0772_),
+    .B(\u_uart_core.u_txfifo.mem[5][5] ),
+    .X(_0810_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3226_ (.A(_0774_),
+    .B(\u_uart_core.u_txfifo.mem[4][5] ),
+    .X(_0811_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3227_ (.A(_0770_),
+    .B(_0810_),
+    .C(_0811_),
+    .X(_0812_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3228_ (.A(_0778_),
+    .B(\u_uart_core.u_txfifo.mem[7][5] ),
+    .X(_0813_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3229_ (.A(_0780_),
+    .B(\u_uart_core.u_txfifo.mem[6][5] ),
+    .X(_0814_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3230_ (.A(_0777_),
+    .B(_0813_),
+    .C(_0814_),
+    .X(_0815_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3231_ (.A(_0812_),
+    .B(_0815_),
+    .C(_0726_),
+    .X(_0816_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3232_ (.A(_0732_),
+    .B(\u_uart_core.u_txfifo.mem[3][5] ),
+    .X(_0817_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3233_ (.A(_0669_),
+    .X(_0818_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3234_ (.A(_0818_),
+    .B(\u_uart_core.u_txfifo.mem[2][5] ),
+    .X(_0819_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3235_ (.A(_0731_),
+    .B(_0817_),
+    .C(_0819_),
+    .X(_0820_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3236_ (.A(_0788_),
+    .B(\u_uart_core.u_txfifo.mem[1][5] ),
+    .X(_0821_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3237_ (.A(_0737_),
+    .B(\u_uart_core.u_txfifo.mem[0][5] ),
+    .X(_0822_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3238_ (.A(_0787_),
+    .B(_0821_),
+    .C(_0822_),
+    .X(_0823_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3239_ (.A(\u_uart_core.u_txfifo.rd_ptr[2] ),
+    .X(_0824_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3240_ (.A(_0820_),
+    .B(_0823_),
+    .C(_0824_),
+    .X(_0825_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3241_ (.A(_0730_),
+    .B(_0825_),
+    .X(_0826_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3242_ (.A1(_0662_),
+    .A2(_0802_),
+    .A3(_0809_),
+    .B1(_0816_),
+    .B2(_0826_),
+    .X(_0827_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3243_ (.A1(_0659_),
+    .A2(_0661_),
+    .A3(_0827_),
+    .B1(\u_uart_core.u_txfsm.txdata[5] ),
+    .B2(_0744_),
+    .X(_0514_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3244_ (.A(\u_uart_core.u_txfifo.rd_ptr[3] ),
+    .X(_0828_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3245_ (.A(_0745_),
+    .B(\u_uart_core.u_txfifo.mem[11][4] ),
+    .X(_0829_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3246_ (.A(_0747_),
+    .B(\u_uart_core.u_txfifo.mem[10][4] ),
+    .X(_0830_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3247_ (.A(_0664_),
+    .B(_0829_),
+    .C(_0830_),
+    .X(_0831_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3248_ (.A(_0751_),
+    .B(\u_uart_core.u_txfifo.mem[9][4] ),
+    .X(_0832_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3249_ (.A(_0753_),
+    .B(\u_uart_core.u_txfifo.mem[8][4] ),
+    .X(_0833_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3250_ (.A(_0750_),
+    .B(_0832_),
+    .C(_0833_),
+    .X(_0834_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3251_ (.A(_0831_),
+    .B(_0834_),
+    .C(_0801_),
+    .X(_0835_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3252_ (.A(_0758_),
+    .B(\u_uart_core.u_txfifo.mem[13][4] ),
+    .X(_0836_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3253_ (.A(_0760_),
+    .B(\u_uart_core.u_txfifo.mem[12][4] ),
+    .X(_0837_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3254_ (.A(_0757_),
+    .B(_0836_),
+    .C(_0837_),
+    .X(_0838_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3255_ (.A(_0763_),
+    .B(\u_uart_core.u_txfifo.mem[15][4] ),
+    .X(_0839_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3256_ (.A(_0765_),
+    .B(\u_uart_core.u_txfifo.mem[14][4] ),
+    .X(_0840_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3257_ (.A(_0698_),
+    .B(_0839_),
+    .C(_0840_),
+    .X(_0841_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3258_ (.A(_0838_),
+    .B(_0841_),
+    .C(_0709_),
+    .X(_0842_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3259_ (.A(_0772_),
+    .B(\u_uart_core.u_txfifo.mem[5][4] ),
+    .X(_0843_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3260_ (.A(_0774_),
+    .B(\u_uart_core.u_txfifo.mem[4][4] ),
+    .X(_0844_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3261_ (.A(_0770_),
+    .B(_0843_),
+    .C(_0844_),
+    .X(_0845_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3262_ (.A(_0778_),
+    .B(\u_uart_core.u_txfifo.mem[7][4] ),
+    .X(_0846_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3263_ (.A(_0780_),
+    .B(\u_uart_core.u_txfifo.mem[6][4] ),
+    .X(_0847_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3264_ (.A(_0777_),
+    .B(_0846_),
+    .C(_0847_),
+    .X(_0848_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3265_ (.A(_0845_),
+    .B(_0848_),
+    .C(_0726_),
+    .X(_0849_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3266_ (.A(_0689_),
+    .X(_0850_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3267_ (.A(_0850_),
+    .B(\u_uart_core.u_txfifo.mem[3][4] ),
+    .X(_0851_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3268_ (.A(_0818_),
+    .B(\u_uart_core.u_txfifo.mem[2][4] ),
+    .X(_0852_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3269_ (.A(_0731_),
+    .B(_0851_),
+    .C(_0852_),
+    .X(_0853_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3270_ (.A(_0788_),
+    .B(\u_uart_core.u_txfifo.mem[1][4] ),
+    .X(_0854_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3271_ (.A(_0737_),
+    .B(\u_uart_core.u_txfifo.mem[0][4] ),
+    .X(_0855_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3272_ (.A(_0787_),
+    .B(_0854_),
+    .C(_0855_),
+    .X(_0856_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3273_ (.A(_0853_),
+    .B(_0856_),
+    .C(_0824_),
+    .X(_0857_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3274_ (.A(_0730_),
+    .B(_0857_),
+    .X(_0858_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3275_ (.A1(_0828_),
+    .A2(_0835_),
+    .A3(_0842_),
+    .B1(_0849_),
+    .B2(_0858_),
+    .X(_0859_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3276_ (.A(_0657_),
+    .X(_0860_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3277_ (.A1(_0659_),
+    .A2(_0661_),
+    .A3(_0859_),
+    .B1(\u_uart_core.u_txfsm.txdata[4] ),
+    .B2(_0860_),
+    .X(_0513_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3278_ (.A(\u_uart_core.u_txfsm.txstate[0] ),
+    .X(_0861_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3279_ (.A(_0660_),
+    .X(_0862_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3280_ (.A(_0718_),
+    .X(_0863_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3281_ (.A(_0745_),
+    .B(\u_uart_core.u_txfifo.mem[11][3] ),
+    .X(_0864_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3282_ (.A(_0747_),
+    .B(\u_uart_core.u_txfifo.mem[10][3] ),
+    .X(_0865_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3283_ (.A(_0863_),
+    .B(_0864_),
+    .C(_0865_),
+    .X(_0866_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3284_ (.A(_0751_),
+    .B(\u_uart_core.u_txfifo.mem[9][3] ),
+    .X(_0867_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3285_ (.A(_0753_),
+    .B(\u_uart_core.u_txfifo.mem[8][3] ),
+    .X(_0868_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3286_ (.A(_0750_),
+    .B(_0867_),
+    .C(_0868_),
+    .X(_0869_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3287_ (.A(_0866_),
+    .B(_0869_),
+    .C(_0801_),
+    .X(_0870_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3288_ (.A(_0758_),
+    .B(\u_uart_core.u_txfifo.mem[13][3] ),
+    .X(_0871_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3289_ (.A(_0760_),
+    .B(\u_uart_core.u_txfifo.mem[12][3] ),
+    .X(_0872_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3290_ (.A(_0757_),
+    .B(_0871_),
+    .C(_0872_),
+    .X(_0873_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3291_ (.A(_0663_),
+    .X(_0874_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3292_ (.A(_0763_),
+    .B(\u_uart_core.u_txfifo.mem[15][3] ),
+    .X(_0875_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3293_ (.A(_0765_),
+    .B(\u_uart_core.u_txfifo.mem[14][3] ),
+    .X(_0876_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3294_ (.A(_0874_),
+    .B(_0875_),
+    .C(_0876_),
+    .X(_0877_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3295_ (.A(_0707_),
+    .X(_0878_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3296_ (.A(_0873_),
+    .B(_0877_),
+    .C(_0878_),
+    .X(_0879_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3297_ (.A(_0772_),
+    .B(\u_uart_core.u_txfifo.mem[5][3] ),
+    .X(_0880_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3298_ (.A(_0774_),
+    .B(\u_uart_core.u_txfifo.mem[4][3] ),
+    .X(_0881_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3299_ (.A(_0770_),
+    .B(_0880_),
+    .C(_0881_),
+    .X(_0882_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3300_ (.A(_0778_),
+    .B(\u_uart_core.u_txfifo.mem[7][3] ),
+    .X(_0883_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3301_ (.A(_0780_),
+    .B(\u_uart_core.u_txfifo.mem[6][3] ),
+    .X(_0884_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3302_ (.A(_0777_),
+    .B(_0883_),
+    .C(_0884_),
+    .X(_0885_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3303_ (.A(_0708_),
+    .X(_0886_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3304_ (.A(_0882_),
+    .B(_0885_),
+    .C(_0886_),
+    .X(_0887_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3305_ (.A(_0729_),
+    .X(_0888_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3306_ (.A(_0718_),
+    .X(_0889_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3307_ (.A(_0850_),
+    .B(\u_uart_core.u_txfifo.mem[3][3] ),
+    .X(_0890_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3308_ (.A(_0818_),
+    .B(\u_uart_core.u_txfifo.mem[2][3] ),
+    .X(_0891_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3309_ (.A(_0889_),
+    .B(_0890_),
+    .C(_0891_),
+    .X(_0892_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3310_ (.A(_0788_),
+    .B(\u_uart_core.u_txfifo.mem[1][3] ),
+    .X(_0893_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3311_ (.A(_0669_),
+    .X(_0894_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3312_ (.A(_0894_),
+    .B(\u_uart_core.u_txfifo.mem[0][3] ),
+    .X(_0895_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3313_ (.A(_0787_),
+    .B(_0893_),
+    .C(_0895_),
+    .X(_0896_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3314_ (.A(_0892_),
+    .B(_0896_),
+    .C(_0824_),
+    .X(_0897_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3315_ (.A(_0888_),
+    .B(_0897_),
+    .X(_0898_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3316_ (.A1(_0828_),
+    .A2(_0870_),
+    .A3(_0879_),
+    .B1(_0887_),
+    .B2(_0898_),
+    .X(_0899_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3317_ (.A1(_0861_),
+    .A2(_0862_),
+    .A3(_0899_),
+    .B1(\u_uart_core.u_txfsm.txdata[3] ),
+    .B2(_0860_),
+    .X(_0512_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3318_ (.A(_0678_),
+    .B(\u_uart_core.u_txfifo.mem[11][2] ),
+    .X(_0900_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3319_ (.A(_0680_),
+    .B(\u_uart_core.u_txfifo.mem[10][2] ),
+    .X(_0901_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3320_ (.A(_0863_),
+    .B(_0900_),
+    .C(_0901_),
+    .X(_0902_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3321_ (.A(_0771_),
+    .B(\u_uart_core.u_txfifo.mem[9][2] ),
+    .X(_0903_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3322_ (.A(_0693_),
+    .X(_0904_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3323_ (.A(_0904_),
+    .B(\u_uart_core.u_txfifo.mem[8][2] ),
+    .X(_0905_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3324_ (.A(_0769_),
+    .B(_0903_),
+    .C(_0905_),
+    .X(_0906_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3325_ (.A(_0902_),
+    .B(_0906_),
+    .C(_0801_),
+    .X(_0907_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3326_ (.A(_0700_),
+    .B(\u_uart_core.u_txfifo.mem[13][2] ),
+    .X(_0908_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3327_ (.A(_0703_),
+    .B(\u_uart_core.u_txfifo.mem[12][2] ),
+    .X(_0909_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3328_ (.A(_0676_),
+    .B(_0908_),
+    .C(_0909_),
+    .X(_0910_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3329_ (.A(_0667_),
+    .B(\u_uart_core.u_txfifo.mem[15][2] ),
+    .X(_0911_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3330_ (.A(_0671_),
+    .B(\u_uart_core.u_txfifo.mem[14][2] ),
+    .X(_0912_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3331_ (.A(_0874_),
+    .B(_0911_),
+    .C(_0912_),
+    .X(_0913_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3332_ (.A(_0910_),
+    .B(_0913_),
+    .C(_0878_),
+    .X(_0914_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3333_ (.A(_0721_),
+    .B(\u_uart_core.u_txfifo.mem[5][2] ),
+    .X(_0915_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3334_ (.A(_0723_),
+    .B(\u_uart_core.u_txfifo.mem[4][2] ),
+    .X(_0916_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3335_ (.A(_0688_),
+    .B(_0915_),
+    .C(_0916_),
+    .X(_0917_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3336_ (.A(_0663_),
+    .X(_0918_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3337_ (.A(_0691_),
+    .B(\u_uart_core.u_txfifo.mem[7][2] ),
+    .X(_0919_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3338_ (.A(_0695_),
+    .B(\u_uart_core.u_txfifo.mem[6][2] ),
+    .X(_0920_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3339_ (.A(_0918_),
+    .B(_0919_),
+    .C(_0920_),
+    .X(_0921_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3340_ (.A(_0917_),
+    .B(_0921_),
+    .C(_0886_),
+    .X(_0922_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3341_ (.A(_0850_),
+    .B(\u_uart_core.u_txfifo.mem[3][2] ),
+    .X(_0923_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3342_ (.A(_0818_),
+    .B(\u_uart_core.u_txfifo.mem[2][2] ),
+    .X(_0924_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3343_ (.A(_0889_),
+    .B(_0923_),
+    .C(_0924_),
+    .X(_0925_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3344_ (.A(_0666_),
+    .B(\u_uart_core.u_txfifo.mem[1][2] ),
+    .X(_0926_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3345_ (.A(_0894_),
+    .B(\u_uart_core.u_txfifo.mem[0][2] ),
+    .X(_0927_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3346_ (.A(_0675_),
+    .B(_0926_),
+    .C(_0927_),
+    .X(_0928_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3347_ (.A(_0925_),
+    .B(_0928_),
+    .C(_0824_),
+    .X(_0929_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3348_ (.A(_0888_),
+    .B(_0929_),
+    .X(_0930_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3349_ (.A1(_0828_),
+    .A2(_0907_),
+    .A3(_0914_),
+    .B1(_0922_),
+    .B2(_0930_),
+    .X(_0931_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3350_ (.A1(_0861_),
+    .A2(_0862_),
+    .A3(_0931_),
+    .B1(\u_uart_core.u_txfsm.txdata[2] ),
+    .B2(_0860_),
+    .X(_0511_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3351_ (.A(_0678_),
+    .B(\u_uart_core.u_txfifo.mem[11][1] ),
+    .X(_0932_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3352_ (.A(_0680_),
+    .B(\u_uart_core.u_txfifo.mem[10][1] ),
+    .X(_0933_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3353_ (.A(_0863_),
+    .B(_0932_),
+    .C(_0933_),
+    .X(_0934_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3354_ (.A(_0771_),
+    .B(\u_uart_core.u_txfifo.mem[9][1] ),
+    .X(_0935_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3355_ (.A(_0904_),
+    .B(\u_uart_core.u_txfifo.mem[8][1] ),
+    .X(_0936_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3356_ (.A(_0769_),
+    .B(_0935_),
+    .C(_0936_),
+    .X(_0937_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3357_ (.A(_0934_),
+    .B(_0937_),
+    .C(_0740_),
+    .X(_0938_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3358_ (.A(_0700_),
+    .B(\u_uart_core.u_txfifo.mem[13][1] ),
+    .X(_0939_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3359_ (.A(_0703_),
+    .B(\u_uart_core.u_txfifo.mem[12][1] ),
+    .X(_0940_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3360_ (.A(_0676_),
+    .B(_0939_),
+    .C(_0940_),
+    .X(_0941_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3361_ (.A(_0667_),
+    .B(\u_uart_core.u_txfifo.mem[15][1] ),
+    .X(_0942_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3362_ (.A(_0671_),
+    .B(\u_uart_core.u_txfifo.mem[14][1] ),
+    .X(_0943_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3363_ (.A(_0874_),
+    .B(_0942_),
+    .C(_0943_),
+    .X(_0944_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3364_ (.A(_0941_),
+    .B(_0944_),
+    .C(_0878_),
+    .X(_0945_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3365_ (.A(_0721_),
+    .B(\u_uart_core.u_txfifo.mem[5][1] ),
+    .X(_0946_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3366_ (.A(_0723_),
+    .B(\u_uart_core.u_txfifo.mem[4][1] ),
+    .X(_0947_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3367_ (.A(_0688_),
+    .B(_0946_),
+    .C(_0947_),
+    .X(_0948_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3368_ (.A(_0691_),
+    .B(\u_uart_core.u_txfifo.mem[7][1] ),
+    .X(_0949_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3369_ (.A(_0695_),
+    .B(\u_uart_core.u_txfifo.mem[6][1] ),
+    .X(_0950_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3370_ (.A(_0918_),
+    .B(_0949_),
+    .C(_0950_),
+    .X(_0951_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3371_ (.A(_0948_),
+    .B(_0951_),
+    .C(_0886_),
+    .X(_0952_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3372_ (.A(_0850_),
+    .B(\u_uart_core.u_txfifo.mem[3][1] ),
+    .X(_0953_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3373_ (.A(_0702_),
+    .B(\u_uart_core.u_txfifo.mem[2][1] ),
+    .X(_0954_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3374_ (.A(_0889_),
+    .B(_0953_),
+    .C(_0954_),
+    .X(_0955_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3375_ (.A(_0666_),
+    .B(\u_uart_core.u_txfifo.mem[1][1] ),
+    .X(_0956_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3376_ (.A(_0894_),
+    .B(\u_uart_core.u_txfifo.mem[0][1] ),
+    .X(_0957_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3377_ (.A(_0675_),
+    .B(_0956_),
+    .C(_0957_),
+    .X(_0958_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3378_ (.A(_0955_),
+    .B(_0958_),
+    .C(_0683_),
+    .X(_0959_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3379_ (.A(_0888_),
+    .B(_0959_),
+    .X(_0960_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3380_ (.A1(_0828_),
+    .A2(_0938_),
+    .A3(_0945_),
+    .B1(_0952_),
+    .B2(_0960_),
+    .X(_0961_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3381_ (.A1(_0861_),
+    .A2(_0862_),
+    .A3(_0961_),
+    .B1(\u_uart_core.u_txfsm.txdata[1] ),
+    .B2(_0860_),
+    .X(_0510_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3382_ (.A(_0678_),
+    .B(\u_uart_core.u_txfifo.mem[11][0] ),
+    .X(_0962_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3383_ (.A(_0680_),
+    .B(\u_uart_core.u_txfifo.mem[10][0] ),
+    .X(_0963_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3384_ (.A(_0863_),
+    .B(_0962_),
+    .C(_0963_),
+    .X(_0964_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3385_ (.A(_0771_),
+    .B(\u_uart_core.u_txfifo.mem[9][0] ),
+    .X(_0965_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3386_ (.A(_0904_),
+    .B(\u_uart_core.u_txfifo.mem[8][0] ),
+    .X(_0966_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3387_ (.A(_0769_),
+    .B(_0965_),
+    .C(_0966_),
+    .X(_0967_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3388_ (.A(_0964_),
+    .B(_0967_),
+    .C(_0740_),
+    .X(_0968_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3389_ (.A(_0700_),
+    .B(\u_uart_core.u_txfifo.mem[13][0] ),
+    .X(_0969_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3390_ (.A(_0703_),
+    .B(\u_uart_core.u_txfifo.mem[12][0] ),
+    .X(_0970_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3391_ (.A(_0676_),
+    .B(_0969_),
+    .C(_0970_),
+    .X(_0971_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3392_ (.A(_0667_),
+    .B(\u_uart_core.u_txfifo.mem[15][0] ),
+    .X(_0972_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3393_ (.A(_0671_),
+    .B(\u_uart_core.u_txfifo.mem[14][0] ),
+    .X(_0973_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3394_ (.A(_0874_),
+    .B(_0972_),
+    .C(_0973_),
+    .X(_0974_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3395_ (.A(_0971_),
+    .B(_0974_),
+    .C(_0878_),
+    .X(_0975_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3396_ (.A(_0721_),
+    .B(\u_uart_core.u_txfifo.mem[5][0] ),
+    .X(_0976_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3397_ (.A(_0723_),
+    .B(\u_uart_core.u_txfifo.mem[4][0] ),
+    .X(_0977_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3398_ (.A(_0688_),
+    .B(_0976_),
+    .C(_0977_),
+    .X(_0978_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3399_ (.A(_0691_),
+    .B(\u_uart_core.u_txfifo.mem[7][0] ),
+    .X(_0979_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3400_ (.A(_0695_),
+    .B(\u_uart_core.u_txfifo.mem[6][0] ),
+    .X(_0980_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3401_ (.A(_0918_),
+    .B(_0979_),
+    .C(_0980_),
+    .X(_0981_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3402_ (.A(_0978_),
+    .B(_0981_),
+    .C(_0886_),
+    .X(_0982_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3403_ (.A(_0699_),
+    .B(\u_uart_core.u_txfifo.mem[3][0] ),
+    .X(_0983_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3404_ (.A(_0702_),
+    .B(\u_uart_core.u_txfifo.mem[2][0] ),
+    .X(_0984_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3405_ (.A(_0889_),
+    .B(_0983_),
+    .C(_0984_),
+    .X(_0985_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3406_ (.A(_0666_),
+    .B(\u_uart_core.u_txfifo.mem[1][0] ),
+    .X(_0986_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3407_ (.A(_0894_),
+    .B(\u_uart_core.u_txfifo.mem[0][0] ),
+    .X(_0987_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3408_ (.A(_0675_),
+    .B(_0986_),
+    .C(_0987_),
+    .X(_0988_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3409_ (.A(_0985_),
+    .B(_0988_),
+    .C(_0683_),
+    .X(_0989_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3410_ (.A(_0888_),
+    .B(_0989_),
+    .X(_0990_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3411_ (.A1(\u_uart_core.u_txfifo.rd_ptr[3] ),
+    .A2(_0968_),
+    .A3(_0975_),
+    .B1(_0982_),
+    .B2(_0990_),
+    .X(_0991_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3412_ (.A1(_0861_),
+    .A2(_0862_),
+    .A3(_0991_),
+    .B1(\u_uart_core.u_txfsm.txdata[0] ),
+    .B2(_0657_),
+    .X(_0509_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3413_ (.A(_0616_),
+    .B(_0632_),
+    .X(_0992_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3414_ (.A(_0603_),
+    .B(_0654_),
+    .X(_0993_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _3415_ (.A1(\u_uart_core.u_txfsm.txstate[3] ),
+    .A2(_0992_),
+    .B1(_0993_),
+    .X(_0994_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3416_ (.A(_0632_),
+    .B(_0993_),
+    .X(_0995_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3417_ (.A(_0615_),
+    .B(_0616_),
+    .C(_0655_),
+    .D(_0995_),
+    .X(_0996_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _3418_ (.A1(_0615_),
+    .A2(_0994_),
+    .B1_N(_0996_),
+    .X(_0508_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3419_ (.A(_0995_),
+    .Y(_0997_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3420_ (.A1(_0621_),
+    .A2(_0997_),
+    .B1(_0994_),
+    .X(_0507_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3421_ (.A(_0632_),
+    .B(_0993_),
+    .X(_0998_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3422_ (.A1(_0655_),
+    .A2(_0658_),
+    .B1(_0997_),
+    .C1(_0998_),
+    .X(_0999_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3423_ (.A(_0999_),
+    .Y(_0506_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3424_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[7].u_bit_reg.data_out ),
+    .Y(_1000_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3425_ (.A(reg_addr[0]),
+    .X(_1001_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3426_ (.A(_1001_),
+    .B(_0546_),
+    .C(_0547_),
+    .X(_1002_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3427_ (.A(_1002_),
+    .X(_1003_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3428_ (.A(reg_cs),
+    .Y(_1004_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3429_ (.A(reg_addr[3]),
+    .X(_1005_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3430_ (.A(reg_be),
+    .Y(_1006_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3431_ (.A(_0551_),
+    .B(_1004_),
+    .C(_1005_),
+    .D(_1006_),
+    .X(_1007_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3432_ (.A(_1007_),
+    .X(_1008_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3433_ (.A(_1003_),
+    .B(_1008_),
+    .Y(_1009_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3434_ (.A(_1009_),
+    .X(_1010_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3435_ (.A1_N(_1000_),
+    .A2_N(_1010_),
+    .B1(_0570_),
+    .B2(_1010_),
+    .X(_0505_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3436_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[0].u_bit_reg.data_out ),
+    .Y(_1011_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3437_ (.A(_0543_),
+    .B(psn_net_136),
+    .C(_0547_),
+    .X(_1012_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3438_ (.A(_1012_),
+    .X(_1013_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3439_ (.A(_1008_),
+    .B(_1013_),
+    .Y(_1014_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3440_ (.A(_1014_),
+    .X(_1015_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3441_ (.A1_N(_1011_),
+    .A2_N(_1015_),
+    .B1(_0563_),
+    .B2(_1015_),
+    .X(_0504_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3442_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[1].u_bit_reg.data_out ),
+    .Y(_1016_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3443_ (.A1_N(_1016_),
+    .A2_N(_1015_),
+    .B1(_0558_),
+    .B2(_1015_),
+    .X(_0503_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3444_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[2].u_bit_reg.data_out ),
+    .Y(_1017_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3445_ (.A(_1014_),
+    .X(_1018_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3446_ (.A(reg_wdata[2]),
+    .X(_1019_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3447_ (.A(_1019_),
+    .X(_1020_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3448_ (.A1_N(_1017_),
+    .A2_N(_1018_),
+    .B1(_1020_),
+    .B2(_1018_),
+    .X(_0502_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3449_ (.A(reg_addr[0]),
+    .B(reg_addr[1]),
+    .C(_0547_),
+    .X(_1021_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3450_ (.A(_1021_),
+    .X(_1022_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3451_ (.A(_1022_),
+    .X(_1023_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3452_ (.A(_1008_),
+    .B(_1023_),
+    .Y(_1024_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3453_ (.A(_1024_),
+    .X(_1025_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3454_ (.A1_N(_0637_),
+    .A2_N(_1025_),
+    .B1(_0580_),
+    .B2(_1025_),
+    .X(_0501_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3455_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[0].u_bit_reg.data_out ),
+    .X(_1026_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3456_ (.A(_1026_),
+    .Y(_1027_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3457_ (.A(_1027_),
+    .X(_1028_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3458_ (.A1_N(_1028_),
+    .A2_N(_1010_),
+    .B1(_0563_),
+    .B2(_1010_),
+    .X(_0500_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3459_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[1].u_bit_reg.data_out ),
+    .Y(_1029_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3460_ (.A(_1029_),
+    .X(_1030_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3461_ (.A(_1009_),
+    .X(_1031_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3462_ (.A1_N(_1030_),
+    .A2_N(_1031_),
+    .B1(_0558_),
+    .B2(_1031_),
+    .X(_0499_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3463_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[2].u_bit_reg.data_out ),
+    .Y(_1032_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3464_ (.A1_N(_1032_),
+    .A2_N(_1031_),
+    .B1(_1020_),
+    .B2(_1031_),
+    .X(_0498_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3465_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[3].u_bit_reg.data_out ),
+    .Y(_1033_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3466_ (.A(_1009_),
+    .X(_1034_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3467_ (.A(reg_wdata[3]),
+    .X(_1035_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3468_ (.A(_1035_),
+    .X(_1036_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3469_ (.A1_N(_1033_),
+    .A2_N(_1034_),
+    .B1(_1036_),
+    .B2(_1034_),
+    .X(_0497_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3470_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[4].u_bit_reg.data_out ),
+    .Y(_1037_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3471_ (.A1_N(_1037_),
+    .A2_N(_1034_),
+    .B1(_0580_),
+    .B2(_1034_),
+    .X(_0496_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3472_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[5].u_bit_reg.data_out ),
+    .Y(_1038_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3473_ (.A(_1038_),
+    .X(_1039_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3474_ (.A(_1009_),
+    .X(_1040_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3475_ (.A1_N(_1039_),
+    .A2_N(_1040_),
+    .B1(_0577_),
+    .B2(_1040_),
+    .X(_0495_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3476_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[6].u_bit_reg.data_out ),
+    .Y(_1041_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3477_ (.A1_N(_1041_),
+    .A2_N(_1040_),
+    .B1(_0574_),
+    .B2(_1040_),
+    .X(_0494_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3478_ (.A(\u_uart_core.reg_rdata[7] ),
+    .Y(_1042_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3479_ (.A(reg_wr),
+    .B(_1004_),
+    .C(\u_uart_core.reg_ack ),
+    .X(_1043_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3480_ (.A(_1043_),
+    .Y(_1044_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3481_ (.A(_1043_),
+    .X(_1045_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3482_ (.A(reg_addr[2]),
+    .Y(_1046_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3483_ (.A(psn_net_161),
+    .X(_1047_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3484_ (.A(reg_addr[3]),
+    .Y(_1048_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _3485_ (.A(_0543_),
+    .B(psn_net_138),
+    .C(psn_net_158),
+    .D(_1048_),
+    .X(_1049_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3486_ (.A(_1049_),
+    .X(_1050_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3487_ (.A(_1050_),
+    .X(_1051_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3488_ (.A(_1001_),
+    .B(_0545_),
+    .C(_1005_),
+    .D(_1047_),
+    .X(_1052_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3489_ (.A(_1052_),
+    .Y(_1053_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3490_ (.A(_1053_),
+    .X(_1054_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3491_ (.A(_1054_),
+    .X(_1055_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3492_ (.A(\u_uart_core.u_rxfifo.rd_ptr[3] ),
+    .Y(_1056_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3493_ (.A(_1056_),
+    .X(_1057_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3494_ (.A(_1057_),
+    .X(_1058_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3495_ (.A(_1058_),
+    .X(_1059_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3496_ (.A(\u_uart_core.u_rxfifo.rd_ptr[2] ),
+    .Y(_1060_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3497_ (.A(_1060_),
+    .X(_1061_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3498_ (.A(_1061_),
+    .X(_1062_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3499_ (.A(\u_uart_core.u_rxfifo.rd_ptr[1] ),
+    .X(_1063_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3500_ (.A(_1063_),
+    .X(_1064_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3501_ (.A(_1064_),
+    .X(_1065_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3502_ (.A(\u_uart_core.u_rxfifo.rd_ptr[0] ),
+    .Y(_1066_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3503_ (.A(_1066_),
+    .X(_1067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3504_ (.A(_1067_),
+    .X(_1068_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3505_ (.A(_1068_),
+    .X(_1069_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3506_ (.A(_1069_),
+    .B(\u_uart_core.u_rxfifo.mem[7][7] ),
+    .X(_1070_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3507_ (.A(\u_uart_core.u_rxfifo.rd_ptr[0] ),
+    .X(_1071_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3508_ (.A(_1071_),
+    .X(_1072_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3509_ (.A(_1072_),
+    .X(_1073_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3510_ (.A(_1073_),
+    .X(_1074_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3511_ (.A(_1074_),
+    .B(\u_uart_core.u_rxfifo.mem[6][7] ),
+    .X(_1075_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3512_ (.A(_1065_),
+    .B(_1070_),
+    .C(_1075_),
+    .X(_1076_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3513_ (.A(\u_uart_core.u_rxfifo.rd_ptr[1] ),
+    .Y(_1077_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3514_ (.A(_1077_),
+    .X(_1078_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3515_ (.A(_1078_),
+    .X(_1079_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3516_ (.A(_1079_),
+    .X(_1080_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3517_ (.A(_1080_),
+    .X(_1081_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3518_ (.A(_1071_),
+    .X(_1082_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3519_ (.A(_1082_),
+    .X(_1083_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3520_ (.A(_1083_),
+    .X(_1084_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3521_ (.A(_1084_),
+    .B(\u_uart_core.u_rxfifo.mem[4][7] ),
+    .X(_1085_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3522_ (.A(_1066_),
+    .X(_1086_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3523_ (.A(_1086_),
+    .X(_1087_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3524_ (.A(_1087_),
+    .X(_1088_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3525_ (.A(_1088_),
+    .X(_1089_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3526_ (.A(_1089_),
+    .B(\u_uart_core.u_rxfifo.mem[5][7] ),
+    .X(_1090_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3527_ (.A(_1081_),
+    .B(_1085_),
+    .C(_1090_),
+    .X(_1091_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3528_ (.A(_1062_),
+    .B(_1076_),
+    .C(_1091_),
+    .X(_1092_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3529_ (.A(\u_uart_core.u_rxfifo.rd_ptr[2] ),
+    .X(_1093_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3530_ (.A(_1093_),
+    .X(_1094_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3531_ (.A(_1094_),
+    .X(_1095_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3532_ (.A(_1089_),
+    .B(\u_uart_core.u_rxfifo.mem[1][7] ),
+    .X(_1096_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3533_ (.A(_1084_),
+    .B(\u_uart_core.u_rxfifo.mem[0][7] ),
+    .X(_1097_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3534_ (.A(_1081_),
+    .B(_1096_),
+    .C(_1097_),
+    .X(_1098_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3535_ (.A(\u_uart_core.u_rxfifo.rd_ptr[1] ),
+    .X(_1099_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3536_ (.A(_1099_),
+    .X(_1100_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3537_ (.A(_1100_),
+    .X(_1101_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3538_ (.A(_1101_),
+    .X(_1102_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3539_ (.A(\u_uart_core.u_rxfifo.rd_ptr[0] ),
+    .X(_1103_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3540_ (.A(_1103_),
+    .X(_1104_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3541_ (.A(_1104_),
+    .X(_1105_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3542_ (.A(_1105_),
+    .X(_1106_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3543_ (.A(_1106_),
+    .B(\u_uart_core.u_rxfifo.mem[2][7] ),
+    .X(_1107_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3544_ (.A(_1086_),
+    .X(_1108_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3545_ (.A(_1108_),
+    .X(_1109_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3546_ (.A(_1109_),
+    .X(_1110_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3547_ (.A(_1110_),
+    .B(\u_uart_core.u_rxfifo.mem[3][7] ),
+    .X(_1111_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3548_ (.A(_1102_),
+    .B(_1107_),
+    .C(_1111_),
+    .X(_1112_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3549_ (.A(_1095_),
+    .B(_1098_),
+    .C(_1112_),
+    .X(_1113_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3550_ (.A(_1094_),
+    .X(_1114_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3551_ (.A(_1079_),
+    .X(_1115_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3552_ (.A(_1115_),
+    .X(_1116_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3553_ (.A(_1108_),
+    .X(_1117_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3554_ (.A(_1117_),
+    .X(_1118_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3555_ (.A(_1118_),
+    .B(\u_uart_core.u_rxfifo.mem[9][7] ),
+    .X(_1119_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3556_ (.A(_1104_),
+    .X(_1120_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3557_ (.A(_1120_),
+    .X(_1121_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3558_ (.A(_1121_),
+    .B(\u_uart_core.u_rxfifo.mem[8][7] ),
+    .X(_1122_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3559_ (.A(_1116_),
+    .B(_1119_),
+    .C(_1122_),
+    .X(_1123_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3560_ (.A(_1064_),
+    .X(_1124_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3561_ (.A(_1124_),
+    .X(_1125_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3562_ (.A(_1120_),
+    .X(_1126_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3563_ (.A(_1126_),
+    .B(\u_uart_core.u_rxfifo.mem[10][7] ),
+    .X(_1127_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3564_ (.A(_1117_),
+    .X(_1128_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3565_ (.A(_1128_),
+    .B(\u_uart_core.u_rxfifo.mem[11][7] ),
+    .X(_1129_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3566_ (.A(_1125_),
+    .B(_1127_),
+    .C(_1129_),
+    .X(_1130_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3567_ (.A(_1114_),
+    .B(_1123_),
+    .C(_1130_),
+    .X(_1131_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3568_ (.A(\u_uart_core.u_rxfifo.rd_ptr[3] ),
+    .X(_1132_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3569_ (.A(_1132_),
+    .X(_1133_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3570_ (.A(_1133_),
+    .X(_1134_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3571_ (.A(_1060_),
+    .X(_1135_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3572_ (.A(_1135_),
+    .X(_1136_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3573_ (.A(_1088_),
+    .B(\u_uart_core.u_rxfifo.mem[15][7] ),
+    .X(_1137_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3574_ (.A(_1083_),
+    .B(\u_uart_core.u_rxfifo.mem[14][7] ),
+    .X(_1138_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3575_ (.A(_1101_),
+    .B(_1137_),
+    .C(_1138_),
+    .X(_1139_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3576_ (.A(_1105_),
+    .B(\u_uart_core.u_rxfifo.mem[12][7] ),
+    .X(_1140_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3577_ (.A(_1109_),
+    .B(\u_uart_core.u_rxfifo.mem[13][7] ),
+    .X(_1141_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3578_ (.A(_1080_),
+    .B(_1140_),
+    .C(_1141_),
+    .X(_1142_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3579_ (.A(_1136_),
+    .B(_1139_),
+    .C(_1142_),
+    .X(_1143_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3580_ (.A(_1134_),
+    .B(_1143_),
+    .X(_1144_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3581_ (.A1(_1059_),
+    .A2(_1092_),
+    .A3(_1113_),
+    .B1(_1131_),
+    .B2(_1144_),
+    .X(_1145_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a22oi_4 _3582_ (.A1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[7].u_bit_reg.data_out ),
+    .A2(_1051_),
+    .B1(_1055_),
+    .B2(_1145_),
+    .Y(_1146_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3583_ (.A1(_1042_),
+    .A2(_1044_),
+    .B1(_1045_),
+    .B2(_1146_),
+    .X(_1147_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3584_ (.A(_1147_),
+    .Y(_0493_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3585_ (.A(\u_uart_core.reg_rdata[6] ),
+    .Y(_1148_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3586_ (.A(_1069_),
+    .B(\u_uart_core.u_rxfifo.mem[7][6] ),
+    .X(_1149_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3587_ (.A(_1074_),
+    .B(\u_uart_core.u_rxfifo.mem[6][6] ),
+    .X(_1150_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3588_ (.A(_1065_),
+    .B(_1149_),
+    .C(_1150_),
+    .X(_1151_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3589_ (.A(_1074_),
+    .B(\u_uart_core.u_rxfifo.mem[4][6] ),
+    .X(_1152_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3590_ (.A(_1069_),
+    .B(\u_uart_core.u_rxfifo.mem[5][6] ),
+    .X(_1153_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3591_ (.A(_1115_),
+    .B(_1152_),
+    .C(_1153_),
+    .X(_1154_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3592_ (.A(_1062_),
+    .B(_1151_),
+    .C(_1154_),
+    .X(_1155_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3593_ (.A(_1089_),
+    .B(\u_uart_core.u_rxfifo.mem[1][6] ),
+    .X(_1156_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3594_ (.A(_1084_),
+    .B(\u_uart_core.u_rxfifo.mem[0][6] ),
+    .X(_1157_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3595_ (.A(_1081_),
+    .B(_1156_),
+    .C(_1157_),
+    .X(_1158_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3596_ (.A(_1106_),
+    .B(\u_uart_core.u_rxfifo.mem[2][6] ),
+    .X(_1159_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3597_ (.A(_1110_),
+    .B(\u_uart_core.u_rxfifo.mem[3][6] ),
+    .X(_1160_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3598_ (.A(_1102_),
+    .B(_1159_),
+    .C(_1160_),
+    .X(_1161_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3599_ (.A(_1095_),
+    .B(_1158_),
+    .C(_1161_),
+    .X(_1162_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3600_ (.A(_1118_),
+    .B(\u_uart_core.u_rxfifo.mem[9][6] ),
+    .X(_1163_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3601_ (.A(_1121_),
+    .B(\u_uart_core.u_rxfifo.mem[8][6] ),
+    .X(_1164_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3602_ (.A(_1116_),
+    .B(_1163_),
+    .C(_1164_),
+    .X(_1165_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3603_ (.A(_1126_),
+    .B(\u_uart_core.u_rxfifo.mem[10][6] ),
+    .X(_1166_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3604_ (.A(_1118_),
+    .B(\u_uart_core.u_rxfifo.mem[11][6] ),
+    .X(_1167_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3605_ (.A(_1125_),
+    .B(_1166_),
+    .C(_1167_),
+    .X(_1168_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3606_ (.A(_1114_),
+    .B(_1165_),
+    .C(_1168_),
+    .X(_1169_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3607_ (.A(_1088_),
+    .B(\u_uart_core.u_rxfifo.mem[15][6] ),
+    .X(_1170_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3608_ (.A(_1083_),
+    .B(\u_uart_core.u_rxfifo.mem[14][6] ),
+    .X(_1171_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3609_ (.A(_1101_),
+    .B(_1170_),
+    .C(_1171_),
+    .X(_1172_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3610_ (.A(_1105_),
+    .B(\u_uart_core.u_rxfifo.mem[12][6] ),
+    .X(_1173_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3611_ (.A(_1109_),
+    .B(\u_uart_core.u_rxfifo.mem[13][6] ),
+    .X(_1174_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3612_ (.A(_1080_),
+    .B(_1173_),
+    .C(_1174_),
+    .X(_1175_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3613_ (.A(_1136_),
+    .B(_1172_),
+    .C(_1175_),
+    .X(_1176_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3614_ (.A(_1134_),
+    .B(_1176_),
+    .X(_1177_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3615_ (.A1(_1058_),
+    .A2(_1155_),
+    .A3(_1162_),
+    .B1(_1169_),
+    .B2(_1177_),
+    .X(_1178_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a22oi_4 _3616_ (.A1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[6].u_bit_reg.data_out ),
+    .A2(_1051_),
+    .B1(_1055_),
+    .B2(_1178_),
+    .Y(_1179_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3617_ (.A1(_1148_),
+    .A2(_1044_),
+    .B1(_1045_),
+    .B2(_1179_),
+    .X(_1180_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3618_ (.A(_1180_),
+    .Y(_0492_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3619_ (.A(\u_uart_core.reg_rdata[5] ),
+    .Y(_1181_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3620_ (.A(_1108_),
+    .X(_1182_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3621_ (.A(_1182_),
+    .B(\u_uart_core.u_rxfifo.mem[7][5] ),
+    .X(_1183_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3622_ (.A(_1104_),
+    .X(_1184_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3623_ (.A(_1184_),
+    .B(\u_uart_core.u_rxfifo.mem[6][5] ),
+    .X(_1185_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3624_ (.A(_1065_),
+    .B(_1183_),
+    .C(_1185_),
+    .X(_1186_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3625_ (.A(_1074_),
+    .B(\u_uart_core.u_rxfifo.mem[4][5] ),
+    .X(_1187_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3626_ (.A(_1069_),
+    .B(\u_uart_core.u_rxfifo.mem[5][5] ),
+    .X(_1188_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3627_ (.A(_1115_),
+    .B(_1187_),
+    .C(_1188_),
+    .X(_1189_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3628_ (.A(_1062_),
+    .B(_1186_),
+    .C(_1189_),
+    .X(_1190_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3629_ (.A(_1089_),
+    .B(\u_uart_core.u_rxfifo.mem[1][5] ),
+    .X(_1191_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3630_ (.A(_1084_),
+    .B(\u_uart_core.u_rxfifo.mem[0][5] ),
+    .X(_1192_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3631_ (.A(_1081_),
+    .B(_1191_),
+    .C(_1192_),
+    .X(_1193_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3632_ (.A(_1106_),
+    .B(\u_uart_core.u_rxfifo.mem[2][5] ),
+    .X(_1194_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3633_ (.A(_1110_),
+    .B(\u_uart_core.u_rxfifo.mem[3][5] ),
+    .X(_1195_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3634_ (.A(_1102_),
+    .B(_1194_),
+    .C(_1195_),
+    .X(_1196_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3635_ (.A(_1095_),
+    .B(_1193_),
+    .C(_1196_),
+    .X(_1197_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3636_ (.A(_1110_),
+    .B(\u_uart_core.u_rxfifo.mem[9][5] ),
+    .X(_1198_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3637_ (.A(_1106_),
+    .B(\u_uart_core.u_rxfifo.mem[8][5] ),
+    .X(_1199_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3638_ (.A(_1116_),
+    .B(_1198_),
+    .C(_1199_),
+    .X(_1200_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3639_ (.A(_1121_),
+    .B(\u_uart_core.u_rxfifo.mem[10][5] ),
+    .X(_1201_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3640_ (.A(_1118_),
+    .B(\u_uart_core.u_rxfifo.mem[11][5] ),
+    .X(_1202_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3641_ (.A(_1102_),
+    .B(_1201_),
+    .C(_1202_),
+    .X(_1203_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3642_ (.A(_1095_),
+    .B(_1200_),
+    .C(_1203_),
+    .X(_1204_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3643_ (.A(_1088_),
+    .B(\u_uart_core.u_rxfifo.mem[15][5] ),
+    .X(_1205_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3644_ (.A(_1083_),
+    .B(\u_uart_core.u_rxfifo.mem[14][5] ),
+    .X(_1206_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3645_ (.A(_1101_),
+    .B(_1205_),
+    .C(_1206_),
+    .X(_1207_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3646_ (.A(_1105_),
+    .B(\u_uart_core.u_rxfifo.mem[12][5] ),
+    .X(_1208_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3647_ (.A(_1109_),
+    .B(\u_uart_core.u_rxfifo.mem[13][5] ),
+    .X(_1209_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3648_ (.A(_1080_),
+    .B(_1208_),
+    .C(_1209_),
+    .X(_1210_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3649_ (.A(_1136_),
+    .B(_1207_),
+    .C(_1210_),
+    .X(_1211_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3650_ (.A(_1134_),
+    .B(_1211_),
+    .X(_1212_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3651_ (.A1(_1058_),
+    .A2(_1190_),
+    .A3(_1197_),
+    .B1(_1204_),
+    .B2(_1212_),
+    .X(_1213_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a22oi_4 _3652_ (.A1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[5].u_bit_reg.data_out ),
+    .A2(_1051_),
+    .B1(_1055_),
+    .B2(_1213_),
+    .Y(_1214_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3653_ (.A1(_1181_),
+    .A2(_1044_),
+    .B1(_1043_),
+    .B2(_1214_),
+    .X(_1215_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3654_ (.A(_1215_),
+    .Y(_0491_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3655_ (.A(_1044_),
+    .X(_1216_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3656_ (.A(_1021_),
+    .Y(_1217_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3657_ (.A(_1005_),
+    .B(_1217_),
+    .X(_1218_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3658_ (.A(_1001_),
+    .B(_0544_),
+    .C(reg_addr[3]),
+    .D(psn_net_113),
+    .X(_1219_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3659_ (.A(_1219_),
+    .Y(_1220_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3660_ (.A(reg_addr[2]),
+    .B(reg_addr[1]),
+    .C(psn_net_107),
+    .X(_1221_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3661_ (.A(_1221_),
+    .Y(_1222_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3662_ (.A1(psn_net_139),
+    .A2(_1222_),
+    .B1(_1048_),
+    .X(_1223_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3663_ (.A(_1218_),
+    .B(_1220_),
+    .C(_1223_),
+    .X(_1224_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3664_ (.A(psn_net_170),
+    .X(_1225_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3665_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_be0.gen_bit_reg[4].u_bit_reg.data_out ),
+    .B(_1225_),
+    .X(_1226_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3666_ (.A(_1093_),
+    .X(_1227_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3667_ (.A(_1078_),
+    .X(_1228_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3668_ (.A(_1086_),
+    .X(_1229_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3669_ (.A(_1229_),
+    .B(\u_uart_core.u_rxfifo.mem[9][4] ),
+    .X(_1230_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3670_ (.A(_1071_),
+    .X(_1231_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3671_ (.A(_1231_),
+    .X(_1232_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3672_ (.A(_1232_),
+    .B(\u_uart_core.u_rxfifo.mem[8][4] ),
+    .X(_1233_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3673_ (.A(_1228_),
+    .B(_1230_),
+    .C(_1233_),
+    .X(_1234_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3674_ (.A(_1099_),
+    .X(_1235_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3675_ (.A(_1235_),
+    .X(_1236_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3676_ (.A(_1071_),
+    .X(_1237_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3677_ (.A(_1237_),
+    .X(_1238_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3678_ (.A(_1238_),
+    .B(\u_uart_core.u_rxfifo.mem[10][4] ),
+    .X(_1239_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3679_ (.A(_1066_),
+    .X(_1240_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3680_ (.A(_1240_),
+    .X(_1241_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3681_ (.A(_1241_),
+    .B(\u_uart_core.u_rxfifo.mem[11][4] ),
+    .X(_1242_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3682_ (.A(_1236_),
+    .B(_1239_),
+    .C(_1242_),
+    .X(_1243_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3683_ (.A(_1227_),
+    .B(_1234_),
+    .C(_1243_),
+    .X(_1244_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3684_ (.A(_1066_),
+    .X(_1245_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3685_ (.A(_1245_),
+    .X(_1246_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3686_ (.A(_1246_),
+    .B(\u_uart_core.u_rxfifo.mem[15][4] ),
+    .X(_1247_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3687_ (.A(_1232_),
+    .B(\u_uart_core.u_rxfifo.mem[14][4] ),
+    .X(_1248_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3688_ (.A(_1064_),
+    .B(_1247_),
+    .C(_1248_),
+    .X(_1249_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3689_ (.A(_1238_),
+    .B(\u_uart_core.u_rxfifo.mem[12][4] ),
+    .X(_1250_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3690_ (.A(_1241_),
+    .B(\u_uart_core.u_rxfifo.mem[13][4] ),
+    .X(_1251_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3691_ (.A(_1228_),
+    .B(_1250_),
+    .C(_1251_),
+    .X(_1252_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3692_ (.A(_1061_),
+    .B(_1249_),
+    .C(_1252_),
+    .X(_1253_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3693_ (.A(_1134_),
+    .B(_1244_),
+    .C(_1253_),
+    .X(_1254_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3694_ (.A(_1246_),
+    .B(\u_uart_core.u_rxfifo.mem[1][4] ),
+    .X(_1255_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3695_ (.A(_1232_),
+    .B(\u_uart_core.u_rxfifo.mem[0][4] ),
+    .X(_1256_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3696_ (.A(_1228_),
+    .B(_1255_),
+    .C(_1256_),
+    .X(_1257_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3697_ (.A(_1238_),
+    .B(\u_uart_core.u_rxfifo.mem[2][4] ),
+    .X(_1258_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3698_ (.A(_1241_),
+    .B(\u_uart_core.u_rxfifo.mem[3][4] ),
+    .X(_1259_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3699_ (.A(_1236_),
+    .B(_1258_),
+    .C(_1259_),
+    .X(_1260_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3700_ (.A(_1227_),
+    .B(_1257_),
+    .C(_1260_),
+    .X(_1261_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3701_ (.A(_1246_),
+    .B(\u_uart_core.u_rxfifo.mem[7][4] ),
+    .X(_1262_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3702_ (.A(_1238_),
+    .B(\u_uart_core.u_rxfifo.mem[6][4] ),
+    .X(_1263_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3703_ (.A(_1064_),
+    .B(_1262_),
+    .C(_1263_),
+    .X(_1264_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3704_ (.A(_1237_),
+    .X(_1265_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3705_ (.A(_1265_),
+    .B(\u_uart_core.u_rxfifo.mem[4][4] ),
+    .X(_1266_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3706_ (.A(_1240_),
+    .X(_1267_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3707_ (.A(_1267_),
+    .B(\u_uart_core.u_rxfifo.mem[5][4] ),
+    .X(_1268_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3708_ (.A(_1228_),
+    .B(_1266_),
+    .C(_1268_),
+    .X(_1269_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3709_ (.A(_1061_),
+    .B(_1264_),
+    .C(_1269_),
+    .X(_1270_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3710_ (.A(_1057_),
+    .B(_1261_),
+    .C(_1270_),
+    .X(_1271_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3711_ (.A1(_1254_),
+    .A2(_1271_),
+    .B1(_1054_),
+    .X(_1272_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3712_ (.A(_1224_),
+    .Y(_1273_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3713_ (.A(_1273_),
+    .X(_1274_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _3714_ (.A1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[4].u_bit_reg.data_out ),
+    .A2(_1051_),
+    .B1(_1274_),
+    .X(_1275_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3715_ (.A(\u_uart_core.u_rxfifo.grey_rd_ptr[4] ),
+    .Y(_1276_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3716_ (.A(\u_uart_core.u_rxfifo.sync_wr_ptr[4] ),
+    .Y(_1277_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3717_ (.A1(_1276_),
+    .A2(\u_uart_core.u_rxfifo.sync_wr_ptr[4] ),
+    .B1(\u_uart_core.u_rxfifo.grey_rd_ptr[4] ),
+    .B2(_1277_),
+    .X(_1278_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3718_ (.A1_N(\u_uart_core.u_rxfifo.sync_wr_ptr_1[3] ),
+    .A2_N(\u_uart_core.u_rxfifo.sync_wr_ptr[4] ),
+    .B1(\u_uart_core.u_rxfifo.sync_wr_ptr_1[3] ),
+    .B2(\u_uart_core.u_rxfifo.sync_wr_ptr[4] ),
+    .X(_1279_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3719_ (.A(_1132_),
+    .B(_1279_),
+    .X(_1280_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3720_ (.A1_N(\u_uart_core.u_rxfifo.sync_wr_ptr_1[2] ),
+    .A2_N(\u_uart_core.u_rxfifo.sync_wr_ptr_1[3] ),
+    .B1(\u_uart_core.u_rxfifo.sync_wr_ptr_1[2] ),
+    .B2(\u_uart_core.u_rxfifo.sync_wr_ptr_1[3] ),
+    .X(_1281_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3721_ (.A1_N(_1277_),
+    .A2_N(_1281_),
+    .B1(_1277_),
+    .B2(_1281_),
+    .X(_1282_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3722_ (.A1_N(\u_uart_core.u_rxfifo.rd_ptr[2] ),
+    .A2_N(_1282_),
+    .B1(\u_uart_core.u_rxfifo.rd_ptr[2] ),
+    .B2(_1282_),
+    .X(_1283_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3723_ (.A(_1282_),
+    .Y(_1284_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3724_ (.A1_N(\u_uart_core.u_rxfifo.sync_wr_ptr_1[1] ),
+    .A2_N(_1284_),
+    .B1(\u_uart_core.u_rxfifo.sync_wr_ptr_1[1] ),
+    .B2(_1284_),
+    .X(_1285_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3725_ (.A(_1285_),
+    .Y(_1286_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3726_ (.A1_N(\u_uart_core.u_rxfifo.sync_wr_ptr_1[0] ),
+    .A2_N(_1286_),
+    .B1(\u_uart_core.u_rxfifo.sync_wr_ptr_1[0] ),
+    .B2(_1286_),
+    .X(_1287_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3727_ (.A(_1103_),
+    .B(_1287_),
+    .X(_1288_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3728_ (.A(_1288_),
+    .Y(_1289_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3729_ (.A1(\u_uart_core.u_rxfifo.rd_ptr[1] ),
+    .A2(_1285_),
+    .B1(_1077_),
+    .B2(_1286_),
+    .X(_1290_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _3730_ (.A(_1289_),
+    .B(_1290_),
+    .Y(_1291_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3731_ (.A1(_1100_),
+    .A2(_1285_),
+    .B1(_1291_),
+    .X(_1292_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3732_ (.A1(_1093_),
+    .A2(_1282_),
+    .B1(_1283_),
+    .B2(_1292_),
+    .X(_1293_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3733_ (.A(_1132_),
+    .B(_1279_),
+    .X(_1294_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3734_ (.A1(_1280_),
+    .A2(_1293_),
+    .B1(_1294_),
+    .X(_1295_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3735_ (.A1_N(_1278_),
+    .A2_N(_1295_),
+    .B1(_1278_),
+    .B2(_1295_),
+    .X(_1296_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3736_ (.A(_1218_),
+    .B(_1296_),
+    .X(_1297_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3737_ (.A(\u_uart_core.u_txfifo.wr_ptr[2] ),
+    .Y(_1298_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3738_ (.A(\u_uart_core.u_txfifo.sync_rd_ptr[4] ),
+    .Y(_1299_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3739_ (.A1_N(\u_uart_core.u_txfifo.sync_rd_ptr_1[2] ),
+    .A2_N(\u_uart_core.u_txfifo.sync_rd_ptr_1[3] ),
+    .B1(\u_uart_core.u_txfifo.sync_rd_ptr_1[2] ),
+    .B2(\u_uart_core.u_txfifo.sync_rd_ptr_1[3] ),
+    .X(_1300_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3740_ (.A1_N(_1299_),
+    .A2_N(_1300_),
+    .B1(_1299_),
+    .B2(_1300_),
+    .X(_1301_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3741_ (.A(_1301_),
+    .Y(_1302_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3742_ (.A(_1298_),
+    .B(_1302_),
+    .X(_1303_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3743_ (.A(_1303_),
+    .Y(_1304_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _3744_ (.A1(_1298_),
+    .A2(_1302_),
+    .B1(_1304_),
+    .X(_1305_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3745_ (.A(\u_uart_core.u_txfifo.sync_rd_ptr[4] ),
+    .X(_1306_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3746_ (.A1_N(\u_uart_core.u_txfifo.sync_rd_ptr_1[3] ),
+    .A2_N(_1306_),
+    .B1(\u_uart_core.u_txfifo.sync_rd_ptr_1[3] ),
+    .B2(_1306_),
+    .X(_1307_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3747_ (.A(\u_uart_core.u_txfifo.wr_ptr[3] ),
+    .B(_1307_),
+    .X(_1308_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3748_ (.A(\u_uart_core.u_txfifo.wr_ptr[3] ),
+    .B(_1307_),
+    .Y(_1309_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3749_ (.A(_1308_),
+    .B(_1309_),
+    .X(_1310_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3750_ (.A(\u_uart_core.u_txfifo.wr_ptr[1] ),
+    .Y(_1311_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3751_ (.A(_1311_),
+    .X(_1312_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3752_ (.A(\u_uart_core.u_txfifo.sync_rd_ptr_1[1] ),
+    .Y(_1313_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3753_ (.A1(\u_uart_core.u_txfifo.sync_rd_ptr_1[1] ),
+    .A2(_1302_),
+    .B1(_1313_),
+    .B2(_1301_),
+    .X(_1314_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3754_ (.A1_N(_1311_),
+    .A2_N(_1314_),
+    .B1(_1311_),
+    .B2(_1314_),
+    .X(_1315_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3755_ (.A(\u_uart_core.u_txfifo.wr_ptr[0] ),
+    .Y(_1316_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3756_ (.A(\u_uart_core.u_txfifo.sync_rd_ptr_1[0] ),
+    .Y(_1317_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3757_ (.A1_N(_1317_),
+    .A2_N(\u_uart_core.u_txfifo.sync_rd_ptr_1[1] ),
+    .B1(_1317_),
+    .B2(\u_uart_core.u_txfifo.sync_rd_ptr_1[1] ),
+    .X(_1318_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3758_ (.A1_N(_1301_),
+    .A2_N(_1318_),
+    .B1(_1301_),
+    .B2(_1318_),
+    .X(_1319_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3759_ (.A(_1316_),
+    .B(_1319_),
+    .X(_1320_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3760_ (.A(_1315_),
+    .B(_1320_),
+    .X(_1321_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3761_ (.A1(_1312_),
+    .A2(_1314_),
+    .B1(_1321_),
+    .X(_1322_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3762_ (.A(_1304_),
+    .B(_1308_),
+    .Y(_1323_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o32a_4 _3763_ (.A1(_1305_),
+    .A2(_1310_),
+    .A3(_1322_),
+    .B1(_1309_),
+    .B2(_1323_),
+    .X(_1324_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3764_ (.A(_1324_),
+    .Y(_1325_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3765_ (.A(\u_uart_core.u_txfifo.grey_wr_ptr[4] ),
+    .Y(_1326_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3766_ (.A(_1326_),
+    .X(_1327_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3767_ (.A1_N(_1327_),
+    .A2_N(_1306_),
+    .B1(_1326_),
+    .B2(_1306_),
+    .X(_1328_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3768_ (.A1_N(_1325_),
+    .A2_N(_1328_),
+    .B1(_1325_),
+    .B2(_1328_),
+    .X(_1329_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3769_ (.A(_1305_),
+    .X(_1330_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3770_ (.A(_1316_),
+    .X(_1331_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3771_ (.A(_1331_),
+    .B(_1319_),
+    .Y(_1332_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3772_ (.A(_1321_),
+    .B(_1332_),
+    .X(_1333_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3773_ (.A(_1330_),
+    .B(_1333_),
+    .X(_1334_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _3774_ (.A1(_1322_),
+    .A2(_1330_),
+    .B1(_1303_),
+    .Y(_1335_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3775_ (.A1_N(_1310_),
+    .A2_N(_1335_),
+    .B1(_1310_),
+    .B2(_1335_),
+    .X(_1336_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3776_ (.A(_1334_),
+    .B(_1336_),
+    .Y(_1337_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3777_ (.A(psn_net_177),
+    .B(_0546_),
+    .C(_1005_),
+    .D(psn_net_160),
+    .X(_1338_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3778_ (.A(_1329_),
+    .B(_1337_),
+    .Y(_1339_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3779_ (.A1(_1329_),
+    .A2(_1337_),
+    .B1(_1338_),
+    .C1(_1339_),
+    .X(_1340_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3780_ (.A(_1340_),
+    .Y(_1341_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3781_ (.A(_1272_),
+    .B(_1341_),
+    .C(_1297_),
+    .D(_1275_),
+    .X(_1342_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3782_ (.A(_1043_),
+    .X(_1343_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3783_ (.A1(_1342_),
+    .A2(_1216_),
+    .A3(_1226_),
+    .B1(\u_uart_core.reg_rdata[4] ),
+    .B2(_1343_),
+    .X(_0490_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3784_ (.A(_0638_),
+    .B(_1225_),
+    .X(_1344_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3785_ (.A(_1218_),
+    .X(_1345_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3786_ (.A(_1293_),
+    .Y(_1346_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3787_ (.A(_1294_),
+    .Y(_1347_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3788_ (.A(_1347_),
+    .B(_1280_),
+    .X(_1348_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3789_ (.A1_N(_1346_),
+    .A2_N(_1348_),
+    .B1(_1346_),
+    .B2(_1348_),
+    .X(_1349_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3790_ (.A(_1048_),
+    .X(_1350_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3791_ (.A(_1350_),
+    .X(_1351_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3792_ (.A(_1012_),
+    .Y(_1352_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3793_ (.A(_1352_),
+    .X(_1353_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3794_ (.A1(_1351_),
+    .A2(_1353_),
+    .A3(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[3].u_bit_reg.data_out ),
+    .B1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[3].u_bit_reg.data_out ),
+    .B2(_1050_),
+    .X(_1354_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3795_ (.A(_1265_),
+    .B(\u_uart_core.u_rxfifo.mem[10][3] ),
+    .X(_1355_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3796_ (.A(_1267_),
+    .B(\u_uart_core.u_rxfifo.mem[11][3] ),
+    .X(_1356_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3797_ (.A(_1068_),
+    .B(\u_uart_core.u_rxfifo.mem[9][3] ),
+    .X(_1357_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3798_ (.A(_1077_),
+    .X(_1358_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3799_ (.A(_1358_),
+    .X(_1359_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3800_ (.A1(_1073_),
+    .A2(\u_uart_core.u_rxfifo.mem[8][3] ),
+    .B1(_1359_),
+    .X(_1360_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3801_ (.A1(_1236_),
+    .A2(_1355_),
+    .A3(_1356_),
+    .B1(_1357_),
+    .B2(_1360_),
+    .X(_1361_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3802_ (.A(_1093_),
+    .X(_1362_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3803_ (.A(_1072_),
+    .B(\u_uart_core.u_rxfifo.mem[12][3] ),
+    .X(_1363_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3804_ (.A(_1067_),
+    .B(\u_uart_core.u_rxfifo.mem[13][3] ),
+    .X(_1364_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3805_ (.A(_1087_),
+    .B(\u_uart_core.u_rxfifo.mem[15][3] ),
+    .X(_1365_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3806_ (.A1(_1082_),
+    .A2(\u_uart_core.u_rxfifo.mem[14][3] ),
+    .B1(_1099_),
+    .X(_1366_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3807_ (.A1(_1359_),
+    .A2(_1363_),
+    .A3(_1364_),
+    .B1(_1365_),
+    .B2(_1366_),
+    .X(_1367_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3808_ (.A(_1362_),
+    .B(_1367_),
+    .X(_1368_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3809_ (.A1(_1061_),
+    .A2(_1361_),
+    .B1(_1057_),
+    .C1(_1368_),
+    .X(_1369_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3810_ (.A(_1265_),
+    .B(\u_uart_core.u_rxfifo.mem[2][3] ),
+    .X(_1370_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3811_ (.A(_1068_),
+    .B(\u_uart_core.u_rxfifo.mem[3][3] ),
+    .X(_1371_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3812_ (.A(_1068_),
+    .B(\u_uart_core.u_rxfifo.mem[1][3] ),
+    .X(_1372_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3813_ (.A1(_1073_),
+    .A2(\u_uart_core.u_rxfifo.mem[0][3] ),
+    .B1(_1359_),
+    .X(_1373_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3814_ (.A1(_1236_),
+    .A2(_1370_),
+    .A3(_1371_),
+    .B1(_1372_),
+    .B2(_1373_),
+    .X(_1374_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3815_ (.A(_1072_),
+    .B(\u_uart_core.u_rxfifo.mem[4][3] ),
+    .X(_1375_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3816_ (.A(_1087_),
+    .B(\u_uart_core.u_rxfifo.mem[5][3] ),
+    .X(_1376_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3817_ (.A(_1087_),
+    .B(\u_uart_core.u_rxfifo.mem[7][3] ),
+    .X(_1377_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3818_ (.A1(_1082_),
+    .A2(\u_uart_core.u_rxfifo.mem[6][3] ),
+    .B1(_1099_),
+    .X(_1378_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3819_ (.A1(_1359_),
+    .A2(_1375_),
+    .A3(_1376_),
+    .B1(_1377_),
+    .B2(_1378_),
+    .X(_1379_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3820_ (.A(_1362_),
+    .B(_1379_),
+    .X(_1380_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3821_ (.A1(_1136_),
+    .A2(_1374_),
+    .B1(_1133_),
+    .C1(_1380_),
+    .X(_1381_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3822_ (.A(_1054_),
+    .B(_1369_),
+    .C(_1381_),
+    .X(_1382_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _3823_ (.A(_1382_),
+    .B(_1354_),
+    .C(_1274_),
+    .X(_1383_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3824_ (.A1(_1334_),
+    .A2(_1336_),
+    .B1(_1338_),
+    .C1(_1337_),
+    .X(_1384_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3825_ (.A(_1384_),
+    .Y(_1385_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3826_ (.A1(_1345_),
+    .A2(_1349_),
+    .B1(_1385_),
+    .C1(_1383_),
+    .X(_1386_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3827_ (.A1(_1386_),
+    .A2(_1216_),
+    .A3(_1344_),
+    .B1(\u_uart_core.reg_rdata[3] ),
+    .B2(_1045_),
+    .X(_0489_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3828_ (.A(\u_uart_core.cfg_stop_bit ),
+    .B(_1225_),
+    .X(_1387_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3829_ (.A1_N(_1283_),
+    .A2_N(_1292_),
+    .B1(_1283_),
+    .B2(_1292_),
+    .X(_1388_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3830_ (.A(_1388_),
+    .Y(_1389_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3831_ (.A(_1351_),
+    .B(psn_net_172),
+    .C(\u_uart_core.u_cfg.u_intr_bit2.data_out ),
+    .X(_1390_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3832_ (.A1(_1350_),
+    .A2(_1352_),
+    .A3(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[2].u_bit_reg.data_out ),
+    .B1(_1050_),
+    .B2(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[2].u_bit_reg.data_out ),
+    .X(_1391_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3833_ (.A(_1078_),
+    .X(_1392_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3834_ (.A(_1103_),
+    .X(_1393_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3835_ (.A(_1393_),
+    .B(\u_uart_core.u_rxfifo.mem[12][2] ),
+    .X(_1394_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3836_ (.A(_1246_),
+    .B(\u_uart_core.u_rxfifo.mem[13][2] ),
+    .X(_1395_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3837_ (.A(_1267_),
+    .B(\u_uart_core.u_rxfifo.mem[15][2] ),
+    .X(_1396_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3838_ (.A1(_1265_),
+    .A2(\u_uart_core.u_rxfifo.mem[14][2] ),
+    .B1(_1100_),
+    .X(_1397_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3839_ (.A1(_1392_),
+    .A2(_1394_),
+    .A3(_1395_),
+    .B1(_1396_),
+    .B2(_1397_),
+    .X(_1398_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3840_ (.A(_1237_),
+    .B(\u_uart_core.u_rxfifo.mem[10][2] ),
+    .X(_1399_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3841_ (.A(_1240_),
+    .B(\u_uart_core.u_rxfifo.mem[11][2] ),
+    .X(_1400_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3842_ (.A(_1067_),
+    .B(\u_uart_core.u_rxfifo.mem[9][2] ),
+    .X(_1401_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3843_ (.A1(_1072_),
+    .A2(\u_uart_core.u_rxfifo.mem[8][2] ),
+    .B1(_1358_),
+    .X(_1402_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3844_ (.A1(_1235_),
+    .A2(_1399_),
+    .A3(_1400_),
+    .B1(_1401_),
+    .B2(_1402_),
+    .X(_1403_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3845_ (.A(_1135_),
+    .B(_1403_),
+    .X(_1404_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3846_ (.A1(_1227_),
+    .A2(_1398_),
+    .B1(_1057_),
+    .C1(_1404_),
+    .X(_1405_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3847_ (.A(_1232_),
+    .B(\u_uart_core.u_rxfifo.mem[4][2] ),
+    .X(_1406_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3848_ (.A(_1241_),
+    .B(\u_uart_core.u_rxfifo.mem[5][2] ),
+    .X(_1407_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3849_ (.A(_1267_),
+    .B(\u_uart_core.u_rxfifo.mem[7][2] ),
+    .X(_1408_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3850_ (.A1(_1073_),
+    .A2(\u_uart_core.u_rxfifo.mem[6][2] ),
+    .B1(_1100_),
+    .X(_1409_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3851_ (.A1(_1392_),
+    .A2(_1406_),
+    .A3(_1407_),
+    .B1(_1408_),
+    .B2(_1409_),
+    .X(_1410_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3852_ (.A(_1237_),
+    .B(\u_uart_core.u_rxfifo.mem[2][2] ),
+    .X(_1411_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3853_ (.A(_1240_),
+    .B(\u_uart_core.u_rxfifo.mem[3][2] ),
+    .X(_1412_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3854_ (.A(_1067_),
+    .B(\u_uart_core.u_rxfifo.mem[1][2] ),
+    .X(_1413_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3855_ (.A1(_1082_),
+    .A2(\u_uart_core.u_rxfifo.mem[0][2] ),
+    .B1(_1078_),
+    .X(_1414_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3856_ (.A1(_1235_),
+    .A2(_1411_),
+    .A3(_1412_),
+    .B1(_1413_),
+    .B2(_1414_),
+    .X(_1415_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3857_ (.A(_1135_),
+    .B(_1415_),
+    .X(_1416_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3858_ (.A1(_1227_),
+    .A2(_1410_),
+    .B1(_1133_),
+    .C1(_1416_),
+    .X(_1417_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3859_ (.A(_1054_),
+    .B(_1405_),
+    .C(_1417_),
+    .X(_1418_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3860_ (.A(_1390_),
+    .B(_1418_),
+    .C(_1273_),
+    .D(_1391_),
+    .X(_1419_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3861_ (.A(_1338_),
+    .Y(_1420_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3862_ (.A(_1333_),
+    .Y(_1421_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3863_ (.A1_N(_1322_),
+    .A2_N(_1330_),
+    .B1(_1322_),
+    .B2(_1330_),
+    .X(_1422_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3864_ (.A(_1421_),
+    .B(_1422_),
+    .X(_1423_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3865_ (.A(_1334_),
+    .B(_1420_),
+    .C(_1423_),
+    .X(_1424_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3866_ (.A1(_1345_),
+    .A2(_1389_),
+    .B1(_1424_),
+    .C1(_1419_),
+    .X(_1425_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3867_ (.A1(_1425_),
+    .A2(_1216_),
+    .A3(_1387_),
+    .B1(\u_uart_core.reg_rdata[2] ),
+    .B2(_1045_),
+    .X(_0488_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3868_ (.A1(_1289_),
+    .A2(_1290_),
+    .B1(_1291_),
+    .X(_1426_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3869_ (.A(_1350_),
+    .B(_1352_),
+    .C(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[1].u_bit_reg.data_out ),
+    .X(_1427_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3870_ (.A(_1350_),
+    .B(_1222_),
+    .C(\u_uart_core.u_cfg.u_intr_bit1.data_out ),
+    .X(_1428_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3871_ (.A(\u_uart_core.app_rxfifo_empty ),
+    .Y(_1429_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3872_ (.A1_N(_1429_),
+    .A2_N(_1219_),
+    .B1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[1].u_bit_reg.data_out ),
+    .B2(_1049_),
+    .X(_1430_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3873_ (.A(_1104_),
+    .B(\u_uart_core.u_rxfifo.mem[12][1] ),
+    .X(_1431_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3874_ (.A(_1108_),
+    .B(\u_uart_core.u_rxfifo.mem[13][1] ),
+    .X(_1432_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3875_ (.A(_1229_),
+    .B(\u_uart_core.u_rxfifo.mem[15][1] ),
+    .X(_1433_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3876_ (.A1(_1393_),
+    .A2(\u_uart_core.u_rxfifo.mem[14][1] ),
+    .B1(_1063_),
+    .X(_1434_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3877_ (.A1(_1079_),
+    .A2(_1431_),
+    .A3(_1432_),
+    .B1(_1433_),
+    .B2(_1434_),
+    .X(_1435_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3878_ (.A(_1103_),
+    .B(\u_uart_core.u_rxfifo.mem[10][1] ),
+    .X(_1436_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3879_ (.A(_1086_),
+    .B(\u_uart_core.u_rxfifo.mem[11][1] ),
+    .X(_1437_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3880_ (.A(_1245_),
+    .B(\u_uart_core.u_rxfifo.mem[9][1] ),
+    .X(_1438_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3881_ (.A1(_1231_),
+    .A2(\u_uart_core.u_rxfifo.mem[8][1] ),
+    .B1(_1358_),
+    .X(_1439_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3882_ (.A1(_1063_),
+    .A2(_1436_),
+    .A3(_1437_),
+    .B1(_1438_),
+    .B2(_1439_),
+    .X(_1440_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3883_ (.A(_1060_),
+    .B(_1440_),
+    .X(_1441_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3884_ (.A1(_1362_),
+    .A2(_1435_),
+    .B1(_1056_),
+    .C1(_1441_),
+    .X(_1442_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3885_ (.A(_1393_),
+    .B(\u_uart_core.u_rxfifo.mem[4][1] ),
+    .X(_1443_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3886_ (.A(_1229_),
+    .B(\u_uart_core.u_rxfifo.mem[5][1] ),
+    .X(_1444_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3887_ (.A(_1229_),
+    .B(\u_uart_core.u_rxfifo.mem[7][1] ),
+    .X(_1445_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3888_ (.A1(_1393_),
+    .A2(\u_uart_core.u_rxfifo.mem[6][1] ),
+    .B1(_1235_),
+    .X(_1446_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3889_ (.A1(_1079_),
+    .A2(_1443_),
+    .A3(_1444_),
+    .B1(_1445_),
+    .B2(_1446_),
+    .X(_1447_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3890_ (.A(_1231_),
+    .B(\u_uart_core.u_rxfifo.mem[2][1] ),
+    .X(_1448_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3891_ (.A(_1245_),
+    .B(\u_uart_core.u_rxfifo.mem[3][1] ),
+    .X(_1449_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3892_ (.A(_1245_),
+    .B(\u_uart_core.u_rxfifo.mem[1][1] ),
+    .X(_1450_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3893_ (.A1(_1231_),
+    .A2(\u_uart_core.u_rxfifo.mem[0][1] ),
+    .B1(_1358_),
+    .X(_1451_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3894_ (.A1(_1063_),
+    .A2(_1448_),
+    .A3(_1449_),
+    .B1(_1450_),
+    .B2(_1451_),
+    .X(_1452_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3895_ (.A(_1135_),
+    .B(_1452_),
+    .X(_1453_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3896_ (.A1(_1362_),
+    .A2(_1447_),
+    .B1(_1132_),
+    .C1(_1453_),
+    .X(_1454_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3897_ (.A(_1053_),
+    .B(_1442_),
+    .C(_1454_),
+    .X(_1455_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3898_ (.A(_1427_),
+    .B(_1428_),
+    .C(_1455_),
+    .D(_1430_),
+    .X(_1456_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3899_ (.A(_1315_),
+    .Y(_1457_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _3900_ (.A1(_1457_),
+    .A2(_1332_),
+    .B1(_1321_),
+    .Y(_1458_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _3901_ (.A(_1333_),
+    .B(_1420_),
+    .C(_1458_),
+    .X(_1459_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3902_ (.A(\u_uart_core.cfg_rx_enable ),
+    .B(psn_net_169),
+    .X(_1460_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2111o_4 _3903_ (.A1(_1345_),
+    .A2(_1426_),
+    .B1(_1459_),
+    .C1(_1456_),
+    .D1(_1460_),
+    .X(_1461_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3904_ (.A(_1461_),
+    .Y(_1462_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3905_ (.A1_N(_1343_),
+    .A2_N(_1462_),
+    .B1(\u_uart_core.reg_rdata[1] ),
+    .B2(_1343_),
+    .X(_0487_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3906_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[0].u_bit_reg.data_out ),
+    .X(_1463_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3907_ (.A1(_1351_),
+    .A2(_1353_),
+    .A3(_1463_),
+    .B1(\u_uart_core.app_tx_fifo_full ),
+    .B2(_1220_),
+    .X(_1464_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3908_ (.A1(_1351_),
+    .A2(psn_net_171),
+    .A3(\u_uart_core.u_cfg.u_intr_bit0.data_out ),
+    .B1(_1026_),
+    .B2(_1050_),
+    .X(_1465_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3909_ (.A1(_1320_),
+    .A2(_1332_),
+    .B1(_1420_),
+    .X(_1466_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _3910_ (.A(_1464_),
+    .B(_1465_),
+    .C(_1466_),
+    .D(_1274_),
+    .X(_1467_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3911_ (.A(_1062_),
+    .X(_1468_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3912_ (.A(_1121_),
+    .B(\u_uart_core.u_rxfifo.mem[8][0] ),
+    .X(_1469_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3913_ (.A(_1128_),
+    .B(\u_uart_core.u_rxfifo.mem[9][0] ),
+    .X(_1470_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3914_ (.A(_1128_),
+    .B(\u_uart_core.u_rxfifo.mem[11][0] ),
+    .X(_1471_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3915_ (.A1(_1126_),
+    .A2(\u_uart_core.u_rxfifo.mem[10][0] ),
+    .B1(_1124_),
+    .X(_1472_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3916_ (.A1(_1116_),
+    .A2(_1469_),
+    .A3(_1470_),
+    .B1(_1471_),
+    .B2(_1472_),
+    .X(_1473_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3917_ (.A(_1120_),
+    .B(\u_uart_core.u_rxfifo.mem[14][0] ),
+    .X(_1474_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3918_ (.A(_1117_),
+    .B(\u_uart_core.u_rxfifo.mem[15][0] ),
+    .X(_1475_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3919_ (.A(_1182_),
+    .B(\u_uart_core.u_rxfifo.mem[13][0] ),
+    .X(_1476_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3920_ (.A1(_1184_),
+    .A2(\u_uart_core.u_rxfifo.mem[12][0] ),
+    .B1(_1392_),
+    .X(_1477_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3921_ (.A1(_1124_),
+    .A2(_1474_),
+    .A3(_1475_),
+    .B1(_1476_),
+    .B2(_1477_),
+    .X(_1478_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3922_ (.A(_1094_),
+    .B(_1478_),
+    .X(_1479_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3923_ (.A1(_1468_),
+    .A2(_1473_),
+    .B1(_1058_),
+    .C1(_1479_),
+    .X(_1480_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3924_ (.A(_1115_),
+    .X(_1481_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3925_ (.A(_1126_),
+    .B(\u_uart_core.u_rxfifo.mem[0][0] ),
+    .X(_1482_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3926_ (.A(_1128_),
+    .B(\u_uart_core.u_rxfifo.mem[1][0] ),
+    .X(_1483_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3927_ (.A(_1117_),
+    .X(_1484_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3928_ (.A(_1484_),
+    .B(\u_uart_core.u_rxfifo.mem[3][0] ),
+    .X(_1485_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3929_ (.A(_1184_),
+    .X(_1486_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3930_ (.A1(_1486_),
+    .A2(\u_uart_core.u_rxfifo.mem[2][0] ),
+    .B1(_1065_),
+    .X(_1487_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3931_ (.A1(_1481_),
+    .A2(_1482_),
+    .A3(_1483_),
+    .B1(_1485_),
+    .B2(_1487_),
+    .X(_1488_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3932_ (.A(_1133_),
+    .X(_1489_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3933_ (.A(_1120_),
+    .B(\u_uart_core.u_rxfifo.mem[6][0] ),
+    .X(_1490_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3934_ (.A(_1182_),
+    .B(\u_uart_core.u_rxfifo.mem[7][0] ),
+    .X(_1491_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3935_ (.A(_1182_),
+    .B(\u_uart_core.u_rxfifo.mem[5][0] ),
+    .X(_1492_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _3936_ (.A1(_1184_),
+    .A2(\u_uart_core.u_rxfifo.mem[4][0] ),
+    .B1(_1392_),
+    .X(_1493_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3937_ (.A1(_1124_),
+    .A2(_1490_),
+    .A3(_1491_),
+    .B1(_1492_),
+    .B2(_1493_),
+    .X(_1494_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _3938_ (.A(_1094_),
+    .B(_1494_),
+    .X(_1495_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _3939_ (.A1(_1468_),
+    .A2(_1488_),
+    .B1(_1489_),
+    .C1(_1495_),
+    .X(_1496_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3940_ (.A(_1486_),
+    .B(_1287_),
+    .Y(_1497_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _3941_ (.A(_1288_),
+    .B(_1497_),
+    .X(_1498_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _3942_ (.A1(_1055_),
+    .A2(_1480_),
+    .A3(_1496_),
+    .B1(_1345_),
+    .B2(_1498_),
+    .X(_1499_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3943_ (.A1(\u_uart_core.cfg_tx_enable ),
+    .A2(_1225_),
+    .B1(_1499_),
+    .B2(_1467_),
+    .X(_1500_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _3944_ (.A1(_1343_),
+    .A2(_1500_),
+    .B1(\u_uart_core.reg_rdata[0] ),
+    .B2(_1216_),
+    .X(_0486_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3945_ (.A1_N(_0604_),
+    .A2_N(_1025_),
+    .B1(_0563_),
+    .B2(_1025_),
+    .X(_0485_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3946_ (.A(\u_uart_core.cfg_rx_enable ),
+    .Y(_1501_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3947_ (.A(_1024_),
+    .X(_1502_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3948_ (.A1_N(_1501_),
+    .A2_N(_1502_),
+    .B1(_0558_),
+    .B2(_1502_),
+    .X(_0484_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3949_ (.A(\u_uart_core.cfg_stop_bit ),
+    .Y(_1503_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3950_ (.A1_N(_1503_),
+    .A2_N(_1502_),
+    .B1(_1020_),
+    .B2(_1502_),
+    .X(_0483_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3951_ (.A(_0638_),
+    .Y(_1504_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3952_ (.A1_N(_1504_),
+    .A2_N(_1024_),
+    .B1(_1036_),
+    .B2(_1024_),
+    .X(_0482_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3953_ (.A(\u_i2cm.prer[7] ),
+    .Y(_1505_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3954_ (.A(_0555_),
+    .B(_1023_),
+    .Y(_1506_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3955_ (.A(_1506_),
+    .X(_1507_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3956_ (.A1_N(_1505_),
+    .A2_N(_1507_),
+    .B1(_0570_),
+    .B2(_1507_),
+    .X(_0481_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3957_ (.A(\u_i2cm.prer[6] ),
+    .Y(_1508_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3958_ (.A1_N(_1508_),
+    .A2_N(_1507_),
+    .B1(_0574_),
+    .B2(_1507_),
+    .X(_0480_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3959_ (.A(\u_i2cm.prer[5] ),
+    .Y(_1509_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3960_ (.A(_1506_),
+    .X(_1510_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3961_ (.A1_N(_1509_),
+    .A2_N(_1510_),
+    .B1(_0577_),
+    .B2(_1510_),
+    .X(_0479_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3962_ (.A(\u_i2cm.prer[4] ),
+    .Y(_1511_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3963_ (.A1_N(_1511_),
+    .A2_N(_1510_),
+    .B1(_0580_),
+    .B2(_1510_),
+    .X(_0478_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3964_ (.A(\u_i2cm.prer[3] ),
+    .Y(_1512_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3965_ (.A(_1506_),
+    .X(_1513_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3966_ (.A1_N(_1512_),
+    .A2_N(_1513_),
+    .B1(_1036_),
+    .B2(_1513_),
+    .X(_0477_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3967_ (.A(\u_i2cm.prer[2] ),
+    .Y(_1514_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3968_ (.A1_N(_1514_),
+    .A2_N(_1513_),
+    .B1(_1020_),
+    .B2(_1513_),
+    .X(_0476_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3969_ (.A(\u_i2cm.prer[1] ),
+    .Y(_1515_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3970_ (.A(_1506_),
+    .X(_1516_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3971_ (.A(_0557_),
+    .X(_1517_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3972_ (.A1_N(_1515_),
+    .A2_N(_1516_),
+    .B1(_1517_),
+    .B2(_1516_),
+    .X(_0475_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3973_ (.A(\u_i2cm.prer[0] ),
+    .Y(_1518_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3974_ (.A(_0562_),
+    .X(_1519_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3975_ (.A1_N(_1518_),
+    .A2_N(_1516_),
+    .B1(_1519_),
+    .B2(_1516_),
+    .X(_0474_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3976_ (.A(\u_i2cm.prer[15] ),
+    .Y(_1520_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3977_ (.A(psn_net_173),
+    .X(_1521_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3978_ (.A(_1521_),
+    .X(_1522_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3979_ (.A(_1522_),
+    .X(_1523_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _3980_ (.A(_0555_),
+    .B(_1523_),
+    .Y(_1524_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3981_ (.A(_1524_),
+    .X(_1525_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3982_ (.A1_N(_1520_),
+    .A2_N(_1525_),
+    .B1(_0570_),
+    .B2(_1525_),
+    .X(_0473_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3983_ (.A(\u_i2cm.prer[14] ),
+    .Y(_1526_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3984_ (.A1_N(_1526_),
+    .A2_N(_1525_),
+    .B1(_0574_),
+    .B2(_1525_),
+    .X(_0472_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3985_ (.A(\u_i2cm.prer[13] ),
+    .Y(_1527_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3986_ (.A(_1524_),
+    .X(_1528_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3987_ (.A1_N(_1527_),
+    .A2_N(_1528_),
+    .B1(_0577_),
+    .B2(_1528_),
+    .X(_0471_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3988_ (.A(\u_i2cm.prer[12] ),
+    .Y(_1529_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3989_ (.A(reg_wdata[4]),
+    .X(_1530_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3990_ (.A(_1530_),
+    .X(_1531_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3991_ (.A1_N(_1529_),
+    .A2_N(_1528_),
+    .B1(_1531_),
+    .B2(_1528_),
+    .X(_0470_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3992_ (.A(\u_i2cm.prer[11] ),
+    .Y(_1532_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3993_ (.A(_1524_),
+    .X(_1533_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3994_ (.A1_N(_1532_),
+    .A2_N(_1533_),
+    .B1(_1036_),
+    .B2(_1533_),
+    .X(_0469_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3995_ (.A(\u_i2cm.prer[10] ),
+    .Y(_1534_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3996_ (.A(_1019_),
+    .X(_1535_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _3997_ (.A1_N(_1534_),
+    .A2_N(_1533_),
+    .B1(_1535_),
+    .B2(_1533_),
+    .X(_0468_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _3998_ (.A(\u_i2cm.prer[9] ),
+    .Y(_1536_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _3999_ (.A(_1524_),
+    .X(_1537_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4000_ (.A1_N(_1536_),
+    .A2_N(_1537_),
+    .B1(_1517_),
+    .B2(_1537_),
+    .X(_0467_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4001_ (.A(\u_i2cm.prer[8] ),
+    .Y(_1538_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4002_ (.A1_N(_1538_),
+    .A2_N(_1537_),
+    .B1(_1519_),
+    .B2(_1537_),
+    .X(_0466_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4003_ (.A(\u_i2cm.ack ),
+    .Y(_1539_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4004_ (.A(_1035_),
+    .X(_1540_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4005_ (.A1_N(_1539_),
+    .A2_N(_0560_),
+    .B1(_1540_),
+    .B2(_0560_),
+    .X(_0465_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4006_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[3].u_bit_reg.data_out ),
+    .X(_1541_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4007_ (.A(_1541_),
+    .Y(_1542_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4008_ (.A1_N(_1542_),
+    .A2_N(_1018_),
+    .B1(_1540_),
+    .B2(_1018_),
+    .X(_0464_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4009_ (.A(\u_uart_core.u_rxfsm.rxstate[2] ),
+    .Y(_1543_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4010_ (.A(_1543_),
+    .X(_1544_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4011_ (.A(\u_uart_core.si_ss ),
+    .X(_1545_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4012_ (.A(\u_uart_core.u_rxfsm.cnt[1] ),
+    .Y(_1546_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4013_ (.A(\u_uart_core.u_rxfsm.cnt[0] ),
+    .Y(_1547_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4014_ (.A(\u_uart_core.u_rxfsm.cnt[2] ),
+    .Y(_1548_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4015_ (.A(_1546_),
+    .B(_1547_),
+    .C(_1548_),
+    .X(_1549_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4016_ (.A(_1549_),
+    .X(_1550_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4017_ (.A(\u_uart_core.si_ss ),
+    .Y(_1551_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4018_ (.A(_1549_),
+    .Y(_1552_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4019_ (.A(\u_uart_core.u_rxfsm.rxstate[1] ),
+    .Y(_1553_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4020_ (.A(\u_uart_core.u_rxfsm.rxstate[0] ),
+    .X(_1554_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4021_ (.A(_1544_),
+    .B(_1553_),
+    .C(_1554_),
+    .X(_1555_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4022_ (.A1(_1551_),
+    .A2(_1552_),
+    .B1(_1555_),
+    .X(_1556_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4023_ (.A1(_1545_),
+    .A2(_1550_),
+    .B1(_1556_),
+    .X(_1557_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4024_ (.A(_1501_),
+    .B(\u_uart_core.rx_fifo_wr_full ),
+    .X(_1558_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4025_ (.A(\u_uart_core.u_rxfsm.rxstate[1] ),
+    .B(\u_uart_core.u_rxfsm.rxstate[0] ),
+    .X(_1559_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4026_ (.A(_1559_),
+    .Y(_1560_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4027_ (.A(_1543_),
+    .B(_1560_),
+    .X(_1561_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4028_ (.A1(\u_uart_core.si_ss ),
+    .A2(_1558_),
+    .B1(_1561_),
+    .X(_1562_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4029_ (.A(\u_uart_core.u_rxfsm.rxstate[2] ),
+    .X(_1563_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4030_ (.A(_1553_),
+    .X(_1564_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4031_ (.A(_1563_),
+    .B(_1564_),
+    .X(_1565_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4032_ (.A(_1565_),
+    .X(_1566_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4033_ (.A(_1544_),
+    .B(\u_uart_core.u_rxfsm.rxstate[1] ),
+    .C(_1554_),
+    .X(_1567_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4034_ (.A(\u_uart_core.u_rxfsm.rxpos[3] ),
+    .Y(_1568_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4035_ (.A(\u_uart_core.u_rxfsm.offset[3] ),
+    .Y(_1569_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4036_ (.A1(\u_uart_core.u_rxfsm.rxpos[3] ),
+    .A2(\u_uart_core.u_rxfsm.offset[3] ),
+    .B1(_1568_),
+    .B2(_1569_),
+    .X(_1570_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4037_ (.A(\u_uart_core.u_rxfsm.rxpos[0] ),
+    .Y(_1571_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4038_ (.A(\u_uart_core.u_rxfsm.offset[0] ),
+    .Y(_0055_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4039_ (.A1(\u_uart_core.u_rxfsm.rxpos[0] ),
+    .A2(\u_uart_core.u_rxfsm.offset[0] ),
+    .B1(_1571_),
+    .B2(_0055_),
+    .X(_1572_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4040_ (.A(\u_uart_core.u_rxfsm.rxpos[2] ),
+    .Y(_1573_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4041_ (.A(\u_uart_core.u_rxfsm.offset[2] ),
+    .X(_1574_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4042_ (.A1_N(_1573_),
+    .A2_N(_1574_),
+    .B1(_1573_),
+    .B2(\u_uart_core.u_rxfsm.offset[2] ),
+    .X(_1575_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4043_ (.A(\u_uart_core.u_rxfsm.rxpos[1] ),
+    .Y(_1576_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4044_ (.A(\u_uart_core.u_rxfsm.offset[1] ),
+    .Y(_1577_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4045_ (.A1(\u_uart_core.u_rxfsm.rxpos[1] ),
+    .A2(\u_uart_core.u_rxfsm.offset[1] ),
+    .B1(_1576_),
+    .B2(_1577_),
+    .X(_1578_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4046_ (.A(_1570_),
+    .B(_1572_),
+    .C(_1575_),
+    .D(_1578_),
+    .X(_1579_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4047_ (.A(_1579_),
+    .X(_1580_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4048_ (.A1(_1566_),
+    .A2(_1567_),
+    .B1(_1580_),
+    .X(_1581_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4049_ (.A(\u_uart_core.u_rxfsm.rxstate[2] ),
+    .B(_1564_),
+    .C(_1554_),
+    .X(_1582_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4050_ (.A(_1582_),
+    .Y(_1583_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4051_ (.A1(_1579_),
+    .A2(_1550_),
+    .B1(_1583_),
+    .X(_1584_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4052_ (.A(_1557_),
+    .B(_1562_),
+    .C(_1581_),
+    .D(_1584_),
+    .X(_1585_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4053_ (.A(_1585_),
+    .Y(_1586_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4054_ (.A(_1554_),
+    .Y(_1587_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4055_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_be0.gen_bit_reg[4].u_bit_reg.data_out ),
+    .B(\u_uart_core.u_cfg.u_uart_ctrl_be0.gen_bit_reg[3].u_bit_reg.data_out ),
+    .X(_1588_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4056_ (.A1(_1587_),
+    .A2(_1588_),
+    .B1(_1563_),
+    .C1(_1564_),
+    .X(_1589_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4057_ (.A(_1551_),
+    .X(_1590_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4058_ (.A(_1544_),
+    .B(_1559_),
+    .C(_1503_),
+    .D(_1590_),
+    .X(_1591_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4059_ (.A(_1589_),
+    .B(_1591_),
+    .X(_1592_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4060_ (.A1(_1544_),
+    .A2(_1586_),
+    .B1(_1585_),
+    .B2(_1592_),
+    .X(_1593_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4061_ (.A(_1593_),
+    .Y(_0463_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4062_ (.A(_1583_),
+    .B(_1588_),
+    .X(_1594_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4063_ (.A(_1556_),
+    .B(_1594_),
+    .Y(_1595_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4064_ (.A1(_1564_),
+    .A2(_1586_),
+    .B1(_1585_),
+    .B2(_1595_),
+    .X(_1596_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4065_ (.A(_1596_),
+    .Y(_0462_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4066_ (.A(_1561_),
+    .X(_1597_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4067_ (.A(_1591_),
+    .Y(_1598_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4068_ (.A(_1597_),
+    .B(_1598_),
+    .C(_1594_),
+    .X(_1599_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4069_ (.A1_N(_1587_),
+    .A2_N(_1586_),
+    .B1(_1586_),
+    .B2(_1599_),
+    .X(_0461_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4070_ (.A(\u_uart_core.reg_ack ),
+    .Y(_1600_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4071_ (.A(\u_uart_core.app_rxfifo_empty ),
+    .B(_1600_),
+    .X(_1601_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4072_ (.A(reg_wr),
+    .B(_1004_),
+    .C(_1601_),
+    .D(_1052_),
+    .X(_1602_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4073_ (.A(psn_net_134),
+    .Y(_1603_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4074_ (.A(_1603_),
+    .B(_1498_),
+    .Y(_1604_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o32a_4 _4075_ (.A1(_1429_),
+    .A2(_1497_),
+    .A3(_1291_),
+    .B1(_1426_),
+    .B2(_1604_),
+    .X(_1605_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4076_ (.A(_1389_),
+    .B(_1296_),
+    .C(_1349_),
+    .D(_1605_),
+    .X(_1606_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4077_ (.A(_1606_),
+    .Y(_0460_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4078_ (.A(\u_uart_core.u_clk_ctl.high_count[10] ),
+    .Y(_1607_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4079_ (.A(_1029_),
+    .B(_1032_),
+    .X(_1608_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4080_ (.A(_1033_),
+    .B(_1608_),
+    .X(_1609_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4081_ (.A(_1037_),
+    .B(_1609_),
+    .X(_1610_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4082_ (.A(_1038_),
+    .B(_1610_),
+    .X(_1611_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4083_ (.A(_1041_),
+    .B(_1611_),
+    .X(_1612_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4084_ (.A(_1000_),
+    .B(_1612_),
+    .X(_1613_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4085_ (.A(_1011_),
+    .B(_1613_),
+    .X(_1614_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4086_ (.A(_1016_),
+    .B(_1614_),
+    .X(_1615_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4087_ (.A(_1017_),
+    .B(_1615_),
+    .X(_1616_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4088_ (.A(_1616_),
+    .Y(_1617_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4089_ (.A(_1026_),
+    .B(_1617_),
+    .X(_1618_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4090_ (.A(\u_uart_core.u_clk_ctl.high_count[1] ),
+    .B(\u_uart_core.u_clk_ctl.high_count[0] ),
+    .C(\u_uart_core.u_clk_ctl.high_count[2] ),
+    .X(_1619_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4091_ (.A(\u_uart_core.u_clk_ctl.high_count[3] ),
+    .B(_1619_),
+    .X(_1620_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4092_ (.A(\u_uart_core.u_clk_ctl.high_count[4] ),
+    .B(_1620_),
+    .X(_1621_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4093_ (.A(\u_uart_core.u_clk_ctl.high_count[5] ),
+    .B(_1621_),
+    .X(_1622_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4094_ (.A(\u_uart_core.u_clk_ctl.high_count[6] ),
+    .B(_1622_),
+    .X(_1623_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4095_ (.A(\u_uart_core.u_clk_ctl.high_count[7] ),
+    .B(_1623_),
+    .X(_1624_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4096_ (.A(\u_uart_core.u_clk_ctl.high_count[8] ),
+    .B(_1624_),
+    .X(_1625_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4097_ (.A(\u_uart_core.u_clk_ctl.high_count[9] ),
+    .B(_1625_),
+    .X(_1626_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4098_ (.A(_1541_),
+    .B(_1618_),
+    .Y(_1627_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4099_ (.A1(_1541_),
+    .A2(_1618_),
+    .B1(_1626_),
+    .C1(_1627_),
+    .X(_1628_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4100_ (.A(\u_uart_core.u_clk_ctl.high_count[10] ),
+    .B(_1626_),
+    .X(_1629_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4101_ (.A(_1629_),
+    .Y(_1630_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4102_ (.A(\u_uart_core.u_clk_ctl.low_count[1] ),
+    .B(\u_uart_core.u_clk_ctl.low_count[0] ),
+    .C(\u_uart_core.u_clk_ctl.low_count[2] ),
+    .X(_1631_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4103_ (.A(\u_uart_core.u_clk_ctl.low_count[3] ),
+    .B(_1631_),
+    .X(_1632_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4104_ (.A(\u_uart_core.u_clk_ctl.low_count[4] ),
+    .B(_1632_),
+    .X(_1633_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4105_ (.A(\u_uart_core.u_clk_ctl.low_count[5] ),
+    .B(_1633_),
+    .X(_1634_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4106_ (.A(\u_uart_core.u_clk_ctl.low_count[6] ),
+    .B(_1634_),
+    .X(_1635_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4107_ (.A(\u_uart_core.u_clk_ctl.low_count[7] ),
+    .B(_1635_),
+    .X(_1636_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4108_ (.A(\u_uart_core.u_clk_ctl.low_count[8] ),
+    .B(_1636_),
+    .C(\u_uart_core.u_clk_ctl.low_count[9] ),
+    .D(\u_uart_core.u_clk_ctl.low_count[10] ),
+    .X(_1637_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4109_ (.A(_1637_),
+    .X(_1638_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4110_ (.A(_1638_),
+    .X(_1639_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4111_ (.A(_1630_),
+    .B(_1639_),
+    .X(_1640_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4112_ (.A(_1607_),
+    .B(_1626_),
+    .Y(_1641_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4113_ (.A1(_1607_),
+    .A2(_1628_),
+    .B1(_1640_),
+    .C1(_1641_),
+    .X(_1642_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4114_ (.A(_1642_),
+    .Y(_0459_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4115_ (.A(_1027_),
+    .B(_1615_),
+    .X(_1643_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4116_ (.A(_1629_),
+    .B(_1638_),
+    .X(_1644_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4117_ (.A1(_1017_),
+    .A2(_1643_),
+    .B1(_1618_),
+    .C1(_1644_),
+    .X(_1645_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4118_ (.A(_1645_),
+    .Y(_1646_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4119_ (.A1(\u_uart_core.u_clk_ctl.high_count[9] ),
+    .A2(_1625_),
+    .B1(_1641_),
+    .C1(_1646_),
+    .X(_0458_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4120_ (.A(_1625_),
+    .Y(_1647_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4121_ (.A(\u_uart_core.u_clk_ctl.high_count[8] ),
+    .B(_1624_),
+    .X(_1648_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4122_ (.A(_1629_),
+    .X(_1649_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4123_ (.A(_1649_),
+    .X(_1650_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4124_ (.A(_1650_),
+    .X(_1651_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4125_ (.A(_1637_),
+    .Y(_1652_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4126_ (.A(_1652_),
+    .X(_1653_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4127_ (.A(_1613_),
+    .Y(_1654_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4128_ (.A(_1026_),
+    .B(_1654_),
+    .X(_1655_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4129_ (.A1(_1463_),
+    .A2(_1655_),
+    .B1(\u_uart_core.u_cfg.u_uart_ctrl_reg3.gen_bit_reg[1].u_bit_reg.data_out ),
+    .X(_1656_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4130_ (.A(_1653_),
+    .B(_1643_),
+    .C(_1656_),
+    .X(_1657_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4131_ (.A1(_1647_),
+    .A2(_1648_),
+    .B1(_1651_),
+    .B2(_1657_),
+    .X(_0457_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4132_ (.A(_1630_),
+    .X(_1658_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4133_ (.A(\u_uart_core.u_clk_ctl.high_count[7] ),
+    .Y(_1659_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4134_ (.A(_1623_),
+    .Y(_1660_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4135_ (.A1(_1659_),
+    .A2(_1660_),
+    .B1(_1624_),
+    .X(_1661_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4136_ (.A(_1644_),
+    .Y(_1662_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4137_ (.A(_1662_),
+    .X(_1663_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4138_ (.A1(_1028_),
+    .A2(_1614_),
+    .B1(_1463_),
+    .B2(_1655_),
+    .X(_1664_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4139_ (.A1_N(_1658_),
+    .A2_N(_1661_),
+    .B1(_1663_),
+    .B2(_1664_),
+    .X(_0456_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4140_ (.A(_1027_),
+    .B(_1612_),
+    .X(_1665_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4141_ (.A1(_1000_),
+    .A2(_1665_),
+    .B1(_1655_),
+    .C1(_1639_),
+    .X(_1666_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4142_ (.A(_1666_),
+    .Y(_1667_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4143_ (.A(\u_uart_core.u_clk_ctl.high_count[6] ),
+    .B(_1622_),
+    .X(_1668_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4144_ (.A1(_1651_),
+    .A2(_1667_),
+    .B1(_1660_),
+    .B2(_1668_),
+    .X(_0455_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4145_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[0].u_bit_reg.data_out ),
+    .B(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[1].u_bit_reg.data_out ),
+    .C(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[2].u_bit_reg.data_out ),
+    .X(_1669_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4146_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[3].u_bit_reg.data_out ),
+    .B(_1669_),
+    .X(_1670_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4147_ (.A(_1670_),
+    .Y(_1671_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4148_ (.A(_1037_),
+    .B(_1671_),
+    .X(_1672_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4149_ (.A(_1039_),
+    .B(_1672_),
+    .X(_1673_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4150_ (.A(_1041_),
+    .B(_1673_),
+    .Y(_1674_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4151_ (.A(_1649_),
+    .X(_1675_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4152_ (.A1(\u_uart_core.u_clk_ctl.high_count[5] ),
+    .A2(_1621_),
+    .B1_N(_1622_),
+    .X(_1676_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4153_ (.A1(_1665_),
+    .A2(_1674_),
+    .A3(_1663_),
+    .B1(_1675_),
+    .B2(_1676_),
+    .X(_0454_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4154_ (.A(_1039_),
+    .B(_1672_),
+    .Y(_1677_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4155_ (.A1(\u_uart_core.u_clk_ctl.high_count[4] ),
+    .A2(_1620_),
+    .B1_N(_1621_),
+    .X(_1678_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4156_ (.A1(_1673_),
+    .A2(_1677_),
+    .A3(_1663_),
+    .B1(_1675_),
+    .B2(_1678_),
+    .X(_0453_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4157_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[4].u_bit_reg.data_out ),
+    .B(_1670_),
+    .X(_1679_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4158_ (.A(_1649_),
+    .X(_1680_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4159_ (.A1(\u_uart_core.u_clk_ctl.high_count[3] ),
+    .A2(_1619_),
+    .B1_N(_1620_),
+    .X(_1681_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4160_ (.A1(_1672_),
+    .A2(_1679_),
+    .A3(_1663_),
+    .B1(_1680_),
+    .B2(_1681_),
+    .X(_0452_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4161_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[3].u_bit_reg.data_out ),
+    .B(_1669_),
+    .X(_1682_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4162_ (.A(\u_uart_core.u_clk_ctl.high_count[2] ),
+    .Y(_1683_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4163_ (.A(\u_uart_core.u_clk_ctl.high_count[1] ),
+    .B(\u_uart_core.u_clk_ctl.high_count[0] ),
+    .Y(_1684_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _4164_ (.A1(_1683_),
+    .A2(_1684_),
+    .B1(_1619_),
+    .Y(_1685_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4165_ (.A1(_1671_),
+    .A2(_1682_),
+    .A3(_1662_),
+    .B1(_1680_),
+    .B2(_1685_),
+    .X(_0451_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4166_ (.A1(_1027_),
+    .A2(_1029_),
+    .B1(_1032_),
+    .X(_1686_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4167_ (.A(_1669_),
+    .B(_1686_),
+    .C(_1639_),
+    .X(_1687_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4168_ (.A(_1687_),
+    .Y(_1688_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4169_ (.A(\u_uart_core.u_clk_ctl.high_count[1] ),
+    .B(\u_uart_core.u_clk_ctl.high_count[0] ),
+    .X(_1689_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4170_ (.A1(_1675_),
+    .A2(_1688_),
+    .B1(_1684_),
+    .B2(_1689_),
+    .X(_0450_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4171_ (.A1_N(_1028_),
+    .A2_N(_1030_),
+    .B1(_1028_),
+    .B2(_1030_),
+    .X(_1690_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4172_ (.A1(_1630_),
+    .A2(_1690_),
+    .B1(_1640_),
+    .C1(\u_uart_core.u_clk_ctl.high_count[0] ),
+    .X(_1691_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4173_ (.A(_1691_),
+    .Y(_0449_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4174_ (.A(reg_wdata[2]),
+    .Y(_1692_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4175_ (.A(_1008_),
+    .B(_1522_),
+    .X(_1693_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4176_ (.A(_1692_),
+    .B(_1693_),
+    .X(_1694_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4177_ (.A1(\u_uart_core.u_cfg.u_intr_bit2.data_out ),
+    .A2(_1694_),
+    .B1(\u_uart_core.rx_fifo_full_err_o ),
+    .X(_0448_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4178_ (.A(reg_wdata[1]),
+    .Y(_1695_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4179_ (.A(_1695_),
+    .B(_1693_),
+    .X(_1696_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4180_ (.A1(\u_uart_core.u_cfg.u_intr_bit1.data_out ),
+    .A2(_1696_),
+    .B1(\u_uart_core.par_error_o ),
+    .X(_0447_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4181_ (.A(reg_wdata[0]),
+    .Y(_1697_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4182_ (.A(_1697_),
+    .B(_1693_),
+    .X(_1698_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4183_ (.A1(\u_uart_core.u_cfg.u_intr_bit0.data_out ),
+    .A2(_1698_),
+    .B1(\u_uart_core.frm_error_o ),
+    .X(_0446_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4184_ (.A(\u_i2cm.core_en ),
+    .Y(_1699_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4185_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.sSCL ),
+    .Y(_1700_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4186_ (.A(\u_i2cm.scl_padoen_o ),
+    .B(_1700_),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.dSCL ),
+    .X(_1701_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4187_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[2] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[1] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[0] ),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[3] ),
+    .X(_1702_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4188_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[5] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[4] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[7] ),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[6] ),
+    .X(_1703_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4189_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[12] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[11] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[13] ),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[10] ),
+    .X(_1704_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4190_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[15] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[14] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[9] ),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[8] ),
+    .X(_1705_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4191_ (.A(_1702_),
+    .B(_1703_),
+    .C(_1704_),
+    .D(_1705_),
+    .X(_1706_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4192_ (.A(_1706_),
+    .Y(_1707_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4193_ (.A(_1699_),
+    .B(_1701_),
+    .C(_1707_),
+    .X(_1708_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4194_ (.A(_1708_),
+    .Y(_1709_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4195_ (.A(_1709_),
+    .X(_1710_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4196_ (.A(_1708_),
+    .X(_1711_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4197_ (.A(_1711_),
+    .X(_1712_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4198_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.slave_wait ),
+    .B(_1702_),
+    .X(_1713_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4199_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[4] ),
+    .B(_1713_),
+    .X(_1714_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4200_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[5] ),
+    .B(_1714_),
+    .X(_1715_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4201_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[6] ),
+    .B(_1715_),
+    .X(_1716_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4202_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[7] ),
+    .B(_1716_),
+    .X(_1717_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4203_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[8] ),
+    .B(_1717_),
+    .X(_1718_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4204_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[9] ),
+    .B(_1718_),
+    .X(_1719_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4205_ (.A(_1704_),
+    .B(_1719_),
+    .X(_1720_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4206_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[14] ),
+    .A2(_1720_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[15] ),
+    .X(_1721_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4207_ (.A1(\u_i2cm.prer[15] ),
+    .A2(_1710_),
+    .B1(_1712_),
+    .B2(_1721_),
+    .X(_0445_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4208_ (.A(_1709_),
+    .X(_1722_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4209_ (.A(_1722_),
+    .X(_1723_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4210_ (.A1_N(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[14] ),
+    .A2_N(_1720_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[14] ),
+    .B2(_1720_),
+    .X(_1724_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4211_ (.A1_N(_1526_),
+    .A2_N(_1723_),
+    .B1(_1723_),
+    .B2(_1724_),
+    .X(_0444_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4212_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[10] ),
+    .B(_1719_),
+    .X(_1725_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4213_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[11] ),
+    .B(_1725_),
+    .X(_1726_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4214_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[12] ),
+    .B(_1726_),
+    .X(_1727_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4215_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[13] ),
+    .B(_1727_),
+    .Y(_1728_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4216_ (.A(_1708_),
+    .X(_1729_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4217_ (.A1(_1722_),
+    .A2(_1720_),
+    .A3(_1728_),
+    .B1(_1527_),
+    .B2(_1729_),
+    .X(_1730_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4218_ (.A(_1730_),
+    .Y(_0443_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4219_ (.A(_1708_),
+    .X(_1731_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4220_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[12] ),
+    .A2(_1726_),
+    .B1_N(_1727_),
+    .Y(_1732_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4221_ (.A1(_1529_),
+    .A2(_1710_),
+    .B1(_1731_),
+    .B2(_1732_),
+    .X(_1733_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4222_ (.A(_1733_),
+    .Y(_0442_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4223_ (.A(_1711_),
+    .X(_0019_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4224_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[11] ),
+    .A2(_1725_),
+    .B1_N(_1726_),
+    .Y(_1734_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4225_ (.A1_N(_0019_),
+    .A2_N(_1734_),
+    .B1(\u_i2cm.prer[11] ),
+    .B2(_0019_),
+    .X(_0441_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4226_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[10] ),
+    .A2(_1719_),
+    .B1_N(_1725_),
+    .Y(_1735_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4227_ (.A1(_1534_),
+    .A2(_1710_),
+    .B1(_1731_),
+    .B2(_1735_),
+    .X(_1736_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4228_ (.A(_1736_),
+    .Y(_0440_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4229_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[9] ),
+    .A2(_1718_),
+    .B1_N(_1719_),
+    .Y(_1737_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4230_ (.A1_N(_0019_),
+    .A2_N(_1737_),
+    .B1(\u_i2cm.prer[9] ),
+    .B2(_1712_),
+    .X(_0439_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4231_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[8] ),
+    .A2(_1717_),
+    .B1_N(_1718_),
+    .Y(_1738_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4232_ (.A1(_1538_),
+    .A2(_1710_),
+    .B1(_1731_),
+    .B2(_1738_),
+    .X(_1739_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4233_ (.A(_1739_),
+    .Y(_0438_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4234_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[7] ),
+    .A2(_1716_),
+    .B1_N(_1717_),
+    .Y(_1740_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4235_ (.A1_N(_1712_),
+    .A2_N(_1740_),
+    .B1(\u_i2cm.prer[7] ),
+    .B2(_1712_),
+    .X(_0437_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4236_ (.A(_1709_),
+    .X(_1741_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4237_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[6] ),
+    .A2(_1715_),
+    .B1_N(_1716_),
+    .Y(_1742_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4238_ (.A1(_1508_),
+    .A2(_1741_),
+    .B1(_1731_),
+    .B2(_1742_),
+    .X(_1743_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4239_ (.A(_1743_),
+    .Y(_0436_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4240_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[5] ),
+    .B(_1714_),
+    .Y(_1744_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4241_ (.A1(_1722_),
+    .A2(_1715_),
+    .A3(_1744_),
+    .B1(_1509_),
+    .B2(_1729_),
+    .X(_1745_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4242_ (.A(_1745_),
+    .Y(_0435_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4243_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[4] ),
+    .A2(_1713_),
+    .B1_N(_1714_),
+    .Y(_1746_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4244_ (.A1(_1511_),
+    .A2(_1741_),
+    .B1(_1729_),
+    .B2(_1746_),
+    .X(_1747_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4245_ (.A(_1747_),
+    .Y(_0434_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4246_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[0] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.slave_wait ),
+    .X(_1748_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4247_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[1] ),
+    .B(_1748_),
+    .X(_1749_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _4248_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[2] ),
+    .A2(_1749_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[3] ),
+    .Y(_1750_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4249_ (.A1(_1713_),
+    .A2(_1750_),
+    .A3(_1741_),
+    .B1(_1512_),
+    .B2(_1711_),
+    .X(_1751_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4250_ (.A(_1751_),
+    .Y(_0433_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4251_ (.A1_N(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[2] ),
+    .A2_N(_1749_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[2] ),
+    .B2(_1749_),
+    .X(_1752_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4252_ (.A1_N(_1514_),
+    .A2_N(_1723_),
+    .B1(_1723_),
+    .B2(_1752_),
+    .X(_0432_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21boi_4 _4253_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[1] ),
+    .A2(_1748_),
+    .B1_N(_1749_),
+    .Y(_1753_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4254_ (.A1(_1515_),
+    .A2(_1741_),
+    .B1(_1729_),
+    .B2(_1753_),
+    .X(_1754_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4255_ (.A(_1754_),
+    .Y(_0431_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4256_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.cnt[0] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.slave_wait ),
+    .Y(_1755_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4257_ (.A1(_1748_),
+    .A2(_1755_),
+    .A3(_1722_),
+    .B1(_1518_),
+    .B2(_1711_),
+    .X(_1756_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4258_ (.A(_1756_),
+    .Y(_0430_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4259_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[16] ),
+    .X(_1757_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4260_ (.A(_1757_),
+    .X(_1758_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4261_ (.A(_1758_),
+    .X(_1759_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4262_ (.A(_1759_),
+    .Y(_1760_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4263_ (.A(\u_i2cm.i2c_al ),
+    .Y(_1761_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4264_ (.A(_1761_),
+    .X(_1762_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4265_ (.A(_0581_),
+    .B(_1762_),
+    .X(_1763_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4266_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[15] ),
+    .Y(_1764_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4267_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[14] ),
+    .X(_1765_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4268_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[13] ),
+    .X(_1766_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4269_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[12] ),
+    .X(_1767_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4270_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[3] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[2] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[6] ),
+    .X(_1768_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4271_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[1] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[0] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[7] ),
+    .D(_1768_),
+    .X(_1769_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4272_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[4] ),
+    .B(_1769_),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[5] ),
+    .X(_1770_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4273_ (.A(_1770_),
+    .X(_1771_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4274_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[11] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[10] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[8] ),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[9] ),
+    .X(_1772_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4275_ (.A(_1766_),
+    .B(_1767_),
+    .C(_1771_),
+    .D(_1772_),
+    .X(_1773_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4276_ (.A(_1759_),
+    .B(_1764_),
+    .C(_1765_),
+    .D(_1773_),
+    .X(_1774_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4277_ (.A(_1774_),
+    .Y(_1775_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4278_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[9] ),
+    .X(_1776_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4279_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[8] ),
+    .Y(_1777_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4280_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[11] ),
+    .X(_1778_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4281_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[13] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[12] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[15] ),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[14] ),
+    .X(_1779_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4282_ (.A(_1778_),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[10] ),
+    .C(_1771_),
+    .D(_1779_),
+    .X(_1780_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4283_ (.A(_1780_),
+    .Y(_1781_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _4284_ (.A(_1760_),
+    .B(_1776_),
+    .C(_1777_),
+    .D(_1781_),
+    .X(_1782_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4285_ (.A(_1778_),
+    .Y(_1783_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4286_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[10] ),
+    .X(_1784_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4287_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[16] ),
+    .B(_1779_),
+    .C(_1770_),
+    .D(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[9] ),
+    .X(_1785_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4288_ (.A(_1785_),
+    .Y(_1786_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _4289_ (.A(_1783_),
+    .B(_1784_),
+    .C(_1777_),
+    .D(_1786_),
+    .X(_1787_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4290_ (.A(_1782_),
+    .B(_1787_),
+    .X(_1788_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4291_ (.A(_1773_),
+    .Y(_1789_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _4292_ (.A(_1760_),
+    .B(_1764_),
+    .C(_1765_),
+    .D(_1789_),
+    .X(_1790_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4293_ (.A(_1779_),
+    .B(_1772_),
+    .X(_1791_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4294_ (.A(_1791_),
+    .X(_1792_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4295_ (.A(_1771_),
+    .B(_1792_),
+    .Y(_1793_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4296_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[3] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[2] ),
+    .X(_1794_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4297_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[3] ),
+    .X(_1795_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4298_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[2] ),
+    .X(_1796_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4299_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[6] ),
+    .X(_1797_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4300_ (.A1(_1795_),
+    .A2(_1796_),
+    .B1(_1797_),
+    .X(_1798_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4301_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[1] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[0] ),
+    .C(_1794_),
+    .D(_1798_),
+    .X(_1799_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4302_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[4] ),
+    .X(_1800_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4303_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[7] ),
+    .X(_1801_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4304_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[5] ),
+    .B(_1800_),
+    .C(_1757_),
+    .D(_1801_),
+    .X(_1802_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4305_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[0] ),
+    .Y(_1803_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21oi_4 _4306_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[1] ),
+    .A2(_1803_),
+    .B1(_1768_),
+    .Y(_1804_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2111o_4 _4307_ (.A1(_1768_),
+    .A2(_1799_),
+    .B1(_1792_),
+    .C1(_1802_),
+    .D1(_1804_),
+    .X(_1805_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4308_ (.A(_1805_),
+    .Y(_1806_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4309_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[5] ),
+    .X(_1807_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4310_ (.A(_1800_),
+    .Y(_1808_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4311_ (.A(_1807_),
+    .B(_1808_),
+    .Y(_1809_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4312_ (.A(_1758_),
+    .B(_1769_),
+    .C(_1809_),
+    .D(_1792_),
+    .X(_1810_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4313_ (.A(_1810_),
+    .Y(_1811_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4314_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[1] ),
+    .X(_1812_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4315_ (.A(_1795_),
+    .B(_1796_),
+    .C(_1757_),
+    .X(_1813_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4316_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[5] ),
+    .B(_1791_),
+    .X(_1814_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4317_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[7] ),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[4] ),
+    .C(_1797_),
+    .D(_1814_),
+    .X(_1815_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4318_ (.A(_1812_),
+    .B(_1803_),
+    .C(_1813_),
+    .D(_1815_),
+    .X(_1816_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4319_ (.A(_1816_),
+    .Y(_1817_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4320_ (.A(_1806_),
+    .B(_1811_),
+    .C(_1817_),
+    .X(_1818_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4321_ (.A(_1758_),
+    .B(_1808_),
+    .C(_1769_),
+    .D(_1814_),
+    .X(_1819_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4322_ (.A(_1819_),
+    .Y(_1820_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4323_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[13] ),
+    .Y(_1821_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4324_ (.A(_1757_),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[15] ),
+    .C(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[14] ),
+    .X(_1822_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4325_ (.A(_1771_),
+    .B(_1772_),
+    .X(_1823_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4326_ (.A(_1821_),
+    .B(_1767_),
+    .C(_1822_),
+    .D(_1823_),
+    .X(_1824_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4327_ (.A(_1824_),
+    .Y(_1825_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4328_ (.A(_1820_),
+    .B(_1825_),
+    .X(_1826_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4329_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[8] ),
+    .B(_1785_),
+    .C(_1783_),
+    .D(_1784_),
+    .X(_1827_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4330_ (.A(_1827_),
+    .Y(_1828_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4331_ (.A(_1767_),
+    .Y(_1829_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4332_ (.A(_1766_),
+    .B(_1829_),
+    .C(_1822_),
+    .D(_1823_),
+    .X(_1830_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4333_ (.A(_1830_),
+    .Y(_1831_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4334_ (.A(_1758_),
+    .B(_1776_),
+    .C(_1777_),
+    .D(_1780_),
+    .X(_1832_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4335_ (.A(_1832_),
+    .Y(_1833_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4336_ (.A(_1828_),
+    .B(_1831_),
+    .C(_1833_),
+    .X(_1834_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4337_ (.A(_1793_),
+    .B(_1818_),
+    .C(_1826_),
+    .D(_1834_),
+    .X(_1835_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4338_ (.A(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[0] ),
+    .X(_1836_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4339_ (.A(_1801_),
+    .Y(_1837_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4340_ (.A(_1759_),
+    .B(_1807_),
+    .C(_1837_),
+    .D(_1800_),
+    .X(_1838_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4341_ (.A(_1812_),
+    .B(_1836_),
+    .C(_1768_),
+    .D(_1838_),
+    .X(_1839_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _4342_ (.A1(_1792_),
+    .A2(_1839_),
+    .B1(_1827_),
+    .Y(_1840_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4343_ (.A(_1788_),
+    .B(_1790_),
+    .C(_1835_),
+    .D(_1840_),
+    .X(_1841_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4344_ (.A(_0581_),
+    .B(\u_i2cm.i2c_al ),
+    .C(_1775_),
+    .D(_1841_),
+    .X(_1842_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4345_ (.A(_1842_),
+    .Y(_1843_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4346_ (.A(_1763_),
+    .B(_1843_),
+    .X(_1844_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4347_ (.A(_1844_),
+    .Y(_1845_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4348_ (.A(_1845_),
+    .X(_1846_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4349_ (.A(_1846_),
+    .X(_1847_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4350_ (.A(_0566_),
+    .B(_1841_),
+    .C(_1844_),
+    .X(_1848_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _4351_ (.A1(_1760_),
+    .A2(_1847_),
+    .B1(_1848_),
+    .Y(_0429_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4352_ (.A(_1762_),
+    .X(_1849_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4353_ (.A(_1849_),
+    .X(_1850_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4354_ (.A(_1850_),
+    .X(_1851_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4355_ (.A(_1851_),
+    .X(_1852_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4356_ (.A(_1844_),
+    .X(_1853_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4357_ (.A1(_1765_),
+    .A2(_1852_),
+    .A3(_1847_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[15] ),
+    .B2(_1853_),
+    .X(_0428_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4358_ (.A1(_1766_),
+    .A2(_1852_),
+    .A3(_1847_),
+    .B1(_1765_),
+    .B2(_1853_),
+    .X(_0427_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4359_ (.A(_1812_),
+    .Y(_1854_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4360_ (.A(_1854_),
+    .B(_1836_),
+    .C(_1813_),
+    .D(_1815_),
+    .X(_1855_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4361_ (.A(_1855_),
+    .Y(_1856_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4362_ (.A(_1825_),
+    .B(_1775_),
+    .C(_1840_),
+    .X(_1857_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4363_ (.A(_1759_),
+    .B(_1793_),
+    .X(_1858_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4364_ (.A(_1831_),
+    .B(_1858_),
+    .C(_1820_),
+    .D(_1833_),
+    .X(_1859_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4365_ (.A(_1788_),
+    .B(_1790_),
+    .C(_1857_),
+    .D(_1859_),
+    .X(_1860_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4366_ (.A(_0565_),
+    .B(_1856_),
+    .C(_1818_),
+    .D(_1860_),
+    .X(_1861_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4367_ (.A(_1861_),
+    .Y(_1862_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4368_ (.A(_1862_),
+    .X(_1863_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4369_ (.A1(\u_i2cm.u_byte_ctrl.core_cmd[2] ),
+    .A2(_1863_),
+    .A3(_1847_),
+    .B1(_1766_),
+    .B2(_1853_),
+    .X(_0426_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4370_ (.A(_1851_),
+    .X(_1864_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4371_ (.A(_1846_),
+    .X(_1865_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4372_ (.A(_1844_),
+    .X(_1866_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4373_ (.A(_1866_),
+    .X(_1867_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4374_ (.A1(_1778_),
+    .A2(_1864_),
+    .A3(_1865_),
+    .B1(_1767_),
+    .B2(_1867_),
+    .X(_0425_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4375_ (.A1(_1784_),
+    .A2(_1864_),
+    .A3(_1865_),
+    .B1(_1778_),
+    .B2(_1867_),
+    .X(_0424_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4376_ (.A1(_1776_),
+    .A2(_1864_),
+    .A3(_1865_),
+    .B1(_1784_),
+    .B2(_1867_),
+    .X(_0423_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4377_ (.A1(\u_i2cm.u_byte_ctrl.core_cmd[1] ),
+    .A2(_1863_),
+    .A3(_1865_),
+    .B1(_1776_),
+    .B2(_1867_),
+    .X(_0422_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4378_ (.A(_1846_),
+    .X(_1868_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4379_ (.A(_1866_),
+    .X(_1869_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4380_ (.A1(_1801_),
+    .A2(_1864_),
+    .A3(_1868_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.c_state[8] ),
+    .B2(_1869_),
+    .X(_0421_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4381_ (.A(_1851_),
+    .X(_1870_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4382_ (.A1(_1797_),
+    .A2(_1870_),
+    .A3(_1868_),
+    .B1(_1801_),
+    .B2(_1869_),
+    .X(_0420_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4383_ (.A1(_1807_),
+    .A2(_1870_),
+    .A3(_1868_),
+    .B1(_1797_),
+    .B2(_1869_),
+    .X(_0419_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4384_ (.A1(\u_i2cm.u_byte_ctrl.core_cmd[3] ),
+    .A2(_1863_),
+    .A3(_1868_),
+    .B1(_1807_),
+    .B2(_1869_),
+    .X(_0418_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4385_ (.A(_1845_),
+    .X(_1871_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4386_ (.A(_1866_),
+    .X(_1872_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4387_ (.A1(_1795_),
+    .A2(_1870_),
+    .A3(_1871_),
+    .B1(_1800_),
+    .B2(_1872_),
+    .X(_0417_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4388_ (.A1(_1796_),
+    .A2(_1870_),
+    .A3(_1871_),
+    .B1(_1795_),
+    .B2(_1872_),
+    .X(_0416_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4389_ (.A1(_1852_),
+    .A2(_1856_),
+    .A3(_1871_),
+    .B1(_1796_),
+    .B2(_1872_),
+    .X(_0415_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4390_ (.A(_1849_),
+    .X(_1873_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4391_ (.A(_1873_),
+    .X(_1874_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4392_ (.A1(_1836_),
+    .A2(_1874_),
+    .A3(_1871_),
+    .B1(_1812_),
+    .B2(_1872_),
+    .X(_0414_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4393_ (.A1(\u_i2cm.u_byte_ctrl.core_cmd[4] ),
+    .A2(_1863_),
+    .A3(_1846_),
+    .B1(_1836_),
+    .B2(_1866_),
+    .X(_0413_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4394_ (.A(\u_uart_core.u_rxfifo.wr_ptr[2] ),
+    .Y(_1875_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4395_ (.A(_1875_),
+    .X(_1876_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4396_ (.A(\u_uart_core.u_rxfifo.wr_ptr[1] ),
+    .Y(_1877_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4397_ (.A(_1877_),
+    .X(_1878_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4398_ (.A(\u_uart_core.u_rxfifo.wr_ptr[0] ),
+    .Y(_1879_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4399_ (.A(_1879_),
+    .X(_1880_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4400_ (.A(_1878_),
+    .B(_1880_),
+    .X(_1881_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4401_ (.A(_1881_),
+    .X(_1882_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4402_ (.A(\u_uart_core.rx_fifo_wr ),
+    .Y(_1883_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4403_ (.A(_1883_),
+    .X(_1884_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4404_ (.A(\u_uart_core.u_rxfifo.wr_ptr[3] ),
+    .Y(_1885_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4405_ (.A(_1885_),
+    .X(_1886_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4406_ (.A(_1876_),
+    .B(_1882_),
+    .C(_1884_),
+    .D(_1886_),
+    .X(_1887_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4407_ (.A(_1887_),
+    .Y(_1888_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4408_ (.A(_1888_),
+    .X(_1889_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4409_ (.A(\u_uart_core.u_rxfifo.grey_wr_ptr[4] ),
+    .Y(_1890_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4410_ (.A(_1890_),
+    .X(_1891_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4411_ (.A1(\u_uart_core.u_rxfifo.grey_wr_ptr[4] ),
+    .A2(_1889_),
+    .B1(_1891_),
+    .B2(_1887_),
+    .X(_0412_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4412_ (.A(\u_uart_core.rx_fifo_wr ),
+    .X(_1892_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4413_ (.A(_1892_),
+    .X(_1893_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4414_ (.A(_1886_),
+    .X(_1894_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4415_ (.A1(_1876_),
+    .A2(_1882_),
+    .B1(_1894_),
+    .X(_1895_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4416_ (.A(_1891_),
+    .B(_1895_),
+    .Y(_1896_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4417_ (.A(_1891_),
+    .B(_1895_),
+    .X(_1897_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4418_ (.A(_1884_),
+    .X(_1898_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4419_ (.A(_1898_),
+    .X(_1899_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4420_ (.A1(_1893_),
+    .A2(_1896_),
+    .A3(_1897_),
+    .B1(_1899_),
+    .B2(\u_uart_core.u_rxfifo.grey_wr_ptr[3] ),
+    .X(_0411_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4421_ (.A(\u_uart_core.u_rxfifo.wr_ptr[2] ),
+    .X(_1900_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4422_ (.A(_1882_),
+    .Y(_1901_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4423_ (.A(\u_uart_core.u_rxfifo.wr_ptr[3] ),
+    .X(_1902_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4424_ (.A(_1900_),
+    .B(_1901_),
+    .C(_1902_),
+    .X(_1903_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4425_ (.A(_1876_),
+    .X(_1904_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4426_ (.A1(_1904_),
+    .A2(_1882_),
+    .B1(_1894_),
+    .X(_1905_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4427_ (.A1(_1892_),
+    .A2(_1903_),
+    .A3(_1905_),
+    .B1(_1899_),
+    .B2(\u_uart_core.u_rxfifo.grey_wr_ptr[2] ),
+    .X(_0410_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4428_ (.A(\u_uart_core.u_rxfifo.wr_ptr[1] ),
+    .X(_1906_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4429_ (.A(\u_uart_core.u_rxfifo.wr_ptr[0] ),
+    .X(_1907_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4430_ (.A(_1907_),
+    .X(_1908_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4431_ (.A(_1906_),
+    .B(_1908_),
+    .X(_1909_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4432_ (.A(_1900_),
+    .B(_1909_),
+    .Y(_1910_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4433_ (.A(_1900_),
+    .B(_1909_),
+    .X(_1911_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4434_ (.A1(_1892_),
+    .A2(_1910_),
+    .A3(_1911_),
+    .B1(_1899_),
+    .B2(\u_uart_core.u_rxfifo.grey_wr_ptr[1] ),
+    .X(_0409_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4435_ (.A(_1878_),
+    .X(_1912_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4436_ (.A1(_1899_),
+    .A2(_1912_),
+    .B1(_1893_),
+    .B2(\u_uart_core.u_rxfifo.grey_wr_ptr[0] ),
+    .X(_0408_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4437_ (.A(\u_uart_core.u_rxfifo.wr_ptr[1] ),
+    .X(_1913_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4438_ (.A(_1913_),
+    .X(_1914_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _4439_ (.A(_1914_),
+    .B(_1908_),
+    .C(_1892_),
+    .D(_1900_),
+    .X(_1915_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4440_ (.A(_1884_),
+    .B(_1881_),
+    .X(_1916_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4441_ (.A(\u_uart_core.u_rxfifo.wr_ptr[3] ),
+    .B(_1876_),
+    .X(_1917_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4442_ (.A(_1916_),
+    .B(_1917_),
+    .X(_1918_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _4443_ (.A1(_1894_),
+    .A2(_1915_),
+    .B1(_1918_),
+    .Y(_0407_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21oi_4 _4444_ (.A1(_1904_),
+    .A2(_1916_),
+    .B1(_1915_),
+    .Y(_0406_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4445_ (.A(_1880_),
+    .X(_1919_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4446_ (.A(_1898_),
+    .B(_1919_),
+    .X(_1920_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4447_ (.A1_N(_1914_),
+    .A2_N(_1920_),
+    .B1(_1914_),
+    .B2(_1920_),
+    .X(_0405_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4448_ (.A1(_1893_),
+    .A2(_1908_),
+    .B1(_1920_),
+    .X(_0404_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4449_ (.A(_1481_),
+    .B(_1484_),
+    .X(_1921_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4450_ (.A(_1921_),
+    .B(_1602_),
+    .X(_1922_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4451_ (.A(_1468_),
+    .B(_1922_),
+    .X(_1923_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4452_ (.A(psn_net_131),
+    .Y(_1924_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4453_ (.A(_1059_),
+    .B(_1923_),
+    .X(_1925_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4454_ (.A1(_1489_),
+    .A2(_1924_),
+    .A3(_1276_),
+    .B1(_1925_),
+    .B2(\u_uart_core.u_rxfifo.grey_rd_ptr[4] ),
+    .X(_0403_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4455_ (.A1(_1489_),
+    .A2(_1924_),
+    .B1(psn_net_130),
+    .X(_0402_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4456_ (.A(_1468_),
+    .X(_1926_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21oi_4 _4457_ (.A1(_1926_),
+    .A2(psn_net_133),
+    .B1(psn_net_185),
+    .Y(_0401_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4458_ (.A(_1486_),
+    .B(psn_net_164),
+    .X(_1927_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4459_ (.A1(_1125_),
+    .A2(_1927_),
+    .B1(psn_net_132),
+    .X(_0400_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4460_ (.A(_1602_),
+    .X(_1928_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21oi_4 _4461_ (.A1(_1484_),
+    .A2(_1928_),
+    .B1(_1927_),
+    .Y(_0399_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4462_ (.A(psn_net_164),
+    .X(_1929_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4463_ (.A1(_1926_),
+    .A2(_1921_),
+    .B1(_1059_),
+    .X(_1930_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4464_ (.A(_1276_),
+    .B(_1930_),
+    .Y(_1931_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4465_ (.A(_1276_),
+    .B(_1930_),
+    .X(_1932_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4466_ (.A1(_1929_),
+    .A2(_1931_),
+    .A3(_1932_),
+    .B1(\u_uart_core.u_rxfifo.grey_rd_ptr[3] ),
+    .B2(_1928_),
+    .X(_0398_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4467_ (.A(_1921_),
+    .Y(_1933_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4468_ (.A(_1114_),
+    .B(_1933_),
+    .C(_1489_),
+    .X(_1934_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4469_ (.A1(_1926_),
+    .A2(_1921_),
+    .B1(_1059_),
+    .X(_1935_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4470_ (.A1(_1929_),
+    .A2(_1934_),
+    .A3(_1935_),
+    .B1(\u_uart_core.u_rxfifo.grey_rd_ptr[2] ),
+    .B2(_1928_),
+    .X(_0397_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4471_ (.A1(_1481_),
+    .A2(_1484_),
+    .B1(_1926_),
+    .X(_1936_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4472_ (.A(_1125_),
+    .B(_1486_),
+    .C(_1114_),
+    .X(_1937_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4473_ (.A1(_1936_),
+    .A2(_1937_),
+    .A3(_1929_),
+    .B1(\u_uart_core.u_rxfifo.grey_rd_ptr[1] ),
+    .B2(psn_net_135),
+    .X(_0396_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4474_ (.A1(_1481_),
+    .A2(_1928_),
+    .B1(\u_uart_core.u_rxfifo.grey_rd_ptr[0] ),
+    .B2(_1929_),
+    .X(_0395_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4475_ (.A(_1542_),
+    .B(_1616_),
+    .X(_1938_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4476_ (.A(_1541_),
+    .B(_1617_),
+    .X(_1939_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4477_ (.A(\u_uart_core.u_clk_ctl.low_count[8] ),
+    .X(_1940_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4478_ (.A(_1636_),
+    .X(_1941_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4479_ (.A(_1940_),
+    .B(_1941_),
+    .C(_1629_),
+    .X(_1942_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4480_ (.A(\u_uart_core.u_clk_ctl.low_count[9] ),
+    .B(_1942_),
+    .X(_1943_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4481_ (.A1(_1938_),
+    .A2(_1939_),
+    .A3(_1662_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[10] ),
+    .B2(_1943_),
+    .X(_0394_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4482_ (.A(\u_uart_core.u_clk_ctl.low_count[10] ),
+    .Y(_1944_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4483_ (.A1(_1017_),
+    .A2(_1615_),
+    .B1(_1617_),
+    .X(_1945_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4484_ (.A1(_1944_),
+    .A2(_1945_),
+    .B1(_1943_),
+    .X(_1946_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4485_ (.A1(\u_uart_core.u_clk_ctl.low_count[9] ),
+    .A2(_1942_),
+    .B1_N(_1946_),
+    .X(_0393_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4486_ (.A1_N(_1940_),
+    .A2_N(_1941_),
+    .B1(_1940_),
+    .B2(_1941_),
+    .X(_1947_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4487_ (.A(_1016_),
+    .B(_1614_),
+    .Y(_1948_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4488_ (.A(_1638_),
+    .X(_1949_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4489_ (.A1(_1615_),
+    .A2(_1948_),
+    .B1(_1949_),
+    .X(_1950_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4490_ (.A1(_1630_),
+    .A2(_1947_),
+    .A3(_1950_),
+    .B1(_1940_),
+    .B2(_1680_),
+    .X(_0392_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4491_ (.A1(_1463_),
+    .A2(_1654_),
+    .B1(_1614_),
+    .X(_1951_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4492_ (.A(_1649_),
+    .B(_1635_),
+    .X(_1952_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4493_ (.A1_N(_1650_),
+    .A2_N(_1941_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[7] ),
+    .B2(_1952_),
+    .X(_1953_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4494_ (.A1(_1644_),
+    .A2(_1951_),
+    .B1(_1953_),
+    .X(_0391_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4495_ (.A(_1650_),
+    .X(_1954_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4496_ (.A(_1000_),
+    .B(_1612_),
+    .Y(_1955_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4497_ (.A(_1638_),
+    .X(_1956_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4498_ (.A1(\u_uart_core.u_clk_ctl.low_count[6] ),
+    .A2(_1634_),
+    .B1_N(_1635_),
+    .X(_1957_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4499_ (.A1(_1613_),
+    .A2(_1955_),
+    .A3(_1653_),
+    .B1(_1956_),
+    .B2(_1957_),
+    .X(_1958_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4500_ (.A(_1958_),
+    .Y(_1959_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4501_ (.A1_N(_1954_),
+    .A2_N(_1959_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[6] ),
+    .B2(_1954_),
+    .X(_0390_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4502_ (.A(_1041_),
+    .B(_1611_),
+    .Y(_1960_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4503_ (.A1(\u_uart_core.u_clk_ctl.low_count[5] ),
+    .A2(_1633_),
+    .B1_N(_1634_),
+    .X(_1961_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4504_ (.A1(_1612_),
+    .A2(_1960_),
+    .A3(_1653_),
+    .B1(_1956_),
+    .B2(_1961_),
+    .X(_1962_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4505_ (.A(_1962_),
+    .Y(_1963_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4506_ (.A1_N(_1954_),
+    .A2_N(_1963_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[5] ),
+    .B2(_1954_),
+    .X(_0389_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4507_ (.A(_1650_),
+    .X(_1964_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4508_ (.A(_1039_),
+    .B(_1610_),
+    .Y(_1965_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4509_ (.A1(\u_uart_core.u_clk_ctl.low_count[4] ),
+    .A2(_1632_),
+    .B1_N(_1633_),
+    .X(_1966_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4510_ (.A1(_1611_),
+    .A2(_1965_),
+    .A3(_1653_),
+    .B1(_1956_),
+    .B2(_1966_),
+    .X(_1967_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4511_ (.A(_1967_),
+    .Y(_1968_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4512_ (.A1_N(_1964_),
+    .A2_N(_1968_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[4] ),
+    .B2(_1964_),
+    .X(_0388_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4513_ (.A(_1609_),
+    .Y(_1969_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4514_ (.A1(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[4].u_bit_reg.data_out ),
+    .A2(_1969_),
+    .B1(_1610_),
+    .X(_1970_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4515_ (.A(_1632_),
+    .Y(_1971_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4516_ (.A(\u_uart_core.u_clk_ctl.low_count[3] ),
+    .B(_1631_),
+    .X(_1972_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4517_ (.A1(_1949_),
+    .A2(_1970_),
+    .B1(_1971_),
+    .B2(_1972_),
+    .X(_1973_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4518_ (.A1(_1675_),
+    .A2(_1973_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[3] ),
+    .B2(_1658_),
+    .X(_0387_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4519_ (.A(_1033_),
+    .B(_1608_),
+    .Y(_1974_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4520_ (.A(\u_uart_core.u_clk_ctl.low_count[2] ),
+    .Y(_1975_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4521_ (.A(\u_uart_core.u_clk_ctl.low_count[0] ),
+    .X(_1976_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4522_ (.A(\u_uart_core.u_clk_ctl.low_count[1] ),
+    .B(_1976_),
+    .Y(_1977_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21ai_4 _4523_ (.A1(_1975_),
+    .A2(_1977_),
+    .B1(_1631_),
+    .Y(_1978_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4524_ (.A1(_1609_),
+    .A2(_1974_),
+    .A3(_1652_),
+    .B1(_1956_),
+    .B2(_1978_),
+    .X(_1979_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4525_ (.A(_1979_),
+    .Y(_1980_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4526_ (.A1_N(_1964_),
+    .A2_N(_1980_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[2] ),
+    .B2(_1964_),
+    .X(_0386_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4527_ (.A(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[1].u_bit_reg.data_out ),
+    .B(\u_uart_core.u_cfg.u_uart_ctrl_reg2.gen_bit_reg[2].u_bit_reg.data_out ),
+    .X(_1981_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4528_ (.A1(\u_uart_core.u_clk_ctl.low_count[1] ),
+    .A2(_1976_),
+    .B1(_1977_),
+    .X(_1982_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4529_ (.A1(_1608_),
+    .A2(_1981_),
+    .A3(_1652_),
+    .B1(_1639_),
+    .B2(_1982_),
+    .X(_1983_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4530_ (.A(_1983_),
+    .Y(_1984_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4531_ (.A1_N(_1651_),
+    .A2_N(_1984_),
+    .B1(\u_uart_core.u_clk_ctl.low_count[1] ),
+    .B2(_1651_),
+    .X(_0385_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4532_ (.A(_1976_),
+    .Y(_1985_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4533_ (.A(_1030_),
+    .B(_1949_),
+    .X(_1986_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4534_ (.A1(_1985_),
+    .A2(_1986_),
+    .A3(_1658_),
+    .B1(_1976_),
+    .B2(_1680_),
+    .X(_0384_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4535_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.sda_chk ),
+    .A2(_1853_),
+    .B1_N(_1848_),
+    .X(_0383_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4536_ (.A(\u_i2cm.sda_padoen_o ),
+    .Y(_1987_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4537_ (.A(_1763_),
+    .B(_1862_),
+    .Y(_1988_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4538_ (.A(_1825_),
+    .B(_1775_),
+    .C(_1790_),
+    .D(_1858_),
+    .X(_1989_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4539_ (.A(_0565_),
+    .B(_1817_),
+    .C(_1856_),
+    .D(_1788_),
+    .X(_1990_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4540_ (.A1(\u_i2cm.u_byte_ctrl.core_txd ),
+    .A2(_1989_),
+    .B1(_1834_),
+    .C1(_1990_),
+    .X(_1991_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4541_ (.A1_N(_1987_),
+    .A2_N(_1988_),
+    .B1(_1988_),
+    .B2(_1991_),
+    .X(_0382_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4542_ (.A(\u_i2cm.scl_padoen_o ),
+    .Y(_1992_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4543_ (.A(_0566_),
+    .X(_1993_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4544_ (.A(_1782_),
+    .B(_1811_),
+    .X(_1994_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4545_ (.A(_1831_),
+    .B(_1858_),
+    .C(_1826_),
+    .D(_1994_),
+    .X(_1995_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4546_ (.A(_0581_),
+    .B(_0565_),
+    .C(_1806_),
+    .D(_1995_),
+    .X(_1996_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4547_ (.A1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.clk_en ),
+    .A2(_1993_),
+    .B1(_1860_),
+    .B2(_1996_),
+    .X(_1997_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4548_ (.A(_1874_),
+    .B(_1995_),
+    .Y(_1998_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4549_ (.A1_N(_1992_),
+    .A2_N(_1997_),
+    .B1(_1997_),
+    .B2(_1998_),
+    .X(_0381_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4550_ (.A(\u_i2cm.u_byte_ctrl.ld ),
+    .X(_1999_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4551_ (.A(_1999_),
+    .X(_2000_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4552_ (.A(\u_i2cm.u_byte_ctrl.shift ),
+    .X(_2001_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4553_ (.A(\u_i2cm.u_byte_ctrl.shift ),
+    .Y(_2002_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4554_ (.A(_2002_),
+    .X(_2003_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4555_ (.A(_2003_),
+    .X(_2004_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4556_ (.A1(\u_i2cm.rxr[7] ),
+    .A2(_2001_),
+    .B1(\u_i2cm.rxr[6] ),
+    .B2(_2004_),
+    .X(_2005_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4557_ (.A(\u_i2cm.u_byte_ctrl.ld ),
+    .Y(_2006_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4558_ (.A(_2006_),
+    .X(_2007_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4559_ (.A1(_2000_),
+    .A2(_2005_),
+    .B1(\u_i2cm.txr[7] ),
+    .B2(_2007_),
+    .X(_0380_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4560_ (.A(\u_i2cm.u_byte_ctrl.ld ),
+    .X(_2008_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4561_ (.A1(\u_i2cm.rxr[6] ),
+    .A2(_2001_),
+    .B1(\u_i2cm.rxr[5] ),
+    .B2(_2004_),
+    .X(_2009_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4562_ (.A1(_2008_),
+    .A2(_2009_),
+    .B1(\u_i2cm.txr[6] ),
+    .B2(_2007_),
+    .X(_0379_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4563_ (.A1(\u_i2cm.rxr[5] ),
+    .A2(_2001_),
+    .B1(\u_i2cm.rxr[4] ),
+    .B2(_2004_),
+    .X(_2010_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4564_ (.A1(_2008_),
+    .A2(_2010_),
+    .B1(\u_i2cm.txr[5] ),
+    .B2(_2007_),
+    .X(_0378_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4565_ (.A(\u_i2cm.u_byte_ctrl.shift ),
+    .X(_2011_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4566_ (.A(_2002_),
+    .X(_2012_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4567_ (.A1(\u_i2cm.rxr[4] ),
+    .A2(_2011_),
+    .B1(\u_i2cm.rxr[3] ),
+    .B2(_2012_),
+    .X(_2013_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4568_ (.A1(_2008_),
+    .A2(_2013_),
+    .B1(\u_i2cm.txr[4] ),
+    .B2(_2007_),
+    .X(_0377_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4569_ (.A1(\u_i2cm.rxr[3] ),
+    .A2(_2011_),
+    .B1(\u_i2cm.rxr[2] ),
+    .B2(_2012_),
+    .X(_2014_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4570_ (.A(_2006_),
+    .X(_2015_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4571_ (.A1(_2008_),
+    .A2(_2014_),
+    .B1(\u_i2cm.txr[3] ),
+    .B2(_2015_),
+    .X(_0376_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4572_ (.A1(\u_i2cm.rxr[2] ),
+    .A2(_2011_),
+    .B1(\u_i2cm.rxr[1] ),
+    .B2(_2012_),
+    .X(_2016_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4573_ (.A1(_1999_),
+    .A2(_2016_),
+    .B1(\u_i2cm.txr[2] ),
+    .B2(_2015_),
+    .X(_0375_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4574_ (.A1(\u_i2cm.rxr[1] ),
+    .A2(_2011_),
+    .B1(\u_i2cm.rxr[0] ),
+    .B2(_2012_),
+    .X(_2017_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4575_ (.A1(_1999_),
+    .A2(_2017_),
+    .B1(\u_i2cm.txr[1] ),
+    .B2(_2015_),
+    .X(_0374_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4576_ (.A1(\u_i2cm.rxr[0] ),
+    .A2(\u_i2cm.u_byte_ctrl.shift ),
+    .B1(\u_i2cm.u_byte_ctrl.core_rxd ),
+    .B2(_2003_),
+    .X(_2018_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4577_ (.A1(_1999_),
+    .A2(_2018_),
+    .B1(\u_i2cm.txr[0] ),
+    .B2(_2015_),
+    .X(_0373_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4578_ (.A(\u_i2cm.u_byte_ctrl.dcnt[0] ),
+    .X(_2019_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4579_ (.A(\u_i2cm.u_byte_ctrl.dcnt[1] ),
+    .B(_2019_),
+    .C(_2003_),
+    .X(_2020_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4580_ (.A(\u_i2cm.u_byte_ctrl.dcnt[2] ),
+    .B(_2020_),
+    .Y(_2021_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4581_ (.A1(\u_i2cm.u_byte_ctrl.dcnt[2] ),
+    .A2(_2020_),
+    .B1(_2000_),
+    .C1(_2021_),
+    .X(_0372_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4582_ (.A1(_2006_),
+    .A2(_2003_),
+    .B1(_2019_),
+    .X(_2022_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4583_ (.A(_2020_),
+    .Y(_2023_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4584_ (.A1(\u_i2cm.u_byte_ctrl.dcnt[1] ),
+    .A2(_2022_),
+    .B1(_2000_),
+    .C1(_2023_),
+    .X(_0371_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4585_ (.A(_2019_),
+    .Y(_2024_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4586_ (.A1(_2019_),
+    .A2(_2001_),
+    .B1(_2024_),
+    .B2(_2004_),
+    .X(_2025_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4587_ (.A(_2000_),
+    .B(_2025_),
+    .X(_0370_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4588_ (.A(_1874_),
+    .X(_2026_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4589_ (.A(\u_i2cm.u_byte_ctrl.c_state[2] ),
+    .Y(_2027_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4590_ (.A(\u_i2cm.u_byte_ctrl.core_ack ),
+    .Y(_2028_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4591_ (.A(_2028_),
+    .X(_2029_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4592_ (.A(_2029_),
+    .X(_2030_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4593_ (.A(_2027_),
+    .B(_2030_),
+    .X(_2031_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4594_ (.A(\u_i2cm.u_byte_ctrl.core_rxd ),
+    .B(_2031_),
+    .X(_2032_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4595_ (.A(_2031_),
+    .Y(_2033_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4596_ (.A(\u_i2cm.irxack ),
+    .B(_2033_),
+    .X(_2034_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4597_ (.A(_2026_),
+    .B(_2032_),
+    .C(_2034_),
+    .X(_0369_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4598_ (.A(\u_i2cm.txr[7] ),
+    .Y(_2035_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4599_ (.A(_0554_),
+    .B(_1013_),
+    .Y(_2036_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4600_ (.A(_2036_),
+    .X(_2037_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4601_ (.A(_0569_),
+    .X(_2038_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4602_ (.A1_N(_2035_),
+    .A2_N(_2037_),
+    .B1(_2038_),
+    .B2(_2037_),
+    .X(_0368_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4603_ (.A(\u_i2cm.txr[6] ),
+    .Y(_2039_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4604_ (.A(_0573_),
+    .X(_2040_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4605_ (.A1_N(_2039_),
+    .A2_N(_2037_),
+    .B1(_2040_),
+    .B2(_2037_),
+    .X(_0367_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4606_ (.A(\u_i2cm.txr[5] ),
+    .Y(_2041_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4607_ (.A(_2036_),
+    .X(_2042_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4608_ (.A(_0576_),
+    .X(_2043_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4609_ (.A1_N(_2041_),
+    .A2_N(_2042_),
+    .B1(_2043_),
+    .B2(_2042_),
+    .X(_0366_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4610_ (.A(\u_i2cm.txr[4] ),
+    .Y(_2044_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4611_ (.A1_N(_2044_),
+    .A2_N(_2042_),
+    .B1(_1531_),
+    .B2(_2042_),
+    .X(_0365_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4612_ (.A(\u_i2cm.txr[3] ),
+    .Y(_2045_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4613_ (.A(_2036_),
+    .X(_2046_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4614_ (.A1_N(_2045_),
+    .A2_N(_2046_),
+    .B1(_1540_),
+    .B2(_2046_),
+    .X(_0364_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4615_ (.A(\u_i2cm.txr[2] ),
+    .Y(_2047_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4616_ (.A1_N(_2047_),
+    .A2_N(_2046_),
+    .B1(_1535_),
+    .B2(_2046_),
+    .X(_0363_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4617_ (.A(\u_i2cm.txr[1] ),
+    .Y(_2048_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4618_ (.A(_2036_),
+    .X(_2049_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4619_ (.A1_N(_2048_),
+    .A2_N(_2049_),
+    .B1(_1517_),
+    .B2(_2049_),
+    .X(_0362_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4620_ (.A(\u_i2cm.txr[0] ),
+    .Y(_2050_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4621_ (.A1_N(_2050_),
+    .A2_N(_2049_),
+    .B1(_1519_),
+    .B2(_2049_),
+    .X(_0361_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4622_ (.A(_1699_),
+    .X(_2051_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4623_ (.A(_2051_),
+    .X(_2052_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4624_ (.A(_2052_),
+    .X(_2053_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4625_ (.A(_0554_),
+    .B(_1003_),
+    .Y(_2054_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4626_ (.A(_2054_),
+    .X(_2055_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4627_ (.A1_N(_2053_),
+    .A2_N(_2055_),
+    .B1(_2038_),
+    .B2(_2055_),
+    .X(_0360_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4628_ (.A(\u_i2cm.ctr[6] ),
+    .Y(_2056_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4629_ (.A1_N(_2056_),
+    .A2_N(_2055_),
+    .B1(_2040_),
+    .B2(_2055_),
+    .X(_0359_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4630_ (.A(\u_i2cm.ctr[5] ),
+    .Y(_2057_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4631_ (.A(_2054_),
+    .X(_2058_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4632_ (.A1_N(_2057_),
+    .A2_N(_2058_),
+    .B1(_2043_),
+    .B2(_2058_),
+    .X(_0358_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4633_ (.A(\u_i2cm.ctr[4] ),
+    .Y(_2059_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4634_ (.A1_N(_2059_),
+    .A2_N(_2058_),
+    .B1(_1531_),
+    .B2(_2058_),
+    .X(_0357_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4635_ (.A(\u_i2cm.ctr[3] ),
+    .Y(_2060_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4636_ (.A(_2054_),
+    .X(_2061_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4637_ (.A1_N(_2060_),
+    .A2_N(_2061_),
+    .B1(_1540_),
+    .B2(_2061_),
+    .X(_0356_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4638_ (.A(\u_i2cm.ctr[2] ),
+    .Y(_2062_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4639_ (.A1_N(_2062_),
+    .A2_N(_2061_),
+    .B1(_1535_),
+    .B2(_2061_),
+    .X(_0355_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4640_ (.A(\u_i2cm.ctr[1] ),
+    .Y(_2063_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4641_ (.A(_2054_),
+    .X(_2064_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4642_ (.A1_N(_2063_),
+    .A2_N(_2064_),
+    .B1(_1517_),
+    .B2(_2064_),
+    .X(_0354_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4643_ (.A(\u_i2cm.ctr[0] ),
+    .Y(_2065_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4644_ (.A1_N(_2065_),
+    .A2_N(_2064_),
+    .B1(_1519_),
+    .B2(_2064_),
+    .X(_0353_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4645_ (.A(\u_uart_core.u_txfifo.wr_ptr[3] ),
+    .Y(_2066_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4646_ (.A(_2066_),
+    .X(_2067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4647_ (.A(_1298_),
+    .X(_2068_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4648_ (.A(\u_uart_core.app_tx_fifo_full ),
+    .B(_1600_),
+    .C(reg_addr[3]),
+    .X(_2069_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4649_ (.A(reg_addr[1]),
+    .B(_0542_),
+    .C(_1046_),
+    .X(_2070_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4650_ (.A(_0551_),
+    .B(_1004_),
+    .C(_2069_),
+    .D(_2070_),
+    .X(_2071_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4651_ (.A(_2071_),
+    .X(_2072_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4652_ (.A(_1312_),
+    .B(_1331_),
+    .C(_2068_),
+    .D(psn_net_112),
+    .X(_2073_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4653_ (.A(_2067_),
+    .B(_2073_),
+    .X(_2074_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4654_ (.A(_2074_),
+    .Y(_2075_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4655_ (.A(_2075_),
+    .X(_2076_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4656_ (.A1(\u_uart_core.u_txfifo.grey_wr_ptr[4] ),
+    .A2(psn_net_99),
+    .B1(_1327_),
+    .B2(psn_net_101),
+    .X(_0352_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4657_ (.A(psn_net_105),
+    .X(_2077_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4658_ (.A(psn_net_142),
+    .Y(_2078_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4659_ (.A(_2078_),
+    .X(_2079_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4660_ (.A(psn_net_181),
+    .X(_2080_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4661_ (.A(_2068_),
+    .X(_2081_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4662_ (.A(_1312_),
+    .B(_1331_),
+    .X(_2082_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4663_ (.A(_2066_),
+    .X(_2083_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4664_ (.A1(_2081_),
+    .A2(_2082_),
+    .B1(_2083_),
+    .X(_2084_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4665_ (.A(_1327_),
+    .B(_2084_),
+    .Y(_2085_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4666_ (.A(_1327_),
+    .B(_2084_),
+    .X(_2086_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4667_ (.A(psn_net_104),
+    .X(_2087_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4668_ (.A1(_2080_),
+    .A2(_2085_),
+    .A3(_2086_),
+    .B1(\u_uart_core.u_txfifo.grey_wr_ptr[3] ),
+    .B2(psn_net_146),
+    .X(_0351_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4669_ (.A(_2082_),
+    .Y(_2088_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4670_ (.A(_2088_),
+    .X(_2089_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4671_ (.A(\u_uart_core.u_txfifo.wr_ptr[3] ),
+    .X(_2090_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4672_ (.A(_2090_),
+    .B(\u_uart_core.u_txfifo.wr_ptr[2] ),
+    .X(_2091_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4673_ (.A(_2089_),
+    .B(_2091_),
+    .X(_2092_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4674_ (.A1(_2081_),
+    .A2(_2082_),
+    .B1(_2083_),
+    .X(_2093_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4675_ (.A1(_2092_),
+    .A2(_2093_),
+    .A3(_2080_),
+    .B1(\u_uart_core.u_txfifo.grey_wr_ptr[2] ),
+    .B2(psn_net_146),
+    .X(_0350_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4676_ (.A(psn_net_145),
+    .X(_2094_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4677_ (.A(\u_uart_core.u_txfifo.wr_ptr[2] ),
+    .X(_2095_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4678_ (.A(_2095_),
+    .X(_2096_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4679_ (.A(\u_uart_core.u_txfifo.wr_ptr[1] ),
+    .B(\u_uart_core.u_txfifo.wr_ptr[0] ),
+    .X(_2097_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4680_ (.A1_N(_2096_),
+    .A2_N(_2097_),
+    .B1(_2096_),
+    .B2(_2097_),
+    .X(_2098_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4681_ (.A1_N(_2094_),
+    .A2_N(_2098_),
+    .B1(\u_uart_core.u_txfifo.grey_wr_ptr[1] ),
+    .B2(_2094_),
+    .X(_0349_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4682_ (.A(\u_uart_core.u_txfifo.wr_ptr[1] ),
+    .X(_2099_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4683_ (.A(_2099_),
+    .X(_2100_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4684_ (.A1_N(_2100_),
+    .A2_N(_2094_),
+    .B1(\u_uart_core.u_txfifo.grey_wr_ptr[0] ),
+    .B2(_2094_),
+    .X(_0348_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _4685_ (.A(_2078_),
+    .B(_2067_),
+    .C(_2095_),
+    .D(_2088_),
+    .X(_2101_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4686_ (.A(_2101_),
+    .X(_2102_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4687_ (.A(_2102_),
+    .X(_2103_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4688_ (.A1(psn_net_102),
+    .A2(_2090_),
+    .B1(_2103_),
+    .X(_0347_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4689_ (.A(psn_net_182),
+    .B(_2089_),
+    .X(_2104_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4690_ (.A1(_2096_),
+    .A2(_2104_),
+    .B1(psn_net_103),
+    .X(_0346_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4691_ (.A(_1331_),
+    .X(_2105_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4692_ (.A(_2105_),
+    .B(psn_net_124),
+    .X(_2106_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4693_ (.A1_N(_2100_),
+    .A2_N(psn_net_123),
+    .B1(_2100_),
+    .B2(psn_net_123),
+    .X(_0345_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4694_ (.A(\u_uart_core.u_txfifo.wr_ptr[0] ),
+    .X(_2107_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4695_ (.A1(_2107_),
+    .A2(_2080_),
+    .B1(psn_net_123),
+    .X(_0344_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4696_ (.A(_0729_),
+    .X(_2108_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4697_ (.A(_0708_),
+    .X(_2109_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4698_ (.A(\u_uart_core.tx_fifo_rd ),
+    .B(_0715_),
+    .X(_2110_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4699_ (.A(_0720_),
+    .B(_2110_),
+    .X(_2111_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4700_ (.A(_2111_),
+    .Y(_2112_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4701_ (.A(_2109_),
+    .B(_2112_),
+    .X(_2113_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4702_ (.A(_2108_),
+    .B(_2113_),
+    .X(_2114_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4703_ (.A1_N(\u_uart_core.u_txfifo.grey_rd_ptr[4] ),
+    .A2_N(_2114_),
+    .B1(\u_uart_core.u_txfifo.grey_rd_ptr[4] ),
+    .B2(_2114_),
+    .X(_0343_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4704_ (.A(_2113_),
+    .Y(_2115_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4705_ (.A1(_0662_),
+    .A2(_2115_),
+    .B1(_2114_),
+    .X(_0342_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4706_ (.A1(_0684_),
+    .A2(_2111_),
+    .B1(_2113_),
+    .X(_0341_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4707_ (.A1(_0720_),
+    .A2(_2110_),
+    .B1(_2112_),
+    .X(_0340_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4708_ (.A(_0651_),
+    .Y(_2116_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4709_ (.A(_2116_),
+    .X(_2117_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21oi_4 _4710_ (.A1(_2117_),
+    .A2(_0712_),
+    .B1(_2110_),
+    .Y(_0339_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4711_ (.A(\u_uart_core.u_txfifo.grey_rd_ptr[4] ),
+    .Y(_2118_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4712_ (.A(_0711_),
+    .B(_0712_),
+    .X(_2119_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4713_ (.A1(_2109_),
+    .A2(_2119_),
+    .B1(_2108_),
+    .X(_2120_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4714_ (.A(_2118_),
+    .B(_2120_),
+    .X(_2121_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4715_ (.A(_2118_),
+    .B(_2120_),
+    .Y(_2122_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4716_ (.A1(_0652_),
+    .A2(_2121_),
+    .A3(_2122_),
+    .B1(_2117_),
+    .B2(\u_uart_core.u_txfifo.grey_rd_ptr[3] ),
+    .X(_0338_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4717_ (.A(_2109_),
+    .B(_2119_),
+    .X(_2123_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4718_ (.A(_2108_),
+    .B(_2123_),
+    .X(_2124_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4719_ (.A(_2108_),
+    .B(_2123_),
+    .Y(_2125_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4720_ (.A1(_0651_),
+    .A2(_2124_),
+    .A3(_2125_),
+    .B1(_2117_),
+    .B2(\u_uart_core.u_txfifo.grey_rd_ptr[2] ),
+    .X(_0337_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4721_ (.A1(_0711_),
+    .A2(_0712_),
+    .B1(_2109_),
+    .X(_2126_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4722_ (.A(_0720_),
+    .B(_0715_),
+    .C(_0684_),
+    .X(_2127_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4723_ (.A1(_0651_),
+    .A2(_2126_),
+    .A3(_2127_),
+    .B1(_2116_),
+    .B2(\u_uart_core.u_txfifo.grey_rd_ptr[1] ),
+    .X(_0336_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4724_ (.A1(_2117_),
+    .A2(_0711_),
+    .B1(_0652_),
+    .B2(\u_uart_core.u_txfifo.grey_rd_ptr[0] ),
+    .X(_0335_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4725_ (.A(\u_uart_core.u_rxfsm.cnt[1] ),
+    .X(_2128_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4726_ (.A(\u_uart_core.u_rxfsm.cnt[0] ),
+    .X(_2129_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4727_ (.A(_2129_),
+    .X(_2130_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4728_ (.A(_1583_),
+    .B(_1555_),
+    .X(_2131_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4729_ (.A(\u_uart_core.si_ss ),
+    .B(_1549_),
+    .C(_1555_),
+    .X(_2132_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4730_ (.A1(_1583_),
+    .A2(_1579_),
+    .B1(_1562_),
+    .C1(_2132_),
+    .X(_2133_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4731_ (.A(_2133_),
+    .Y(_2134_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4732_ (.A1(_1597_),
+    .A2(_2131_),
+    .B1(_2134_),
+    .X(_2135_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4733_ (.A(_2128_),
+    .B(_2130_),
+    .C(_2135_),
+    .X(_2136_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4734_ (.A(_2135_),
+    .Y(_2137_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4735_ (.A(_1550_),
+    .B(_2131_),
+    .X(_2138_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4736_ (.A1(\u_uart_core.u_rxfsm.cnt[2] ),
+    .A2(_2136_),
+    .B1(_2137_),
+    .B2(_2138_),
+    .X(_0334_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4737_ (.A(_1546_),
+    .X(_2139_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4738_ (.A1_N(_2139_),
+    .A2_N(_2130_),
+    .B1(_2139_),
+    .B2(_2130_),
+    .X(_2140_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a32o_4 _4739_ (.A1(_2131_),
+    .A2(_2140_),
+    .A3(_2134_),
+    .B1(_2128_),
+    .B2(_2137_),
+    .X(_0333_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4740_ (.A(_1547_),
+    .X(_2141_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4741_ (.A(_2141_),
+    .B(_1559_),
+    .X(_2142_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4742_ (.A1(_2137_),
+    .A2(_2142_),
+    .B1(_2130_),
+    .B2(_2135_),
+    .X(_0332_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4743_ (.A(_1582_),
+    .B(_1579_),
+    .X(_2143_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4744_ (.A(_2143_),
+    .X(_2144_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4745_ (.A(_1550_),
+    .B(_2144_),
+    .X(_2145_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4746_ (.A(_1567_),
+    .X(_2146_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4747_ (.A(_1563_),
+    .B(_1560_),
+    .X(_2147_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4748_ (.A1(_1898_),
+    .A2(_2145_),
+    .B1(_2146_),
+    .C1(_2147_),
+    .X(_2148_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4749_ (.A(_2148_),
+    .Y(_0331_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4750_ (.A(\u_uart_core.rx_fifo_wr_data[7] ),
+    .X(_2149_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4751_ (.A(_2145_),
+    .Y(_2150_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4752_ (.A1(_2149_),
+    .A2(_2150_),
+    .B1(_1545_),
+    .B2(_2145_),
+    .X(_0330_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4753_ (.A(\u_uart_core.rx_fifo_wr_data[6] ),
+    .X(_2151_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4754_ (.A(_2151_),
+    .X(_2152_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4755_ (.A(_1546_),
+    .B(\u_uart_core.u_rxfsm.cnt[0] ),
+    .C(_1548_),
+    .D(_2144_),
+    .X(_2153_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4756_ (.A(_1590_),
+    .X(_2154_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4757_ (.A(_2154_),
+    .B(_2153_),
+    .X(_2155_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4758_ (.A1(_2152_),
+    .A2(_2153_),
+    .B1_N(_2155_),
+    .X(_0329_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4759_ (.A(\u_uart_core.rx_fifo_wr_data[5] ),
+    .X(_2156_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4760_ (.A(_2156_),
+    .X(_2157_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4761_ (.A(\u_uart_core.u_rxfsm.cnt[1] ),
+    .B(_2141_),
+    .C(_1548_),
+    .D(_2144_),
+    .X(_2158_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4762_ (.A(_2154_),
+    .B(_2158_),
+    .X(_2159_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4763_ (.A1(_2157_),
+    .A2(_2158_),
+    .B1_N(_2159_),
+    .X(_0328_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4764_ (.A(\u_uart_core.rx_fifo_wr_data[4] ),
+    .X(_2160_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4765_ (.A(_2160_),
+    .X(_2161_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4766_ (.A(_1548_),
+    .B(_2144_),
+    .C(\u_uart_core.u_rxfsm.cnt[1] ),
+    .D(_2129_),
+    .X(_2162_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4767_ (.A(_1590_),
+    .X(_2163_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4768_ (.A(_2163_),
+    .B(_2162_),
+    .X(_2164_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4769_ (.A1(_2161_),
+    .A2(_2162_),
+    .B1_N(_2164_),
+    .X(_0327_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4770_ (.A(\u_uart_core.rx_fifo_wr_data[3] ),
+    .X(_2165_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4771_ (.A(_2165_),
+    .X(_2166_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4772_ (.A(\u_uart_core.u_rxfsm.cnt[2] ),
+    .B(_2143_),
+    .X(_2167_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4773_ (.A(_2139_),
+    .B(_2141_),
+    .C(_2167_),
+    .X(_2168_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4774_ (.A(_2163_),
+    .B(_2168_),
+    .X(_2169_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4775_ (.A1(_2166_),
+    .A2(_2168_),
+    .B1_N(_2169_),
+    .X(_0326_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4776_ (.A(\u_uart_core.rx_fifo_wr_data[2] ),
+    .X(_2170_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4777_ (.A(_2170_),
+    .X(_2171_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4778_ (.A(_2139_),
+    .B(_2129_),
+    .C(_2167_),
+    .X(_2172_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4779_ (.A(_2163_),
+    .B(_2172_),
+    .X(_2173_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4780_ (.A1(_2171_),
+    .A2(_2172_),
+    .B1_N(_2173_),
+    .X(_0325_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4781_ (.A(\u_uart_core.rx_fifo_wr_data[1] ),
+    .X(_2174_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4782_ (.A(_2174_),
+    .X(_2175_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4783_ (.A(_2128_),
+    .B(_2141_),
+    .C(_2167_),
+    .X(_2176_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4784_ (.A(_2163_),
+    .B(_2176_),
+    .X(_2177_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4785_ (.A1(_2175_),
+    .A2(_2176_),
+    .B1_N(_2177_),
+    .X(_0324_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4786_ (.A(\u_uart_core.rx_fifo_wr_data[0] ),
+    .X(_2178_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4787_ (.A(_2178_),
+    .X(_2179_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4788_ (.A(_2128_),
+    .B(_2129_),
+    .C(_2167_),
+    .X(_2180_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4789_ (.A(_1590_),
+    .B(_2180_),
+    .X(_2181_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4790_ (.A1(_2179_),
+    .A2(_2180_),
+    .B1_N(_2181_),
+    .X(_0323_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4791_ (.A(\u_uart_core.u_rxfifo.sync_rd_ptr[4] ),
+    .Y(_2182_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4792_ (.A(\u_uart_core.u_rxfifo.sync_rd_ptr_1[3] ),
+    .Y(_2183_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4793_ (.A1(\u_uart_core.u_rxfifo.sync_rd_ptr[4] ),
+    .A2(\u_uart_core.u_rxfifo.sync_rd_ptr_1[3] ),
+    .B1(_2182_),
+    .B2(_2183_),
+    .X(_2184_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4794_ (.A(_2184_),
+    .Y(_2185_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4795_ (.A1(_1885_),
+    .A2(_2184_),
+    .B1(\u_uart_core.u_rxfifo.wr_ptr[3] ),
+    .B2(_2185_),
+    .X(_2186_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4796_ (.A1_N(_2183_),
+    .A2_N(\u_uart_core.u_rxfifo.sync_rd_ptr_1[2] ),
+    .B1(_2183_),
+    .B2(\u_uart_core.u_rxfifo.sync_rd_ptr_1[2] ),
+    .X(_2187_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4797_ (.A1_N(_2182_),
+    .A2_N(_2187_),
+    .B1(_2182_),
+    .B2(_2187_),
+    .X(_2188_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4798_ (.A(_1875_),
+    .B(_2188_),
+    .Y(_2189_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4799_ (.A(_2186_),
+    .B(_2189_),
+    .X(_2190_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4800_ (.A1(_1875_),
+    .A2(_2188_),
+    .B1(_2189_),
+    .X(_2191_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4801_ (.A(\u_uart_core.u_rxfifo.sync_rd_ptr_1[1] ),
+    .Y(_2192_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4802_ (.A1_N(_2192_),
+    .A2_N(_2188_),
+    .B1(_2192_),
+    .B2(_2188_),
+    .X(_2193_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4803_ (.A(_2193_),
+    .X(_2194_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4804_ (.A1_N(\u_uart_core.u_rxfifo.sync_rd_ptr_1[0] ),
+    .A2_N(_2194_),
+    .B1(\u_uart_core.u_rxfifo.sync_rd_ptr_1[0] ),
+    .B2(_2193_),
+    .X(_2195_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4805_ (.A(_2195_),
+    .Y(_2196_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4806_ (.A1_N(_1877_),
+    .A2_N(_2194_),
+    .B1(_1877_),
+    .B2(_2194_),
+    .X(_2197_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21o_4 _4807_ (.A1(_1879_),
+    .A2(_2196_),
+    .B1(_2197_),
+    .X(_2198_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4808_ (.A1(_1878_),
+    .A2(_2194_),
+    .B1(_2198_),
+    .X(_2199_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4809_ (.A(_2191_),
+    .B(_2199_),
+    .Y(_2200_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4810_ (.A(_2186_),
+    .B(_2200_),
+    .X(_2201_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4811_ (.A1(_1902_),
+    .A2(_2185_),
+    .B1(_2190_),
+    .C1(_2201_),
+    .X(_2202_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4812_ (.A1_N(_1891_),
+    .A2_N(\u_uart_core.u_rxfifo.sync_rd_ptr[4] ),
+    .B1(_1890_),
+    .B2(\u_uart_core.u_rxfifo.sync_rd_ptr[4] ),
+    .X(_2203_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4813_ (.A1_N(_2202_),
+    .A2_N(_2203_),
+    .B1(_2202_),
+    .B2(_2203_),
+    .X(_2204_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4814_ (.A(_2186_),
+    .B(_2189_),
+    .Y(_2205_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4815_ (.A(_2198_),
+    .Y(_2206_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4816_ (.A1(_1880_),
+    .A2(_2196_),
+    .B1(_2197_),
+    .X(_2207_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4817_ (.A(_2190_),
+    .B(_2205_),
+    .C(_2206_),
+    .D(_2207_),
+    .X(_2208_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4818_ (.A(_2191_),
+    .B(_2199_),
+    .X(_2209_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4819_ (.A(_2200_),
+    .B(_2208_),
+    .C(_2209_),
+    .D(_2204_),
+    .X(_2210_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4820_ (.A(_2210_),
+    .Y(_2211_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4821_ (.A1(_1893_),
+    .A2(_2204_),
+    .B1(\u_uart_core.rx_fifo_wr_full ),
+    .B2(_2211_),
+    .X(_0322_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4822_ (.A(\u_uart_core.u_txfifo.sync_wr_ptr[4] ),
+    .Y(_2212_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4823_ (.A1_N(\u_uart_core.u_txfifo.sync_wr_ptr_1[2] ),
+    .A2_N(\u_uart_core.u_txfifo.sync_wr_ptr_1[3] ),
+    .B1(\u_uart_core.u_txfifo.sync_wr_ptr_1[2] ),
+    .B2(\u_uart_core.u_txfifo.sync_wr_ptr_1[3] ),
+    .X(_2213_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4824_ (.A(\u_uart_core.u_txfifo.sync_wr_ptr[4] ),
+    .X(_2214_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4825_ (.A(_2213_),
+    .Y(_2215_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4826_ (.A1(_2212_),
+    .A2(_2213_),
+    .B1(_2214_),
+    .B2(_2215_),
+    .X(_2216_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4827_ (.A1_N(\u_uart_core.u_txfifo.sync_wr_ptr_1[1] ),
+    .A2_N(_2216_),
+    .B1(\u_uart_core.u_txfifo.sync_wr_ptr_1[1] ),
+    .B2(_2216_),
+    .X(_2217_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4828_ (.A(_2217_),
+    .Y(_2218_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4829_ (.A1_N(\u_uart_core.u_txfifo.sync_wr_ptr_1[0] ),
+    .A2_N(_2218_),
+    .B1(\u_uart_core.u_txfifo.sync_wr_ptr_1[0] ),
+    .B2(_2218_),
+    .X(_2219_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nand2_4 _4830_ (.A(_0904_),
+    .B(_2219_),
+    .Y(_2220_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4831_ (.A1(_0715_),
+    .A2(_2219_),
+    .B1(_2220_),
+    .X(_2221_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and3_4 _4832_ (.A(_0719_),
+    .B(_2217_),
+    .C(_2220_),
+    .X(_2222_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4833_ (.A(_0706_),
+    .B(_2216_),
+    .X(_2223_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a21bo_4 _4834_ (.A1(_0707_),
+    .A2(_2216_),
+    .B1_N(_2223_),
+    .X(_2224_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4835_ (.A(_0686_),
+    .B(_2218_),
+    .X(_2225_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4836_ (.A(\u_uart_core.u_txfifo.sync_wr_ptr_1[3] ),
+    .Y(_2226_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4837_ (.A1(\u_uart_core.u_txfifo.sync_wr_ptr_1[3] ),
+    .A2(_2214_),
+    .B1(_2226_),
+    .B2(_2212_),
+    .X(_2227_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4838_ (.A(_0728_),
+    .B(_2227_),
+    .C(_0707_),
+    .X(_2228_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4839_ (.A1_N(_2118_),
+    .A2_N(_2214_),
+    .B1(_2118_),
+    .B2(_2214_),
+    .X(_2229_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4840_ (.A1_N(_2228_),
+    .A2_N(_2229_),
+    .B1(_2228_),
+    .B2(_2229_),
+    .X(_2230_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4841_ (.A1_N(_0729_),
+    .A2_N(_2227_),
+    .B1(_0728_),
+    .B2(_2227_),
+    .X(_2231_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4842_ (.A1_N(_2223_),
+    .A2_N(_2231_),
+    .B1(_2223_),
+    .B2(_2231_),
+    .X(_2232_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a211o_4 _4843_ (.A1(_2224_),
+    .A2(_2225_),
+    .B1(_2230_),
+    .C1(_2232_),
+    .X(_2233_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4844_ (.A(_2220_),
+    .B(_2224_),
+    .Y(_2234_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o21a_4 _4845_ (.A1(_0918_),
+    .A2(_2217_),
+    .B1(_2234_),
+    .X(_2235_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4846_ (.A(_0719_),
+    .B(_2217_),
+    .C(_2234_),
+    .X(_2236_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4847_ (.A(_2236_),
+    .Y(_2237_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4848_ (.A(_2222_),
+    .B(_2233_),
+    .C(_2235_),
+    .D(_2237_),
+    .X(_2238_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__nor2_4 _4849_ (.A(_2221_),
+    .B(_2238_),
+    .Y(_2239_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4850_ (.A(_2238_),
+    .Y(_2240_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and2_4 _4851_ (.A(_2221_),
+    .B(_2240_),
+    .X(_2241_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4852_ (.A1(\u_uart_core.tx_fifo_rd_empty ),
+    .A2(_2239_),
+    .B1(_0652_),
+    .B2(_2241_),
+    .X(_0321_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4853_ (.A(_1336_),
+    .Y(_2242_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4854_ (.A(_1422_),
+    .B(_1458_),
+    .C(_1329_),
+    .D(_2242_),
+    .X(_2243_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4855_ (.A(_2243_),
+    .Y(_2244_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4856_ (.A1(_1329_),
+    .A2(_2080_),
+    .B1(\u_uart_core.app_tx_fifo_full ),
+    .B2(_2244_),
+    .X(_0320_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4857_ (.A(_1563_),
+    .B(_1559_),
+    .C(_1545_),
+    .D(_1558_),
+    .X(_2245_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4858_ (.A(_2245_),
+    .Y(_2246_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4859_ (.A(_2246_),
+    .X(_2247_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4860_ (.A1_N(_1568_),
+    .A2_N(_2247_),
+    .B1(_1569_),
+    .B2(_2247_),
+    .X(_0319_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4861_ (.A1_N(_1573_),
+    .A2_N(_2247_),
+    .B1(_1574_),
+    .B2(_2247_),
+    .X(_0318_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4862_ (.A(_2246_),
+    .X(_2248_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4863_ (.A1_N(_1576_),
+    .A2_N(_2248_),
+    .B1(\u_uart_core.u_rxfsm.offset[1] ),
+    .B2(_2248_),
+    .X(_0317_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4864_ (.A1_N(_1571_),
+    .A2_N(_2248_),
+    .B1(\u_uart_core.u_rxfsm.offset[0] ),
+    .B2(_2248_),
+    .X(_0316_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4865_ (.A(\u_uart_core.u_txfifo.mem[7][7] ),
+    .Y(_2249_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4866_ (.A1_N(_2249_),
+    .A2_N(_2103_),
+    .B1(_2038_),
+    .B2(_2103_),
+    .X(_0315_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4867_ (.A(\u_uart_core.u_txfifo.mem[7][6] ),
+    .Y(_2250_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4868_ (.A(_2102_),
+    .X(_2251_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4869_ (.A1_N(_2250_),
+    .A2_N(_2103_),
+    .B1(_2040_),
+    .B2(_2251_),
+    .X(_0314_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4870_ (.A(\u_uart_core.u_txfifo.mem[7][5] ),
+    .Y(_2252_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4871_ (.A1_N(_2252_),
+    .A2_N(_2251_),
+    .B1(_2043_),
+    .B2(_2251_),
+    .X(_0313_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4872_ (.A(\u_uart_core.u_txfifo.mem[7][4] ),
+    .Y(_2253_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4873_ (.A(_2102_),
+    .X(_2254_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4874_ (.A1_N(_2253_),
+    .A2_N(_2251_),
+    .B1(_1531_),
+    .B2(_2254_),
+    .X(_0312_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4875_ (.A(\u_uart_core.u_txfifo.mem[7][3] ),
+    .Y(_2255_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4876_ (.A(_1035_),
+    .X(_2256_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4877_ (.A1_N(_2255_),
+    .A2_N(_2254_),
+    .B1(_2256_),
+    .B2(_2254_),
+    .X(_0311_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4878_ (.A(\u_uart_core.u_txfifo.mem[7][2] ),
+    .Y(_2257_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4879_ (.A(psn_net_193),
+    .X(_2258_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4880_ (.A1_N(_2257_),
+    .A2_N(_2254_),
+    .B1(_1535_),
+    .B2(_2258_),
+    .X(_0310_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4881_ (.A(\u_uart_core.u_txfifo.mem[7][1] ),
+    .Y(_2259_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4882_ (.A(_0557_),
+    .X(_2260_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4883_ (.A1_N(_2259_),
+    .A2_N(_2258_),
+    .B1(_2260_),
+    .B2(_2258_),
+    .X(_0309_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4884_ (.A(\u_uart_core.u_txfifo.mem[7][0] ),
+    .Y(_2261_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4885_ (.A(_0562_),
+    .X(_2262_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4886_ (.A1_N(_2261_),
+    .A2_N(_2258_),
+    .B1(_2262_),
+    .B2(psn_net_192),
+    .X(_0308_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4887_ (.A(\u_uart_core.u_txfifo.mem[8][7] ),
+    .Y(_2263_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4888_ (.A(_2067_),
+    .B(_2095_),
+    .C(_2097_),
+    .D(_2087_),
+    .X(_2264_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4889_ (.A(_2264_),
+    .Y(_2265_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4890_ (.A(_2265_),
+    .X(_2266_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4891_ (.A1_N(_2263_),
+    .A2_N(_2266_),
+    .B1(_2038_),
+    .B2(_2266_),
+    .X(_0307_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4892_ (.A(\u_uart_core.u_txfifo.mem[8][6] ),
+    .Y(_2267_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4893_ (.A1_N(_2267_),
+    .A2_N(_2266_),
+    .B1(_2040_),
+    .B2(_2266_),
+    .X(_0306_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4894_ (.A(\u_uart_core.u_txfifo.mem[8][5] ),
+    .Y(_2268_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4895_ (.A(_2265_),
+    .X(_2269_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4896_ (.A1_N(_2268_),
+    .A2_N(_2269_),
+    .B1(_2043_),
+    .B2(_2269_),
+    .X(_0305_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4897_ (.A(\u_uart_core.u_txfifo.mem[8][4] ),
+    .Y(_2270_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4898_ (.A(_1530_),
+    .X(_2271_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4899_ (.A1_N(_2270_),
+    .A2_N(_2269_),
+    .B1(_2271_),
+    .B2(_2269_),
+    .X(_0304_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4900_ (.A(\u_uart_core.u_txfifo.mem[8][3] ),
+    .Y(_2272_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4901_ (.A(_2265_),
+    .X(_2273_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4902_ (.A1_N(_2272_),
+    .A2_N(_2273_),
+    .B1(_2256_),
+    .B2(_2273_),
+    .X(_0303_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4903_ (.A(\u_uart_core.u_txfifo.mem[8][2] ),
+    .Y(_2274_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4904_ (.A(_1019_),
+    .X(_2275_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4905_ (.A1_N(_2274_),
+    .A2_N(_2273_),
+    .B1(_2275_),
+    .B2(_2273_),
+    .X(_0302_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4906_ (.A(\u_uart_core.u_txfifo.mem[8][1] ),
+    .Y(_2276_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4907_ (.A(_2265_),
+    .X(_2277_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4908_ (.A1_N(_2276_),
+    .A2_N(_2277_),
+    .B1(_2260_),
+    .B2(_2277_),
+    .X(_0301_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4909_ (.A(\u_uart_core.u_txfifo.mem[8][0] ),
+    .Y(_2278_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4910_ (.A1_N(_2278_),
+    .A2_N(_2277_),
+    .B1(_2262_),
+    .B2(_2277_),
+    .X(_0300_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4911_ (.A(\u_uart_core.u_txfifo.mem[0][7] ),
+    .Y(_2279_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4912_ (.A(_2099_),
+    .X(_2280_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4913_ (.A(_2077_),
+    .X(_2281_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or4_4 _4914_ (.A(_2280_),
+    .B(_2091_),
+    .C(_2107_),
+    .D(psn_net_140),
+    .X(_2282_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4915_ (.A(_2282_),
+    .Y(_2283_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4916_ (.A(_2283_),
+    .X(_2284_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4917_ (.A(reg_wdata[7]),
+    .X(_2285_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4918_ (.A1_N(_2279_),
+    .A2_N(_2284_),
+    .B1(_2285_),
+    .B2(_2284_),
+    .X(_0299_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4919_ (.A(\u_uart_core.u_txfifo.mem[0][6] ),
+    .Y(_2286_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4920_ (.A(reg_wdata[6]),
+    .X(_2287_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4921_ (.A1_N(_2286_),
+    .A2_N(_2284_),
+    .B1(_2287_),
+    .B2(_2284_),
+    .X(_0298_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4922_ (.A(\u_uart_core.u_txfifo.mem[0][5] ),
+    .Y(_2288_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4923_ (.A(_2283_),
+    .X(_2289_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4924_ (.A(reg_wdata[5]),
+    .X(_2290_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4925_ (.A1_N(_2288_),
+    .A2_N(_2289_),
+    .B1(_2290_),
+    .B2(_2289_),
+    .X(_0297_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4926_ (.A(\u_uart_core.u_txfifo.mem[0][4] ),
+    .Y(_2291_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4927_ (.A1_N(_2291_),
+    .A2_N(_2289_),
+    .B1(_2271_),
+    .B2(_2289_),
+    .X(_0296_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4928_ (.A(\u_uart_core.u_txfifo.mem[0][3] ),
+    .Y(_2292_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4929_ (.A(_2283_),
+    .X(_2293_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4930_ (.A1_N(_2292_),
+    .A2_N(_2293_),
+    .B1(_2256_),
+    .B2(_2293_),
+    .X(_0295_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4931_ (.A(\u_uart_core.u_txfifo.mem[0][2] ),
+    .Y(_2294_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4932_ (.A1_N(_2294_),
+    .A2_N(_2293_),
+    .B1(_2275_),
+    .B2(_2293_),
+    .X(_0294_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4933_ (.A(\u_uart_core.u_txfifo.mem[0][1] ),
+    .Y(_2295_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4934_ (.A(_2283_),
+    .X(_2296_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4935_ (.A1_N(_2295_),
+    .A2_N(_2296_),
+    .B1(_2260_),
+    .B2(_2296_),
+    .X(_0293_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4936_ (.A(\u_uart_core.u_txfifo.mem[0][0] ),
+    .Y(_2297_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4937_ (.A1_N(_2297_),
+    .A2_N(_2296_),
+    .B1(_2262_),
+    .B2(_2296_),
+    .X(_0292_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4938_ (.A(\u_uart_core.u_txfifo.mem[10][7] ),
+    .Y(_2298_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4939_ (.A(_1312_),
+    .B(\u_uart_core.u_txfifo.wr_ptr[0] ),
+    .C(_2072_),
+    .X(_2299_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4940_ (.A(_2299_),
+    .X(_2300_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or3_4 _4941_ (.A(_2083_),
+    .B(_2096_),
+    .C(_2300_),
+    .X(_2301_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4942_ (.A(_2301_),
+    .Y(_2302_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4943_ (.A(_2302_),
+    .X(_2303_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4944_ (.A1_N(_2298_),
+    .A2_N(_2303_),
+    .B1(_2285_),
+    .B2(_2303_),
+    .X(_0291_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4945_ (.A(\u_uart_core.u_txfifo.mem[10][6] ),
+    .Y(_2304_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4946_ (.A1_N(_2304_),
+    .A2_N(_2303_),
+    .B1(_2287_),
+    .B2(_2303_),
+    .X(_0290_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4947_ (.A(\u_uart_core.u_txfifo.mem[10][5] ),
+    .Y(_2305_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4948_ (.A(_2302_),
+    .X(_2306_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4949_ (.A1_N(_2305_),
+    .A2_N(_2306_),
+    .B1(_2290_),
+    .B2(_2306_),
+    .X(_0289_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4950_ (.A(\u_uart_core.u_txfifo.mem[10][4] ),
+    .Y(_2307_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4951_ (.A1_N(_2307_),
+    .A2_N(_2306_),
+    .B1(_2271_),
+    .B2(_2306_),
+    .X(_0288_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4952_ (.A(\u_uart_core.u_txfifo.mem[10][3] ),
+    .Y(_2308_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4953_ (.A(_2302_),
+    .X(_2309_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4954_ (.A1_N(_2308_),
+    .A2_N(_2309_),
+    .B1(_2256_),
+    .B2(_2309_),
+    .X(_0287_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4955_ (.A(\u_uart_core.u_txfifo.mem[10][2] ),
+    .Y(_2310_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4956_ (.A1_N(_2310_),
+    .A2_N(_2309_),
+    .B1(_2275_),
+    .B2(_2309_),
+    .X(_0286_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4957_ (.A(\u_uart_core.u_txfifo.mem[10][1] ),
+    .Y(_2311_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4958_ (.A(_2302_),
+    .X(_2312_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4959_ (.A1_N(_2311_),
+    .A2_N(_2312_),
+    .B1(_2260_),
+    .B2(_2312_),
+    .X(_0285_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4960_ (.A(\u_uart_core.u_txfifo.mem[10][0] ),
+    .Y(_2313_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4961_ (.A1_N(_2313_),
+    .A2_N(_2312_),
+    .B1(_2262_),
+    .B2(_2312_),
+    .X(_0284_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4962_ (.A(\u_uart_core.u_txfifo.mem[11][7] ),
+    .Y(_2314_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__and4_4 _4963_ (.A(_2079_),
+    .B(_2090_),
+    .C(_2081_),
+    .D(_2089_),
+    .X(_2315_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4964_ (.A(_2315_),
+    .X(_2316_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4965_ (.A1_N(_2314_),
+    .A2_N(_2316_),
+    .B1(_2285_),
+    .B2(_2316_),
+    .X(_0283_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4966_ (.A(\u_uart_core.u_txfifo.mem[11][6] ),
+    .Y(_2317_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4967_ (.A1_N(_2317_),
+    .A2_N(_2316_),
+    .B1(_2287_),
+    .B2(_2316_),
+    .X(_0282_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4968_ (.A(\u_uart_core.u_txfifo.mem[11][5] ),
+    .Y(_2318_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4969_ (.A(_2315_),
+    .X(_2319_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4970_ (.A1_N(_2318_),
+    .A2_N(_2319_),
+    .B1(_2290_),
+    .B2(_2319_),
+    .X(_0281_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4971_ (.A(\u_uart_core.u_txfifo.mem[11][4] ),
+    .Y(_2320_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4972_ (.A1_N(_2320_),
+    .A2_N(_2319_),
+    .B1(_2271_),
+    .B2(_2319_),
+    .X(_0280_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4973_ (.A(\u_uart_core.u_txfifo.mem[11][3] ),
+    .Y(_2321_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4974_ (.A(_2315_),
+    .X(_2322_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4975_ (.A(_1035_),
+    .X(_2323_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4976_ (.A1_N(_2321_),
+    .A2_N(_2322_),
+    .B1(_2323_),
+    .B2(_2322_),
+    .X(_0279_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4977_ (.A(\u_uart_core.u_txfifo.mem[11][2] ),
+    .Y(_2324_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4978_ (.A1_N(_2324_),
+    .A2_N(_2322_),
+    .B1(_2275_),
+    .B2(_2322_),
+    .X(_0278_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4979_ (.A(\u_uart_core.u_txfifo.mem[11][1] ),
+    .Y(_2325_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4980_ (.A(_2315_),
+    .X(_2326_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4981_ (.A(_0557_),
+    .X(_2327_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4982_ (.A1_N(_2325_),
+    .A2_N(_2326_),
+    .B1(_2327_),
+    .B2(_2326_),
+    .X(_0277_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4983_ (.A(\u_uart_core.u_txfifo.mem[11][0] ),
+    .Y(_2328_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4984_ (.A(_0562_),
+    .X(_2329_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__a2bb2o_4 _4985_ (.A1_N(_2328_),
+    .A2_N(_2326_),
+    .B1(_2329_),
+    .B2(_2326_),
+    .X(_0276_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4986_ (.A(_1700_),
+    .B(\u_i2cm.u_byte_ctrl.u_bit_ctrl.dSCL ),
+    .X(_2330_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4987_ (.A(_2330_),
+    .Y(_2331_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__o22a_4 _4988_ (.A1(\u_i2cm.u_byte_ctrl.core_rxd ),
+    .A2(_2331_),
+    .B1(\u_i2cm.u_byte_ctrl.u_bit_ctrl.sSDA ),
+    .B2(_2330_),
+    .X(_0275_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__inv_2 _4989_ (.A(\u_uart_core.u_rxfifo.mem[1][7] ),
+    .Y(_2332_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__buf_2 _4990_ (.A(_1883_),
+    .X(_2333_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__or2_4 _4991_ (.A(_1902_),
+    .B(\u_uart_core.u_rxfifo.wr_ptr[2] ),
+    .X(_2334_),
+    .VGND(vssd1),
+    .VNB(vssd1),