signoff/build/gpio_defaults.out

Step 1:  Create new cells for new GPIO default vectors.
Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Step 2:  Modify top-level layouts to use the specified defaults.
Done.