| commit | f56d6b07c4af02ce71190436d958f445fbcd117d | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Dec 10 04:20:36 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Dec 10 04:20:36 2021 +0000 |
| tree | 008b87c9d467d28d155529858fd3990ae4142f79 | |
| parent | 05a1d444b7f4a87bd5d7d8ecffd5054b0c185405 [diff] |
final gds & signoff results
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.