commit | e3c5ff2fb9a75e302e6e4f1a8ef7e3a418c43574 | [log] [tgz] |
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author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Wed Dec 08 16:16:21 2021 +0000 |
committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Wed Dec 08 16:16:21 2021 +0000 |
tree | d1061e614da9c0eddbb4befc1b9a1da63be09bc0 | |
parent | deb1699cf76d2fcf30baf1fe6b5940c13a3ba530 [diff] |
add info
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.