commit | deb1699cf76d2fcf30baf1fe6b5940c13a3ba530 | [log] [tgz] |
---|---|---|
author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Wed Dec 08 11:10:27 2021 +0000 |
committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Wed Dec 08 11:10:27 2021 +0000 |
tree | b5dcf31ae2dceeb0e6667ae3c3373902312065c3 | |
parent | d0db2ab1c38ab9328dc4be9db8f17b5d8de4fd50 [diff] |
update BRAM
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.