| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/axi_dma,axi_dma,axi_dma,Flow_completed,0h36m17s,0h8m28s,70730.32465018527,1.7357759999999998,17682.581162546318,25,1509.72,30693,0,0,0,0,0,0,0,183,0,-1,-1,1877512,260722,-15.22,-15.22,0.0,-1.51,0.0,-1239.27,-1239.27,0.0,0.0,0.0,1263892003,0.0,22.54,23.69,0.17,0.02,-1,30470,31060,9504,10094,0,0,0,30693,207,161,169,161,852,297,120,9135,9643,10128,16,956,23756,686,25398,58.8235294117647,17.0,17,DELAY 2,5,25,1,153.6,153.18,0.3,0,sky130_fd_sc_hd,4,3 |
