blob: 7d65b60ed02db106828f8f20ba6a086d13f820c8 [file] [log] [blame]
project:
category: Test Harness
cover_image: doc/ciic_harness.png
description: Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor
inside of the Caravel test harness intended for use with the SkyWater 130nm PDK.
foundry: SkyWater
git_url: https://github.com/AlexSUnderwood/caravel_riscv_osu.git
layout_image: gds/caravel.png
organization: Oklahoma State University VLSIARCH
organization_url: https://vlsiarch.ecen.okstate.edu/
owner: James Stine
process: SKY130
project_id: 00010028
project_name: Caravel_RISCV_OSU
shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/sky130/mpw-001/slot-040
tags:
- Open MPW
- Test Harness
- RISC-V
top_level_netlist: verilog/gl/caravel.v
user_level_netlist: verilog/gl/user_project_wrapper.v
version: '0.1'