| --- | |
| project: | |
| description: "Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor inside of the Caravel test harness intended for use with the SkyWater 130nm PDK." | |
| foundry: "SkyWater" | |
| git_url: "https://github.com/AlexSUnderwood/caravel_riscv_osu.git" | |
| organization: "Oklahoma State University VLSIARCH" | |
| organization_url: "https://vlsiarch.ecen.okstate.edu/" | |
| owner: "James Stine" | |
| process: "SKY130" | |
| project_name: "Caravel_RISCV_OSU" | |
| tags: | |
| - "Open MPW" | |
| - "Test Harness" | |
| - "RISC-V" | |
| category: "Test Harness" | |
| top_level_netlist: "verilog/gl/caravel.v" | |
| user_level_netlist: "verilog/gl/user_project_wrapper.v" | |
| version: "0.1" | |
| cover_image: "doc/ciic_harness.png" |