| commit | 040355e76bbccc1a1bc90cd6119359563a7249a8 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Feb 05 18:17:51 2021 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Feb 05 18:17:51 2021 -0800 |
| tree | 4da9d8cc062aa1227da8e67378cc6da9c870734f | |
| parent | 9164ebcc550e9b2264f89cd9a0005d560b5fa491 [diff] |
final gds & drc results
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB
