| /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */ |
| |
| module gpio_control_block(mgmt_gpio_in, mgmt_gpio_oeb, mgmt_gpio_out, one, pad_gpio_ana_en, pad_gpio_ana_pol, pad_gpio_ana_sel, pad_gpio_holdover, pad_gpio_ib_mode_sel, pad_gpio_in, pad_gpio_inenb, pad_gpio_out, pad_gpio_outenb, pad_gpio_slow_sel, pad_gpio_vtrip_sel, resetn, serial_clock, serial_data_in, serial_data_out, user_gpio_in, user_gpio_oeb, user_gpio_out, zero, vccd, vssd, vccd1, vssd1, pad_gpio_dm); |
| wire _000_; |
| wire _001_; |
| wire _002_; |
| wire _003_; |
| wire _004_; |
| wire _005_; |
| wire _006_; |
| wire _007_; |
| wire _008_; |
| wire _009_; |
| wire _010_; |
| wire _011_; |
| wire _012_; |
| wire _013_; |
| wire _014_; |
| wire _015_; |
| wire _016_; |
| wire _017_; |
| wire _018_; |
| wire _019_; |
| wire _020_; |
| wire _021_; |
| wire _022_; |
| wire _023_; |
| wire _024_; |
| wire _025_; |
| wire _026_; |
| wire _027_; |
| wire _028_; |
| wire _029_; |
| wire _030_; |
| wire _031_; |
| wire _032_; |
| wire _033_; |
| wire _034_; |
| wire _035_; |
| wire _036_; |
| wire _037_; |
| wire _038_; |
| wire _039_; |
| wire clknet_0_serial_clock; |
| wire clknet_1_0_0_serial_clock; |
| wire clknet_1_1_0_serial_clock; |
| wire gpio_logic1; |
| wire gpio_outenb; |
| wire load_data; |
| wire mgmt_ena; |
| output mgmt_gpio_in; |
| input mgmt_gpio_oeb; |
| input mgmt_gpio_out; |
| output one; |
| output pad_gpio_ana_en; |
| output pad_gpio_ana_pol; |
| output pad_gpio_ana_sel; |
| output [2:0] pad_gpio_dm; |
| output pad_gpio_holdover; |
| output pad_gpio_ib_mode_sel; |
| input pad_gpio_in; |
| output pad_gpio_inenb; |
| output pad_gpio_out; |
| output pad_gpio_outenb; |
| output pad_gpio_slow_sel; |
| output pad_gpio_vtrip_sel; |
| input resetn; |
| input serial_clock; |
| input serial_data_in; |
| output serial_data_out; |
| wire \shift_register[0] ; |
| wire \shift_register[10] ; |
| wire \shift_register[11] ; |
| wire \shift_register[1] ; |
| wire \shift_register[2] ; |
| wire \shift_register[3] ; |
| wire \shift_register[4] ; |
| wire \shift_register[5] ; |
| wire \shift_register[6] ; |
| wire \shift_register[7] ; |
| wire \shift_register[8] ; |
| wire \shift_register[9] ; |
| output user_gpio_in; |
| input user_gpio_oeb; |
| input user_gpio_out; |
| input vccd; |
| input vccd1; |
| input vssd1; |
| input vssd; |
| output zero; |
| sky130_fd_sc_hd__diode_2 ANTENNA_0 ( |
| .DIODE(pad_gpio_inenb), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_0_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_0_36 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_0_63 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_0_7 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_10_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_10_59 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_10_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_11_30 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_11_32 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_12_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_12_52 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_12_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_13_11 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_13_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_13_32 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_14_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_14_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_15_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_15_36 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_45 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_7 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_16_18 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_16_25 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_16_32 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_16_40 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_16_44 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_16_6 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_16_63 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_1_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_1_63 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_1_7 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_2_11 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_2_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_2_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_3_30 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_4_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_5_30 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_5_32 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_5_37 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_6_49 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_6_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_7_26 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_7_36 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_8_18 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_8_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_8_49 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_8_62 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_8_9 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_9_26 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_9_55 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_9_63 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_0 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_1 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_10 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_11 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_12 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_13 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_14 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_15 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_16 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_17 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_18 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_19 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_2 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_20 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_21 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_22 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_23 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_24 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_25 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_26 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_27 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_28 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_29 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_3 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_30 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_31 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_32 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_33 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_34 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_35 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_36 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_37 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_38 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_39 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_4 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_40 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_41 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_42 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_43 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_44 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_45 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_46 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_47 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_48 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_49 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_5 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_50 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_51 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_52 ( |
| .VGND(vssd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_6 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_7 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_8 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_9 ( |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__or2_4 _040_ ( |
| .A(clknet_1_1_0_serial_clock), |
| .B(resetn), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_027_) |
| ); |
| sky130_fd_sc_hd__buf_2 _041_ ( |
| .A(_027_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_028_) |
| ); |
| sky130_fd_sc_hd__buf_2 _042_ ( |
| .A(_028_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_025_) |
| ); |
| sky130_fd_sc_hd__buf_2 _043_ ( |
| .A(_025_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_024_) |
| ); |
| sky130_fd_sc_hd__buf_2 _044_ ( |
| .A(_025_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_023_) |
| ); |
| sky130_fd_sc_hd__buf_2 _045_ ( |
| .A(_025_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_022_) |
| ); |
| sky130_fd_sc_hd__buf_2 _046_ ( |
| .A(_025_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_021_) |
| ); |
| sky130_fd_sc_hd__buf_2 _047_ ( |
| .A(_028_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_029_) |
| ); |
| sky130_fd_sc_hd__buf_2 _048_ ( |
| .A(_029_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_020_) |
| ); |
| sky130_fd_sc_hd__buf_2 _049_ ( |
| .A(_029_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_019_) |
| ); |
| sky130_fd_sc_hd__buf_2 _050_ ( |
| .A(_029_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_018_) |
| ); |
| sky130_fd_sc_hd__buf_2 _051_ ( |
| .A(_029_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_017_) |
| ); |
| sky130_fd_sc_hd__buf_2 _052_ ( |
| .A(_029_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_016_) |
| ); |
| sky130_fd_sc_hd__buf_2 _053_ ( |
| .A(_028_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_030_) |
| ); |
| sky130_fd_sc_hd__buf_2 _054_ ( |
| .A(_030_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_015_) |
| ); |
| sky130_fd_sc_hd__buf_2 _055_ ( |
| .A(_030_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_014_) |
| ); |
| sky130_fd_sc_hd__buf_2 _056_ ( |
| .A(_030_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_013_) |
| ); |
| sky130_fd_sc_hd__buf_2 _057_ ( |
| .A(_030_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_012_) |
| ); |
| sky130_fd_sc_hd__buf_2 _058_ ( |
| .A(_030_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_011_) |
| ); |
| sky130_fd_sc_hd__buf_2 _059_ ( |
| .A(_028_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_031_) |
| ); |
| sky130_fd_sc_hd__buf_2 _060_ ( |
| .A(_031_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_010_) |
| ); |
| sky130_fd_sc_hd__buf_2 _061_ ( |
| .A(_031_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_009_) |
| ); |
| sky130_fd_sc_hd__buf_2 _062_ ( |
| .A(_031_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_008_) |
| ); |
| sky130_fd_sc_hd__buf_2 _063_ ( |
| .A(_031_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_007_) |
| ); |
| sky130_fd_sc_hd__buf_2 _064_ ( |
| .A(_031_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_006_) |
| ); |
| sky130_fd_sc_hd__buf_2 _065_ ( |
| .A(_027_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_032_) |
| ); |
| sky130_fd_sc_hd__buf_2 _066_ ( |
| .A(_032_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_005_) |
| ); |
| sky130_fd_sc_hd__buf_2 _067_ ( |
| .A(_032_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_004_) |
| ); |
| sky130_fd_sc_hd__buf_2 _068_ ( |
| .A(_032_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_003_) |
| ); |
| sky130_fd_sc_hd__buf_2 _069_ ( |
| .A(_032_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_002_) |
| ); |
| sky130_fd_sc_hd__buf_2 _070_ ( |
| .A(_032_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_001_) |
| ); |
| sky130_fd_sc_hd__buf_2 _071_ ( |
| .A(pad_gpio_inenb), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_039_) |
| ); |
| sky130_fd_sc_hd__inv_2 _072_ ( |
| .A(mgmt_ena), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Y(_033_) |
| ); |
| sky130_fd_sc_hd__a32o_4 _073_ ( |
| .A1(gpio_outenb), |
| .A2(mgmt_gpio_oeb), |
| .A3(mgmt_ena), |
| .B1(user_gpio_oeb), |
| .B2(_033_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(pad_gpio_outenb) |
| ); |
| sky130_fd_sc_hd__inv_2 _074_ ( |
| .A(pad_gpio_dm[2]), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Y(_034_) |
| ); |
| sky130_fd_sc_hd__and3_4 _075_ ( |
| .A(mgmt_gpio_oeb), |
| .B(_034_), |
| .C(pad_gpio_dm[1]), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_035_) |
| ); |
| sky130_fd_sc_hd__or2_4 _076_ ( |
| .A(mgmt_gpio_out), |
| .B(_035_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_036_) |
| ); |
| sky130_fd_sc_hd__nand2_4 _077_ ( |
| .A(pad_gpio_dm[0]), |
| .B(_035_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Y(_037_) |
| ); |
| sky130_fd_sc_hd__a32o_4 _078_ ( |
| .A1(mgmt_ena), |
| .A2(_036_), |
| .A3(_037_), |
| .B1(_033_), |
| .B2(user_gpio_out), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(pad_gpio_out) |
| ); |
| sky130_fd_sc_hd__inv_2 _079_ ( |
| .A(pad_gpio_in), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Y(_000_) |
| ); |
| sky130_fd_sc_hd__inv_2 _080_ ( |
| .A(resetn), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Y(_038_) |
| ); |
| sky130_fd_sc_hd__and2_4 _081_ ( |
| .A(clknet_1_1_0_serial_clock), |
| .B(_038_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(load_data) |
| ); |
| sky130_fd_sc_hd__buf_2 _082_ ( |
| .A(_028_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(_026_) |
| ); |
| sky130_fd_sc_hd__ebufn_2 _083_ ( |
| .A(pad_gpio_in), |
| .TE_B(_039_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Z(mgmt_gpio_in) |
| ); |
| sky130_fd_sc_hd__dfstp_4 _084_ ( |
| .CLK(load_data), |
| .D(\shift_register[0] ), |
| .Q(mgmt_ena), |
| .SET_B(_001_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _085_ ( |
| .CLK(load_data), |
| .D(\shift_register[2] ), |
| .Q(pad_gpio_holdover), |
| .RESET_B(_002_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _086_ ( |
| .CLK(load_data), |
| .D(\shift_register[8] ), |
| .Q(pad_gpio_slow_sel), |
| .RESET_B(_003_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _087_ ( |
| .CLK(load_data), |
| .D(\shift_register[9] ), |
| .Q(pad_gpio_vtrip_sel), |
| .RESET_B(_004_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _088_ ( |
| .CLK(load_data), |
| .D(\shift_register[3] ), |
| .Q(pad_gpio_inenb), |
| .RESET_B(_005_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _089_ ( |
| .CLK(load_data), |
| .D(\shift_register[4] ), |
| .Q(pad_gpio_ib_mode_sel), |
| .RESET_B(_006_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfstp_4 _090_ ( |
| .CLK(load_data), |
| .D(\shift_register[1] ), |
| .Q(gpio_outenb), |
| .SET_B(_007_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _091_ ( |
| .CLK(load_data), |
| .D(\shift_register[10] ), |
| .Q(pad_gpio_dm[0]), |
| .RESET_B(_008_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfstp_4 _092_ ( |
| .CLK(load_data), |
| .D(\shift_register[11] ), |
| .Q(pad_gpio_dm[1]), |
| .SET_B(_009_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfstp_4 _093_ ( |
| .CLK(load_data), |
| .D(serial_data_out), |
| .Q(pad_gpio_dm[2]), |
| .SET_B(_010_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _094_ ( |
| .CLK(load_data), |
| .D(\shift_register[5] ), |
| .Q(pad_gpio_ana_en), |
| .RESET_B(_011_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _095_ ( |
| .CLK(load_data), |
| .D(\shift_register[6] ), |
| .Q(pad_gpio_ana_sel), |
| .RESET_B(_012_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _096_ ( |
| .CLK(load_data), |
| .D(\shift_register[7] ), |
| .Q(pad_gpio_ana_pol), |
| .RESET_B(_013_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _097_ ( |
| .CLK(clknet_1_1_0_serial_clock), |
| .D(serial_data_in), |
| .Q(\shift_register[0] ), |
| .RESET_B(_014_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _098_ ( |
| .CLK(clknet_1_1_0_serial_clock), |
| .D(\shift_register[0] ), |
| .Q(\shift_register[1] ), |
| .RESET_B(_015_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _099_ ( |
| .CLK(clknet_1_1_0_serial_clock), |
| .D(\shift_register[1] ), |
| .Q(\shift_register[2] ), |
| .RESET_B(_016_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _100_ ( |
| .CLK(clknet_1_1_0_serial_clock), |
| .D(\shift_register[2] ), |
| .Q(\shift_register[3] ), |
| .RESET_B(_017_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _101_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[3] ), |
| .Q(\shift_register[4] ), |
| .RESET_B(_018_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _102_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[4] ), |
| .Q(\shift_register[5] ), |
| .RESET_B(_019_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _103_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[5] ), |
| .Q(\shift_register[6] ), |
| .RESET_B(_020_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _104_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[6] ), |
| .Q(\shift_register[7] ), |
| .RESET_B(_021_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _105_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[7] ), |
| .Q(\shift_register[8] ), |
| .RESET_B(_022_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _106_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[8] ), |
| .Q(\shift_register[9] ), |
| .RESET_B(_023_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _107_ ( |
| .CLK(clknet_1_1_0_serial_clock), |
| .D(\shift_register[9] ), |
| .Q(\shift_register[10] ), |
| .RESET_B(_024_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _108_ ( |
| .CLK(clknet_1_0_0_serial_clock), |
| .D(\shift_register[10] ), |
| .Q(\shift_register[11] ), |
| .RESET_B(_025_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__dfrtp_4 _109_ ( |
| .CLK(clknet_1_1_0_serial_clock), |
| .D(\shift_register[11] ), |
| .Q(serial_data_out), |
| .RESET_B(_026_), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__clkbuf_16 clkbuf_0_serial_clock ( |
| .A(serial_clock), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(clknet_0_serial_clock) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 clkbuf_1_0_0_serial_clock ( |
| .A(clknet_0_serial_clock), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(clknet_1_0_0_serial_clock) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 clkbuf_1_1_0_serial_clock ( |
| .A(clknet_0_serial_clock), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .X(clknet_1_1_0_serial_clock) |
| ); |
| sky130_fd_sc_hd__conb_1 const_source ( |
| .HI(one), |
| .LO(zero), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd) |
| ); |
| sky130_fd_sc_hd__einvp_8 gpio_in_buf ( |
| .A(_000_), |
| .TE(gpio_logic1), |
| .VGND(vssd), |
| .VNB(vssd), |
| .VPB(vccd), |
| .VPWR(vccd), |
| .Z(user_gpio_in) |
| ); |
| sky130_fd_sc_hd__conb_1 gpio_logic_high ( |
| .HI(gpio_logic1), |
| .VGND(vssd1), |
| .VNB(vssd1), |
| .VPB(vccd1), |
| .VPWR(vccd1) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 gpio_logic_high_tap ( |
| .VGND(vssd1), |
| .VPWR(vccd1) |
| ); |
| assign vssd1 = vssd; |
| endmodule |
