| commit | 9164ebcc550e9b2264f89cd9a0005d560b5fa491 | [log] [tgz] |
|---|---|---|
| author | affanabbasi <69873021+affanabbasi@users.noreply.github.com> | Fri Feb 05 15:09:05 2021 -0600 |
| committer | GitHub <noreply@github.com> | Fri Feb 05 15:09:05 2021 -0600 |
| tree | 9e6e1cc336db300b1ef586067ef33a027db94983 | |
| parent | 6c4c06c25a1d427a9539e9c4ecaed4e70a6bc4b6 [diff] |
gds from drc cleaned mag file
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB