commit	10c1ee322396292192ea3237d8dc312c5694294d	[log] [tgz]
author	Ganesh Gore <goreganesh007@gmail.com>	Thu Dec 17 14:20:26 2020 -0700
committer	Ganesh Gore <goreganesh007@gmail.com>	Thu Dec 17 14:20:26 2020 -0700
tree	b3e18a43d769853c99c1c2b160dd7147ff2c4f62
parent	7ee0335046666720db06b8823ed053bdfb588b91 [diff]

[Localrun03] All clean

OpenFPGA_task/arch/fabric_key.xml[Added - diff]
OpenFPGA_task/arch/openfpga_arch.xml[Added - diff]
OpenFPGA_task/arch/vpr_arch.xml[Added - diff]
OpenFPGA_task/config/task.conf[Added - diff]
OpenFPGA_task/config/task_generation.conf[Added - diff]
OpenFPGA_task/config/task_simulation.conf[Added - diff]
OpenFPGA_task/design_variables.yml[Added - diff]
OpenFPGA_task/generate_fabric.openfpga[Added - diff]
OpenFPGA_task/generate_testbench.openfpga[Added - diff]
OpenFPGA_task/micro_benchmark/and.act[Added - diff]
OpenFPGA_task/micro_benchmark/and.blif[Added - diff]
OpenFPGA_task/micro_benchmark/and.v[Added - diff]
OpenFPGA_task/process_top_def.sh[Added - diff]
OpenFPGA_task/sc_verilog/digital_io_hd.v[Added - diff]
OpenFPGA_task/sc_verilog/fpga_top.v[Added - diff]
OpenFPGA_task/sc_verilog/sky130_fd_sc_hd_wrapper .v[Added - diff]
OpenFPGA_task/user_project_wrapper_empty.def[Added - diff]
OpenFPGA_task/user_project_wrapper_template.def[Added - diff]
checks/KlayoutMerge.log[Added - diff]
checks/caravel.magic.drc[diff]
checks/caravel.magic.drc.mag[diff]
checks/caravel.magic.rdb[diff]
checks/compare_caravel.txt[Added - diff]
checks/full_log.log[diff]
checks/magic_drc.log[diff]
checks/magic_extract.log[diff]
checks/magic_merge_user_project_wrapper.log[diff]
checks/manifest_check.maglef.log[diff]
checks/manifest_check.rtl.log[diff]
checks/spdx_compliance_report.log[diff]
gds/caravel.gds.gz[diff]
gds/user_project_wrapper.gds.gz[diff]
mag/.magicrc[diff]
mag/user_project_wrapper_empty.mag[diff]
qflow/digital_pll_controller/tech[Deleted - diff]
qflow/ring_osc2x13/tech[Deleted - diff]
source_commit_hash.txt[Added - diff]
verilog/OpenFPGA_Verilog/InstancesMap.txt[Added - diff]
verilog/OpenFPGA_Verilog/define_simulation.v[Added - diff]
verilog/OpenFPGA_Verilog/fabric_netlists.v[Added - diff]
verilog/OpenFPGA_Verilog/fpga_core.v[Added - diff]
verilog/OpenFPGA_Verilog/fpga_defines.v[Added - diff]
verilog/OpenFPGA_Verilog/fpga_top.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/grid_clb.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_clb_.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_io_mode_io_.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_io_mode_physical__iopad.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cbx_1__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cbx_1__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cbx_1__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cby_0__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cby_1__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cby_2__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_0__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_0__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_0__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_1__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_1__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_1__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_2__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_2__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_2__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/arch_encoder.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/digital_io_hd.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/fpga_top.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/inv_buf_passgate.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/local_encoder.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/luts.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/memories.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/mux_primitives.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/muxes.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/sky130_fd_sc_hd_wrapper .v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/wires.v[Added - diff]
verilog/OpenFPGA_Verilog/top_include_netlists.v[Added - diff]

80 files changed

tree: b3e18a43d769853c99c1c2b160dd7147ff2c4f62

README.md

Caravel-QLSOFA-HD

Highlights

Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library
Base K4 architecture from VPR with 60 vertical and horizontal channels
Soft adder implementation
Designed using commercial PnR tool

Contribution

NOTE

This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel