OpenFPGA_task/micro_benchmark/and.v - third_party/shuttle/sky130/mpw-001/slot-036 - Git at Google

 `timescale 1ns / 1ps

 module top(
   a,
   b,
   c);

 input wire a;
 input wire b;
 output wire c;

 assign c = a & b;

 endmodule
	`timescale 1ns / 1ps

	module top(
	a,
	b,
	c);

	input wire a;
	input wire b;
	output wire c;

	assign c = a & b;

	endmodule