commit	e88affe28790cd629b3931541fdb30ee64046d45	[log] [tgz]
author	manarabdelaty <manarabdelatty@aucegypt.edu>	Mon Dec 28 18:49:03 2020 +0200
committer	manarabdelaty <manarabdelatty@aucegypt.edu>	Mon Dec 28 18:49:03 2020 +0200
tree	0385b0a7a0dafc21334c79347d56adab77b19b46
parent	914647f379343272c8cfe863582050c761d16511 [diff]

Added N5 simulations

verilog/dv/caravel/user_proj_example/io_ports/Makefile[diff]
verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v[diff]
verilog/rtl/user_project/IPs/DFFRAMBB.v[diff]
verilog/rtl/user_project/IPs/RAM_3Kx32.v[diff]
verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_GPIO.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_bus0.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_db_reg.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_sys_0.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/AHB_2_APB.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_PWM32.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_TIMER32.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_WDT32.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_bus0.v[Deleted - diff]
verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_sys_0.v[Deleted - diff]
verilog/rtl/user_project/rtl/DFFRFile.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/AHBSRAM.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/APB_I2C.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/APB_SPI.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/APB_UART.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/DFFRAM.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/DMC_32x16HC.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/GPIO.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/PWM32.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/QSPI_XIP_CTRL.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/RAM_4Kx32.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/TIMER32.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/WDT32.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/apb2i2c/apb2i2c.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/i2c_master.v[Deleted - diff]
verilog/rtl/user_project/rtl/IPs/spi_master.v[Deleted - diff]
verilog/rtl/user_project/rtl/NfiVe32.v[Deleted - diff]
verilog/rtl/user_project/rtl/acc/AHB_SPM.v[Deleted - diff]
verilog/rtl/user_project/rtl/soc_core.v[Deleted - diff]
verilog/rtl/user_project/rtl/user_project_wrapper.v[Deleted - diff]
verilog/rtl/user_project/soc_core.v[diff]

37 files changed

tree: 0385b0a7a0dafc21334c79347d56adab77b19b46

README.md

Caravel_N5_SoC