Add Microwatt to Caravel
This adds the Microwatt OpenPOWER core to the Caravel project.
diff --git a/README.rst b/README.rst
index 62c2da9..3d69ae9 100644
--- a/README.rst
+++ b/README.rst
@@ -18,251 +18,18 @@
# SPDX-License-Identifier: Apache-2.0
-->
-CIIC Harness
-============
+Microwatt on Caravel
+====================
-|License| |Documentation Status| |Build Status|
-
-A template SoC for Google SKY130 free shuttles. It is still WIP. The
-current SoC architecture is given below.
+The Microwatt 64 bit OpenPOWER core integrated into the Caravel Google SKY130 free shuttles.
.. raw:: html
<p align="center">
- <img src="/docs/source/_static/ciic_harness.png" width="75%" height="75%">
+ <img src="/docs/source/_static/microwatt-caravel.png" width="75%" height="75%">
</p>
-Datasheet and detailed documentation exists here:
-https://caravel-harness.readthedocs.io/en/develop/
+Tests
+=====
-.. raw:: html
-
- <!---
- # SPDX-FileCopyrightText: 2020 Efabless Corporation
- #
- # Licensed under the Apache License, Version 2.0 (the "License");
- # you may not use this file except in compliance with the License.
- # You may obtain a copy of the License at
- #
- # http://www.apache.org/licenses/LICENSE-2.0
- #
- # Unless required by applicable law or agreed to in writing, software
- # distributed under the License is distributed on an "AS IS" BASIS,
- # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- # See the License for the specific language governing permissions and
- # limitations under the License.
- #
- # SPDX-License-Identifier: Apache-2.0
- -->
-.. _getting-started:
-
-Getting Started
-===============
-
-- For information on tooling and versioning, please refer to `tool-versioning.rst <./docs/source/tool-versioning.rst>`__.
-
-Start by cloning the repo and uncompressing the files.
-
-.. code:: bash
-
- git clone https://github.com/efabless/caravel.git
- cd caravel
- make uncompress
-
-Then you need to install the open\_pdks prerequisite:
-
-- `Magic VLSI Layout
- Tool <http://opencircuitdesign.com/magic/index.html>`__ is needed to
- run open\_pdks -- version >= 8.3.60\*
-
- **NOTE:**
-
- You can avoid the need for the magic prerequisite by using
- the openlane docker to do the installation step in open\_pdks. This
- could be done by cloning
- `openlane <https://github.com/efabless/openlane/tree/master>`__ and
- following the instructions given there to use the Makefile.
-
-Install the required version of the PDK by running the following
-commands:
-
-.. code:: bash
-
- export PDK_ROOT=<The place where you want to install the pdk>
- make pdk
-
-Then, you can learn more about the caravel chip by watching these video:
-
-- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
-- Aboard Caravel -- How to put your design on Caravel? --
- https://youtu.be/9QV8SDelURk
-- Things to Clarify About Caravel -- What versions to use with Caravel?
- -- https://youtu.be/-LZ522mxXMw
-
- - You could only use openlane:rc6
- - Make sure you have the commit hashes provided here inside the
- `Makefile <https://github.com/efabless/caravel/blob/master/Makefile>`__
-
-Aboard Caravel
---------------
-
-Your area is the full user\_project\_wrapper, so feel free to add your
-project there or create a differnt macro and harden it seperately then
-insert it into the user\_project\_wrapper. For example, if your design
-is analog or you're using a different tool other than OpenLANE.
-
-If you will use OpenLANE to harden your design, go through the
-instructions in this `README <https://github.com/efabless/caravel/blob/develop/openlane/README.rst>`__.
-
-You must copy your synthesized gate-level-netlist for
-``user_project_wrapper`` to ``verilog/gl/`` and overwrite
-``user_project_wrapper.v``. Otherwise, you can point to it in
-`info.yaml <https://github.com/efabless/caravel/blob/master/info.yaml>`__.
-
-**NOTE:**
-
- If you're using openlane to harden your design, this should
- happen automatically.
-
-Then, you will need to put your design aboard the Caravel chip. Make
-sure you have the following:
-
-- `Magic VLSI Layout
- Tool <http://opencircuitdesign.com/magic/index.html>`__ installed on
- your machine. We may provide a Dockerized version later.\*
-- You have your user\_project\_wrapper.gds under ``./gds/`` in the
- Caravel directory.
-
-**NOTE:**
-
- You can avoid the need for the magic prerequisite by
- using the openlane docker to run the make step. This
- `section <#running-make-using-openlane-magic>`__ shows how.
-
-Run the following command:
-
-.. code:: bash
-
- export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step>
- make
-
-|Expectation_DRC|
-
-Running Make using OpenLANE Magic
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-To use the magic installed inside Openlane to complete the final GDS
-streaming out step, export the following:
-
-.. code:: bash
-
- export PDK_ROOT=<The location where the pdk is installed>
- export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
- export IMAGE_NAME=<the openlane image name installed on your machine. Preferably openlane:rc6>
- export CARAVEL_PATH=$(pwd)
-
-Then, mount the docker:
-
-.. code:: bash
-
- docker run -it -v $CARAVEL_PATH:$CARAVEL_PATH -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e CARAVEL_PATH=$CARAVEL_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME
-
-Finally, once inside the docker run the following commands:
-
-.. code:: bash
-
- cd $CARAVEL_PATH
- make
- exit
-
-|Expectation_DRC|
-
-IMPORTANT
-^^^^^^^^^
-
-Please make sure to run ``make compress`` before commiting anything to
-your repository. Avoid having 2 versions of the
-gds/user\_project\_wrapper.gds or gds/caravel.gds one compressed and the
-other not compressed.
-
-Required Directory Structure
-----------------------------
-
-- ./gds/ : includes all the gds files used or produced from the
- project.
-- ./def/ : includes all the def files used or produced from the
- project.
-- ./lef/ : includes all the lef files used or produced from the
- project.
-- ./mag/ : includes all the mag files used or produced from the
- project.
-- ./maglef/ : includes all the maglef files used or produced from the
- project.
-- ./spi/lvs/ : includes all the maglef files used or produced from the
- project.
-- ./verilog/dv/ : includes all the simulation test benches and how to
- run them.
-- ./verilog/gl/ : includes all the synthesized/elaborated netlists.
-- ./verilog/rtl/ : includes all the Verilog RTLs and source files.
-- ./openlane/\ ``<macro>``/ : includes all configuration files used to
- run openlane on your project.
-- info.yaml: includes all the info required in `this
- example <https://github.com/efabless/caravel/blob/master/info.yaml>`__. Please make sure that you are pointing to an
- elaborated caravel netlist as well as a synthesized
- gate-level-netlist for the user\_project\_wrapper
-
-Managment SoC
--------------
-
-The managment SoC runs firmware that can be used to:
-
-- Configure User Project I/O pads
-- Observe and control User Project signals (through on-chip logic
- analyzer probes)
-- Control the User Project power supply
-
-The memory map of the management SoC can be found
-`here <https://github.com/efabless/caravel/blob/master/verilog/rtl/README>`__
-
-User Project Area
------------------
-
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).
-
-See `the Caravel premliminary datasheet` https://caravel-harness.readthedocs.io/en/develop/ for details.
-
-The repository contains a `sample user project <https://github.com/efabless/caravel/blob/master/verilog/rtl/user_proj_example.v>`__ that contains a binary 32-bit up counter.
-
-.. raw:: html
-
- <p align="center">
- <img src="/docs/source/_static/counter_32.png" width="50%" height="50%">
- </p>
-
-The firmware running on the Management Area SoC, configures the I/O pads
-used by the counter and uses the logic probes to observe/control the
-counter. Three firmware examples are provided:
-
-#. Configure the User Project I/O pads as o/p. Observe the counter value
- in the testbench: `IO\_Ports
- Test <https://github.com/efabless/caravel/blob/master/verilog/dv/caravel/user_proj_example/io_ports>`__.
-#. Configure the User Project I/O pads as o/p. Use the Chip LA to load
- the counter and observe the o/p till it reaches 500:
- `LA\_Test1 <https://github.com/efabless/caravel/blob/master/verilog/dv/caravel/user_proj_example/la_test1>`__.
-#. Configure the User Project I/O pads as o/p. Use the Chip LA to
- control the clock source and reset signals and observe the counter
- value for five clock cylcles:
- `LA\_Test2 <https://github.com/efabless/caravel/blob/master/verilog/dv/caravel/user_proj_example/la_test2>`__.
-
-.. |Expectation_DRC| replace:: This should merge the GDSes using magic and you'll end up with your version of ``./gds/caravel.gds``. You should expect ^40 magic DRC violations with the current "development" state of caravel.
-
-.. |License| image:: https://img.shields.io/github/license/efabless/caravel
- :alt: GitHub license - Apache 2.0
- :target: https://github.com/efabless/caravel
-.. |Documentation Status| image:: https://readthedocs.org/projects/caravel-harness/badge/?version=latest
- :alt: ReadTheDocs Badge - https://caravel-harness.rtfd.io
- :target: https://caravel-harness.readthedocs.io/en/latest/?badge=latest
-.. |Build Status| image:: https://travis-ci.com/efabless/caravel.svg?branch=master
- :alt: Travis Badge - https://travis-ci.org/efabless/caravel
- :target: https://travis-ci.com/efabless/caravel
-
+- Check out verilog/dv/caravel/microwatt/README.md
diff --git a/docs/source/_static/microwatt-caravel.png b/docs/source/_static/microwatt-caravel.png
new file mode 100644
index 0000000..b09ae98
--- /dev/null
+++ b/docs/source/_static/microwatt-caravel.png
Binary files differ
diff --git a/info.yaml b/info.yaml
index 35806bf..9c86098 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,19 +1,18 @@
---
project:
- description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+ description: "Microwatt 64 bit OpenPOWER core"
foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
+ git_url: "https://github.com/antonblanchard/microwatt-caravel.git"
+ organization: "IBM"
+ organization_url: "http://ibm.com"
+ owner: "Anton Blanchard"
process: "SKY130"
- project_name: "Caravel"
- project_id: "00000000"
+ project_name: "Microwatt"
+ project_id: "00000077"
tags:
- "Open MPW"
- - "Test Harness"
- category: "Test Harness"
+ category: "processor"
top_level_netlist: "verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
- cover_image: "docs/source/_static/ciic_harness.png"
+ cover_image: "docs/source/_static/microwatt-caravel.png"
diff --git a/openlane/RAM_512x64/config.tcl b/openlane/RAM_512x64/config.tcl
index 32dcadf..8715009 100644
--- a/openlane/RAM_512x64/config.tcl
+++ b/openlane/RAM_512x64/config.tcl
@@ -43,7 +43,7 @@
#set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
#set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 3
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
diff --git a/openlane/dcache/config.tcl b/openlane/dcache/config.tcl
new file mode 100644
index 0000000..55c554d
--- /dev/null
+++ b/openlane/dcache/config.tcl
@@ -0,0 +1,52 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) dcache
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/dcache.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 750 750"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.56
+set ::env(CELL_PAD) 2
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+ set ::env(ROUTING_CORES) $result
+} else {
+ set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/dcache/pin_order.cfg b/openlane/dcache/pin_order.cfg
new file mode 100644
index 0000000..1aed545
--- /dev/null
+++ b/openlane/dcache/pin_order.cfg
@@ -0,0 +1,14 @@
+#N
+wishbone_in.*
+wishbone_out.*
+
+#W
+clk
+rst
+m_in.*
+m_out.*
+
+#S
+stall_out
+d_in.*
+d_out.*
diff --git a/openlane/icache/config.tcl b/openlane/icache/config.tcl
new file mode 100644
index 0000000..d9bb310
--- /dev/null
+++ b/openlane/icache/config.tcl
@@ -0,0 +1,45 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) icache
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/icache.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "15"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 680 680"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.56
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+ set ::env(ROUTING_CORES) $result
+} else {
+ set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/icache/pin_order.cfg b/openlane/icache/pin_order.cfg
new file mode 100644
index 0000000..7334de4
--- /dev/null
+++ b/openlane/icache/pin_order.cfg
@@ -0,0 +1,16 @@
+#N
+wishbone_in.*
+wishbone_out.*
+
+#E
+clk
+rst
+m_in.*
+
+#S
+i_in.*
+i_out.*
+flush_in
+inval_in
+stall_in
+stall_out
diff --git a/openlane/multiply_4/config.tcl b/openlane/multiply_4/config.tcl
new file mode 100644
index 0000000..7ea0ffe
--- /dev/null
+++ b/openlane/multiply_4/config.tcl
@@ -0,0 +1,52 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) multiply_4
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/multiply_4.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "30"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1100 1100"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+ set ::env(ROUTING_CORES) $result
+} else {
+ set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/multiply_4/pin_order.cfg b/openlane/multiply_4/pin_order.cfg
new file mode 100644
index 0000000..1f9b365
--- /dev/null
+++ b/openlane/multiply_4/pin_order.cfg
@@ -0,0 +1,6 @@
+#N
+clk
+m_in.*
+
+#E
+m_out.*
diff --git a/openlane/register_file/config.tcl b/openlane/register_file/config.tcl
new file mode 100644
index 0000000..3798972
--- /dev/null
+++ b/openlane/register_file/config.tcl
@@ -0,0 +1,52 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) register_file
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/register_file.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "20"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1100 1100"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+ set ::env(ROUTING_CORES) $result
+} else {
+ set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/register_file/pin_order.cfg b/openlane/register_file/pin_order.cfg
new file mode 100644
index 0000000..1fa4e07
--- /dev/null
+++ b/openlane/register_file/pin_order.cfg
@@ -0,0 +1,7 @@
+#N
+clk
+d_in.*
+d_out.*
+
+#W
+w_in.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e60639f..4d27b15 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -25,13 +25,15 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/microwatt.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+# Should we switch to independent clock?
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "35"
## Internal Macros
### Macro Placement
@@ -39,25 +41,63 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $script_dir/../../verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/RAM_512x64.v \
+ $script_dir/../../verilog/rtl/register_file.v \
+ $script_dir/../../verilog/rtl/multiply_4.v \
+ $script_dir/../../verilog/rtl/icache.v \
+ $script_dir/../../verilog/rtl/dcache.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
+ $script_dir/../../lef/RAM_512x64.lef \
+ $script_dir/../../lef/register_file.lef \
+ $script_dir/../../lef/multiply_4.lef \
+ $script_dir/../../lef/icache.lef \
+ $script_dir/../../lef/dcache.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
+ $script_dir/../../gds/RAM_512x64.gds \
+ $script_dir/../../gds/register_file.gds \
+ $script_dir/../../gds/multiply_4.gds \
+ $script_dir/../../gds/icache.gds \
+ $script_dir/../../gds/dcache.gds"
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.20
+set ::env(CELL_PAD) 8
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
+#set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+#set ::env(FP_TAPCELL_DIST) 13
+
+set ::env(GLB_RT_OBS) "met5 60.000 2720.000 2860.000 3420.000, met4 60.000 2720.000 2860.000 3420.000, met5 60.000 1740.000 740.000 2420.000, met4 60.000 1740.000 740.000 2420.000, met5 2110.000 1720.000 2860.000 2470.000, met4 2110.000 1720.000 2860.000 2470.000, met5 60.000 100.000 1160.000 1200.000, met4 60.000 100.000 1160.000 1200.000, met5 1760.000 100.000 2860.000 1200.000, met4 1760.000 100.000 2860.000 1200.000"
+
+set ::env(FP_HORIZONTAL_HALO) 70
+set ::env(FP_VERTICAL_HALO) 47.5
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(GLB_RT_ALLOW_CONGESTION) 1
+
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) 400
+
+if {[catch {exec nproc} result] == 0} {
+ set ::env(ROUTING_CORES) $result
+} else {
+ set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
# DON'T TOUCH THE FOLLOWING SECTIONS
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index cab6c9d..6a71318 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,5 @@
-mprj 1175 1700 N
+microwatt_0.soc0.bram.bram0.ram_0.memory_0 60.000 2720.000 N
+microwatt_0.soc0.processor.icache_0 60.000 1740.000 N
+microwatt_0.soc0.processor.dcache_0 2110.000 1720.000 N
+microwatt_0.soc0.processor.execute1_0.multiply_0 60.000 100.000 N
+microwatt_0.soc0.processor.register_file_0 1760.000 100.000 N
diff --git a/openlane/user_project_wrapper/scripts/layout.py b/openlane/user_project_wrapper/scripts/layout.py
new file mode 100755
index 0000000..61661b7
--- /dev/null
+++ b/openlane/user_project_wrapper/scripts/layout.py
@@ -0,0 +1,73 @@
+#!/usr/bin/python3
+
+import re
+import os
+
+X=0
+Y=1
+
+# Wrapper size
+die_size = (2920, 3520)
+
+r = re.compile('SIZE ([0-9\.]+) BY ([0-9\.]+) ;')
+
+def get_macro_size(name):
+ lef_file = os.path.dirname(os.path.abspath(__file__)) + '/../../../lef/' + name + '.lef'
+ with open(lef_file) as f:
+ for line in f:
+ m = r.search(line)
+ if m:
+ lx = float(m.group(1))
+ ly = float(m.group(2))
+ return (lx, ly)
+
+
+# Macro sizes
+#ram = (2800, 550)
+#icache = ( 660, 660)
+#dcache = ( 720, 720)
+#multiply_4 = ( 800, 800)
+#regfile = (1000, 1000)
+ram = get_macro_size('RAM_512x64')
+icache = get_macro_size('icache')
+dcache = get_macro_size('dcache')
+multiply_4 = get_macro_size('multiply_4')
+regfile = get_macro_size('register_file')
+
+horizontal_margin = 60
+vertical_margin = 100
+
+# Macro layout
+
+# RAM at top
+ram_l = (horizontal_margin, die_size[Y]-ram[Y]-vertical_margin)
+
+# Caches in the middle
+icache_l = (horizontal_margin, die_size[Y]-icache[Y]-1100)
+dcache_l = (die_size[X]-dcache[X]-horizontal_margin, die_size[Y]-dcache[Y]-1050)
+
+# Multiply and regfile at bottom
+multiply_4_l = (horizontal_margin, vertical_margin)
+regfile_l = (die_size[X]-regfile[X]-horizontal_margin, vertical_margin)
+
+print('microwatt_0.soc0.bram.bram0.ram_0.memory_0 %8.3f %8.3f N' % ram_l)
+print('microwatt_0.soc0.processor.icache_0 %8.3f %8.3f N' % icache_l)
+print('microwatt_0.soc0.processor.dcache_0 %8.3f %8.3f N' % dcache_l)
+print('microwatt_0.soc0.processor.execute1_0.multiply_0 %8.3f %8.3f N' % multiply_4_l)
+print('microwatt_0.soc0.processor.register_file_0 %8.3f %8.3f N' % regfile_l)
+
+def print_obs(sz, base, last=False):
+ sep = ''
+ if not last:
+ sep = ', '
+ print('met5 %.3f %.3f %.3f %.3f, ' % (base[X], base[Y], base[X]+sz[X], base[Y]+sz[Y]), end='')
+ print('met4 %.3f %.3f %.3f %.3f%s' % (base[X], base[Y], base[X]+sz[X], base[Y]+sz[Y], sep), end='')
+
+print()
+print('set ::env(GLB_RT_OBS) "', end='')
+print_obs(ram, ram_l)
+print_obs(icache, icache_l)
+print_obs(dcache, dcache_l)
+print_obs(multiply_4, multiply_4_l)
+print_obs(regfile, regfile_l, last=True)
+print('"')
diff --git a/scripts/microwatt-build-caravel.sh b/scripts/microwatt-build-caravel.sh
new file mode 100755
index 0000000..d1c5639
--- /dev/null
+++ b/scripts/microwatt-build-caravel.sh
@@ -0,0 +1,9 @@
+#!/bin/bash -e
+
+cd $CARAVEL_PATH
+make uncompress
+cd openlane
+
+make user_project_wrapper
+
+docker run --rm -v $CARAVEL_PATH:$CARAVEL_PATH -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e CARAVEL_PATH=$CARAVEL_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME sh -c "cd $CARAVEL_PATH && make"
diff --git a/scripts/microwatt-build-macros.sh b/scripts/microwatt-build-macros.sh
new file mode 100755
index 0000000..46dc226
--- /dev/null
+++ b/scripts/microwatt-build-macros.sh
@@ -0,0 +1,12 @@
+#!/bin/bash -e
+
+cd $CARAVEL_PATH
+make uncompress
+cd openlane
+
+for macro in icache dcache register_file multiply_4 RAM_512x64
+do
+ make $macro < /dev/null &
+done
+
+wait
diff --git a/scripts/microwatt-commit-caravel.py b/scripts/microwatt-commit-caravel.py
new file mode 100755
index 0000000..840e377
--- /dev/null
+++ b/scripts/microwatt-commit-caravel.py
@@ -0,0 +1,95 @@
+#!/usr/bin/env python3
+
+import os
+import sys
+import subprocess
+
+compress_size = 100*1000*1000
+gzip_compress_size_max = 200*1000*1000
+gzip_compress_cmd = [ 'gzip', '-9', '-f' ]
+xz_compress_cmd = [ 'xz', '-9', '-f' ]
+gzip_uncompress_cmd = [ 'gzip', '-d', '-f' ]
+xz_uncompress_cmd = [ 'xz', '-d', '-f' ]
+
+files = [ "def/user_project_wrapper.def",
+ "gds/user_project_wrapper.gds",
+ "lef/user_project_wrapper.lef",
+ "mag/user_project_wrapper.mag",
+ "maglef/user_project_wrapper.mag",
+ "spi/lvs/user_project_wrapper.spice",
+ "verilog/gl/user_project_wrapper.v",
+ "gds/caravel.gds"
+]
+
+# Check all the files exist
+for fname in files:
+ try:
+ s = os.stat(fname)
+ except:
+ print("%s doesn't exist" % fname)
+ sys.exit(1)
+
+
+add_files = list()
+rm_files = list()
+
+for fname in files:
+ sz = os.stat(fname).st_size
+ if sz > gzip_compress_size_max:
+ cmd = xz_compress_cmd.copy()
+ cmd.append(fname)
+ print(cmd)
+ subprocess.check_call(cmd)
+
+ rm_files.append(fname)
+ rm_files.append(fname + '.gz')
+ add_files.append(fname + '.xz')
+ elif sz > compress_size or 'gds' in fname:
+ cmd = gzip_compress_cmd.copy()
+ cmd.append(fname)
+ print(cmd)
+ subprocess.check_call(cmd)
+
+ rm_files.append(fname)
+ rm_files.append(fname + '.xz')
+ add_files.append(fname + '.gz')
+ else:
+ rm_files.append(fname + '.gz')
+ rm_files.append(fname + '.xz')
+ add_files.append(fname)
+
+
+checked_rm_files = list()
+for f in rm_files:
+ cmd = [ 'git', 'rm', f ]
+ try:
+ print(cmd)
+ subprocess.check_call(cmd)
+ checked_rm_files.append(f)
+ except:
+ pass
+
+
+cmd = [ 'git', 'add' ]
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+cmd = [ 'git', 'commit', '-m', 'Tape out' ]
+cmd.extend(checked_rm_files)
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+# Uncompress files now they've been checked in
+for fname in add_files:
+ if fname.endswith('.gz'):
+ cmd = gzip_uncompress_cmd.copy()
+ cmd.append(fname)
+ print(cmd)
+ subprocess.check_call(cmd)
+ elif fname.endswith('.xz'):
+ cmd = xz_uncompress_cmd.copy()
+ cmd.append(fname)
+ print(cmd)
+ subprocess.check_call(cmd)
diff --git a/scripts/microwatt-commit-macros.py b/scripts/microwatt-commit-macros.py
new file mode 100755
index 0000000..8fa3bae
--- /dev/null
+++ b/scripts/microwatt-commit-macros.py
@@ -0,0 +1,87 @@
+#!/usr/bin/env python3
+
+import os
+import sys
+import subprocess
+
+compress_size = 100*1000*1000
+gzip_compress_cmd = [ 'gzip', '-9', '-f' ]
+gzip_uncompress_cmd = [ 'gzip', '-d', '-f' ]
+
+macros = [ 'RAM_512x64',
+ 'dcache',
+ 'icache',
+ 'multiply_4',
+ 'register_file'
+]
+
+# Directories and extensions
+dirs = [ ('def', 'def'),
+ ('gds', 'gds'),
+ ('lef', 'lef'),
+ ('mag', 'mag'),
+ ('maglef', 'mag'),
+ ('spi/lvs', 'spice'),
+ ('verilog/gl', 'v')
+]
+
+# Check all the files exist
+for (dir, ext) in dirs:
+ for macro in macros:
+ fname = '%s/%s.%s' % (dir, macro, ext)
+ try:
+ s = os.stat(fname)
+ except:
+ print("%s doesn't exist" % fname)
+ sys.exit(1)
+
+
+add_files = list()
+rm_files = list()
+
+for (dir, ext) in dirs:
+ for macro in macros:
+ fname = '%s/%s.%s' % (dir, macro, ext)
+ sz = os.stat(fname).st_size
+ if sz > compress_size or 'gds' in dir:
+ cmd = gzip_compress_cmd.copy()
+ cmd.append(fname)
+ print(cmd)
+ subprocess.check_call(cmd)
+
+ rm_files.append(fname)
+ add_files.append(fname + '.gz')
+ else:
+ rm_files.append(fname + '.gz')
+ add_files.append(fname)
+
+
+checked_rm_files = list()
+for f in rm_files:
+ cmd = [ 'git', 'rm', f ]
+ try:
+ print(cmd)
+ subprocess.check_call(cmd)
+ checked_rm_files.append(f)
+ except:
+ pass
+
+
+cmd = [ 'git', 'add' ]
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+cmd = [ 'git', 'commit', '-m', 'Build macros' ]
+cmd.extend(checked_rm_files)
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+# Uncompress files now they've been checked in
+for fname in add_files:
+ if fname.endswith('.gz'):
+ cmd = gzip_uncompress_cmd.copy()
+ cmd.append(fname)
+ print(cmd)
+ subprocess.check_call(cmd)
diff --git a/scripts/microwatt-tape-out.sh b/scripts/microwatt-tape-out.sh
new file mode 100755
index 0000000..82efa30
--- /dev/null
+++ b/scripts/microwatt-tape-out.sh
@@ -0,0 +1,13 @@
+#!/bin/bash -e
+
+export OPENLANE_IMAGE_NAME=localhost/openlane:rc7
+export IMAGE_NAME=$OPENLANE_IMAGE_NAME
+export PDK_ROOT=/shared/anton/pdk.rc7
+export OPENLANE_ROOT=/shared/anton/openlane.rc7
+
+export CARAVEL_PATH="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"/../
+
+$CARAVEL_PATH/scripts/microwatt-build-macros.sh
+$CARAVEL_PATH/scripts/microwatt-commit-macros.py
+$CARAVEL_PATH/scripts/microwatt-build-caravel.sh
+$CARAVEL_PATH/scripts/microwatt-commit-caravel.py
diff --git a/verilog/dv/caravel/microwatt/README.md b/verilog/dv/caravel/microwatt/README.md
new file mode 100644
index 0000000..7661dd8
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/README.md
@@ -0,0 +1,46 @@
+# Microwatt Tests
+
+To run these you need icarus verilog, a riscv toolchain and a ppc64le
+toolchain. On Fedora these are available as packages:
+
+```
+sudo dnf install iverilog gcc-riscv64-linux-gnu gcc-powerpc64le-linux-gnu
+```
+
+And on Ubuntu:
+
+```
+sudo apt install iverilog gcc-riscv64-linux-gnu gcc-powerpc64le-linux-gnu
+```
+
+The test cases need a path to the PDK, eg:
+
+```
+make PDK_PATH=/home/anton/pdk/sky130A
+```
+
+## minimal
+This is probably where you should start. This is a minimal test that verifies
+that Microwatt is running. The SPI flash controller is lightly tested because
+Microwatt uses it to fetch instructions for the test case. The logic analyzer
+is also lightly tested because Microwatt uses that to signal back to the
+management engine that it is alive.
+
+## uart
+This tests the management engine handing over the TX and RX I/O pins to
+Microwatt, and Microwatt receiving a character and echoing it back.
+
+## logic_analyzer
+Microwatt has 32 LA inputs and 32 LA outputs hooked up. This tests that
+functionality by ping ponging an LFSR sequence between the management engine
+and Microwatt. Each value in the sequence is checked before emitting the next
+one.
+
+## spi_flash
+Before starting flash is initialized with a hash of the offset. The test case
+then does reads at various offsets and checks if the values returned are
+correct.
+
+## memory_test
+A simple memory tester. Writes hashes of the offset of memory into memory,
+then reads them back.
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/Makefile b/verilog/dv/caravel/microwatt/external_bus_minimal/Makefile
new file mode 100644
index 0000000..ccbe467
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = external_bus_minimal
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ $(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+ $(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds
+ $(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S
+
+microwatt.hex: microwatt.elf
+ $(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@F000/@0000/g' $@
+
+clean:
+ rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/external_bus_minimal_tb.v b/verilog/dv/caravel/microwatt/external_bus_minimal/external_bus_minimal_tb.v
new file mode 100644
index 0000000..b2d2e27
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/external_bus_minimal_tb.v
@@ -0,0 +1,333 @@
+`default_nettype none
+/*
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ * Copyright (C) 2020 Anton Blanchard <anton@linux.ibm.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+
+module external_bus_tb (
+ input clk,
+
+ input [7:0] ext_bus_in,
+ input ext_bus_pty_in,
+
+ output [7:0] ext_bus_out,
+ output ext_bus_pty_out
+);
+ localparam [7:0] CMD_READ = 8'h2;
+ localparam [7:0] CMD_WRITE = 8'h3;
+ localparam [7:0] CMD_READ_ACK = 8'h82;
+ localparam [7:0] CMD_WRITE_ACK = 8'h83;
+
+ localparam [3:0] ADDR_BYTES = 4;
+ localparam [3:0] DATA_BYTES = 8;
+
+ localparam [3:0] READ_DELAY_CYCLES = 8;
+
+ localparam [3:0] RECV_STATE_IDLE = 0;
+ localparam [3:0] RECV_STATE_WRITE_ADDR = 1;
+ localparam [3:0] RECV_STATE_WRITE_DATA = 2;
+ localparam [3:0] RECV_STATE_WRITE_SEL = 3;
+ localparam [3:0] RECV_STATE_READ_ADDR = 4;
+ localparam [3:0] RECV_STATE_READ_DELAY = 5;
+ reg [3:0] recv_state;
+
+ reg [31:0] recv_addr;
+ reg [63:0] recv_data;
+ reg [7:0] recv_sel;
+ reg [3:0] recv_count;
+ reg [127:0] tx_data;
+
+ reg [7:0] bus_out;
+
+ assign ext_bus_out = bus_out;
+ assign ext_bus_pty_out = ~^bus_out;
+
+ initial begin
+ bus_out <= 8'h0;
+ recv_state <= 0;
+ recv_addr <= 0;
+ recv_sel <= 0;
+ recv_data <= 0;
+ recv_count <= 0;
+ tx_data <= 0;
+ end
+
+ // receive on positive edge
+ always @(posedge clk) begin
+ if (ext_bus_pty_in != ~^ext_bus_in) begin
+ $display("Bad parity on bus");
+ $fatal;
+ end
+
+ case (recv_state)
+ RECV_STATE_IDLE: begin
+ //$display("Idle state");
+
+ if (ext_bus_in == CMD_WRITE) begin
+ $display("Got write command");
+ recv_state <= RECV_STATE_WRITE_ADDR;
+ recv_addr <= 0;
+ recv_sel <= 0;
+ recv_data <= 0;
+ recv_count <= ADDR_BYTES;
+ end
+ if (ext_bus_in == CMD_READ) begin
+ $display("Got read command");
+ recv_state <= RECV_STATE_READ_ADDR;
+ recv_addr <= 0;
+ recv_sel <= 0;
+ recv_data <= 0;
+ recv_count <= ADDR_BYTES;
+ end
+ end
+
+ RECV_STATE_WRITE_ADDR: begin
+ $display("RECV_STATE_WRITE_ADDR state");
+
+ recv_addr <= { ext_bus_in, recv_addr[23:8] };
+ $display("A: %02x", ext_bus_in);
+ if (recv_count == 1) begin
+ recv_state <= RECV_STATE_WRITE_SEL;
+ end else begin
+ recv_count <= recv_count - 1;
+ end
+ end
+
+ RECV_STATE_WRITE_SEL: begin
+ $display("RECV_STATE_WRITE_SEL state");
+
+ $display("S: %02x", ext_bus_in);
+ recv_sel <= ext_bus_in;
+ recv_state <= RECV_STATE_WRITE_DATA;
+ recv_count <= DATA_BYTES;
+ end
+
+ RECV_STATE_WRITE_DATA: begin
+ $display("RECV_STATE_WRITE_DATA state");
+
+ recv_data <= { ext_bus_in, recv_addr[23:8] };
+ $display("D: %02x", ext_bus_in);
+ if (recv_count == 1) begin
+ tx_data <= CMD_WRITE_ACK;
+ recv_state <= RECV_STATE_IDLE;
+ end else begin
+ recv_count <= recv_count - 1;
+ end
+ end
+
+ RECV_STATE_READ_ADDR: begin
+ $display("RECV_STATE_READ_ADDR state");
+
+ recv_addr <= { ext_bus_in, recv_addr[23:8] };
+ $display("A: %02x", ext_bus_in);
+ if (recv_count == 1) begin
+ recv_count <= READ_DELAY_CYCLES;
+ recv_state <= RECV_STATE_READ_DELAY;
+ end else begin
+ recv_count <= recv_count - 1;
+ end
+ end
+
+ RECV_STATE_READ_DELAY: begin
+ $display("RECV_STATE_READ_DELAY state");
+ if (recv_count == 1) begin
+ tx_data <= { 64'h0102030405060708, CMD_READ_ACK};
+ recv_state <= RECV_STATE_IDLE;
+ end else begin
+ recv_count <= recv_count - 1;
+ end
+ end
+
+ default: begin
+ $display("BAD state");
+ $fatal;
+ end
+ endcase
+ end
+
+ // transmit on negative edge
+ always @(negedge clk) begin
+ if (|tx_data) begin
+ $display("T: %02x", tx_data[7:0]);
+ bus_out <= tx_data[7:0];
+ tx_data <= tx_data[127:8];
+ end else begin
+ bus_out <= 8'h0;
+ end
+ end
+endmodule
+
+module external_bus_minimal_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire user_flash_csb;
+ wire user_flash_clk;
+ inout user_flash_io0;
+ inout user_flash_io1;
+ wire ext_bus_clk;
+ wire [7:0] ext_bus_in;
+ wire ext_bus_pty_in;
+ wire [7:0] ext_bus_out;
+ wire ext_bus_pty_out;
+
+ assign user_flash_csb = mprj_io[8];
+ assign user_flash_clk = mprj_io[9];
+ assign user_flash_io0 = mprj_io[10];
+ assign mprj_io[11] = user_flash_io1;
+
+ assign checkbits = mprj_io[17:16];
+
+ assign ext_bus_clk = mprj_io[18];
+ assign ext_bus_out[7:0] = mprj_io[26:19];
+ assign ext_bus_pty_out = mprj_io[27];
+ assign mprj_io[35:28] = ext_bus_in[7:0];
+ assign mprj_io[36] = ext_bus_pty_in;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // 50 MHz clock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("external_bus_minimal.vcd");
+ $dumpvars(0, external_bus_minimal_tb);
+
+ $display("Microwatt external bus minimal test");
+
+ repeat (1000000) begin
+ @(posedge clock);
+ end
+
+ $display("Timeout, test failed");
+ $fatal;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ initial begin
+ wait(checkbits == 2'h1);
+ $display("Management engine started");
+
+ wait(checkbits == 2'h2);
+ $display("Microwatt alive!");
+
+ // Wait for Microwatt to respond with success
+ wait(checkbits == 2'h3);
+ $display("Success!");
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mgmt_engine.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ spiflash #(
+ .FILENAME("microwatt.hex")
+ ) spiflash_microwatt (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ external_bus_tb external_bus_tb (
+ .clk(ext_bus_clk),
+ .ext_bus_in(ext_bus_out),
+ .ext_bus_pty_in(ext_bus_pty_out),
+ .ext_bus_out(ext_bus_in),
+ .ext_bus_pty_out(ext_bus_pty_in)
+ );
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/mgmt_engine.c b/verilog/dv/caravel/microwatt/external_bus_minimal/mgmt_engine.c
new file mode 100644
index 0000000..97203bc
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/mgmt_engine.c
@@ -0,0 +1,30 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+// --------------------------------------------------------
+
+void main(void)
+{
+ mgmt_engine_io_setup(false, true);
+
+ // Take microwatt out of reset
+ reg_la2_data &= ~0x00000002;
+
+ while ((reg_la0_data != LA_MICROWATT_START) && (reg_la0_data != LA_MICROWATT_SUCCESS))
+ /* Do Nothing */ ;
+
+ // Signal to TB that microwatt is alive
+ reg_mprj_datal = GPIO1_MICROWATT_START;
+
+ while (reg_la0_data != LA_MICROWATT_SUCCESS)
+ /* Do Nothing */ ;
+
+ // Signal success to the TB
+ reg_mprj_datal = GPIO1_SUCCESS;
+
+ while (1)
+ /* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/microwatt.c b/verilog/dv/caravel/microwatt/external_bus_minimal/microwatt.c
new file mode 100644
index 0000000..ca28e1a
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/microwatt.c
@@ -0,0 +1,25 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+
+#define EXT_BUS_OFFSET 0x40000000
+
+int main(void)
+{
+ uint64_t *p = (uint64_t *)EXT_BUS_OFFSET;
+
+ microwatt_alive();
+
+ __asm__ __volatile__("");
+ *p = 0x5A5A5A5A5A5A5A5A;
+ __asm__ __volatile__("");
+ *p = 0x0f0f0f0f0f0f0f0f;
+ __asm__ __volatile__("");
+ *p = 0xACEACEACEACEACEA;
+ __asm__ __volatile__("");
+
+ microwatt_success();
+
+ while (1)
+ /* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/include/console.h b/verilog/dv/caravel/microwatt/include/console.h
new file mode 100644
index 0000000..e49d569
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/console.h
@@ -0,0 +1,12 @@
+#include <stddef.h>
+#include <stdbool.h>
+
+void console_init(void);
+void console_set_irq_en(bool rx_irq, bool tx_irq);
+int getchar(void);
+int putchar(int c);
+int puts(const char *str);
+
+#ifndef __USE_LIBC
+size_t strlen(const char *s);
+#endif
diff --git a/verilog/dv/caravel/microwatt/include/io.h b/verilog/dv/caravel/microwatt/include/io.h
new file mode 100644
index 0000000..d148046
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/io.h
@@ -0,0 +1,55 @@
+#ifndef __IO_H
+#define __IO_H
+
+#include <stdint.h>
+
+static inline uint8_t readb(unsigned long addr)
+{
+ uint8_t val;
+ __asm__ volatile("sync; lbzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+ return val;
+}
+
+static inline uint16_t readw(unsigned long addr)
+{
+ uint16_t val;
+ __asm__ volatile("sync; lhzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+ return val;
+}
+
+static inline uint32_t readl(unsigned long addr)
+{
+ uint32_t val;
+ __asm__ volatile("sync; lwzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+ return val;
+}
+
+static inline uint64_t readq(unsigned long addr)
+{
+ uint64_t val;
+ __asm__ volatile("sync; ldcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+ return val;
+}
+
+static inline void writeb(uint8_t val, unsigned long addr)
+{
+ __asm__ volatile("sync; stbcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void writew(uint16_t val, unsigned long addr)
+{
+ __asm__ volatile("sync; sthcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void writel(uint32_t val, unsigned long addr)
+{
+ __asm__ volatile("sync; stwcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void writeq(uint64_t val, unsigned long addr)
+{
+ __asm__ volatile("sync; stdcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+#endif /* __IO_H */
+
diff --git a/verilog/dv/caravel/microwatt/include/mgmt_engine_util.h b/verilog/dv/caravel/microwatt/include/mgmt_engine_util.h
new file mode 100644
index 0000000..25730a2
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/mgmt_engine_util.h
@@ -0,0 +1,84 @@
+#include <stdbool.h>
+
+#include "../../defs.h"
+
+static void inline mgmt_engine_io_setup(bool jtag, bool external_bus)
+{
+ // Set LA[65] as output to act as a reset pin for microwatt and
+ // LA[66] as output to specify reset location (RAM or FLASH)
+ reg_la2_ena = 0xFFFFFFF9;
+
+ // Put microwatt into reset and tell it to fetch from flash
+ reg_la2_data = 0x00000002 | 0x00000004;
+
+ // Set up the housekeeping SPI to be connected internally so
+ // that external pin changes don't affect it.
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Communicate status with test case over GPIO 7 and 37
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Signal to the tb that we are alive
+ reg_mprj_datal = GPIO1_MGMT_ENGINE_START;
+
+ // Configure UART
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+
+ // 7 unused
+
+ // Configure SPI
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; // CSB
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; // SCK
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // IO0/MOSI
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // IO1/MISO
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // IO2
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // IO3
+
+ // Configure JTAG
+ if (jtag) {
+ // Overlaps our testbench status bits
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; // TDO
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_PULLDOWN; // TMS
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_PULLDOWN; // TCK
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_PULLDOWN; // TDI
+ }
+
+ // Configure external bus
+ if (external_bus) {
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ }
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+ // 37 unused
+
+ // Now, apply the configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1)
+ /* Do Nothing */;
+
+ // Configure LA bits 0-31 as inputs from Microwatt
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+
+ // Configure LA bits 63-32 as outputs from Microwatt
+ reg_la1_ena = 0x00000000; // [63:32]
+}
diff --git a/verilog/dv/caravel/microwatt/include/microwatt_soc.h b/verilog/dv/caravel/microwatt/include/microwatt_soc.h
new file mode 100644
index 0000000..a224d74
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/microwatt_soc.h
@@ -0,0 +1,155 @@
+#ifndef __MICROWATT_SOC_H
+#define __MICROWATT_SOC_H
+
+/*
+ * Microwatt SoC memory map
+ */
+
+#define MEMORY_BASE 0x00000000 /* "Main" memory alias, either BRAM or DRAM */
+#define DRAM_BASE 0x40000000 /* DRAM if present */
+#define BRAM_BASE 0x80000000 /* Internal BRAM */
+
+#define SYSCON_BASE 0xc0000000 /* System control regs */
+#define UART_BASE 0xc0002000 /* UART */
+#define XICS_ICP_BASE 0xc0004000 /* Interrupt controller */
+#define XICS_ICS_BASE 0xc0005000 /* Interrupt controller */
+#define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */
+#define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */
+#define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */
+#define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */
+#define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */
+#define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */
+
+/*
+ * Interrupt numbers
+ */
+#define IRQ_UART0 0
+#define IRQ_ETHERNET 1
+
+/*
+ * Register definitions for the syscon registers
+ */
+
+#define SYS_REG_SIGNATURE 0x00
+#define SYS_REG_INFO 0x08
+#define SYS_REG_INFO_HAS_UART (1ull << 0)
+#define SYS_REG_INFO_HAS_DRAM (1ull << 1)
+#define SYS_REG_INFO_HAS_BRAM (1ull << 2)
+#define SYS_REG_INFO_HAS_SPI_FLASH (1ull << 3)
+#define SYS_REG_INFO_HAS_LITEETH (1ull << 4)
+#define SYS_REG_INFO_HAS_LARGE_SYSCON (1ull << 5)
+#define SYS_REG_INFO_HAS_UART1 (1ull << 6)
+#define SYS_REG_INFO_HAS_ARTB (1ull << 7)
+#define SYS_REG_BRAMINFO 0x10
+#define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull
+#define SYS_REG_DRAMINFO 0x18
+#define SYS_REG_DRAMINFO_SIZE_MASK 0xfffffffffffffull
+#define SYS_REG_CLKINFO 0x20
+#define SYS_REG_CLKINFO_FREQ_MASK 0xffffffffffull
+#define SYS_REG_CTRL 0x28
+#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0)
+#define SYS_REG_CTRL_CORE_RESET (1ull << 1)
+#define SYS_REG_CTRL_SOC_RESET (1ull << 2)
+#define SYS_REG_DRAMINITINFO 0x30
+#define SYS_REG_SPI_INFO 0x38
+#define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff
+#define SYS_REG_UART0_INFO 0x40
+#define SYS_REG_UART1_INFO 0x48
+#define SYS_REG_UART_IS_16550 (1ull << 32)
+
+
+/*
+ * Register definitions for the potato UART
+ */
+#define POTATO_CONSOLE_TX 0x00
+#define POTATO_CONSOLE_RX 0x08
+#define POTATO_CONSOLE_STATUS 0x10
+#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01
+#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02
+#define POTATO_CONSOLE_STATUS_RX_FULL 0x04
+#define POTATO_CONSOLE_STATUS_TX_FULL 0x08
+#define POTATO_CONSOLE_CLOCK_DIV 0x18
+#define POTATO_CONSOLE_IRQ_EN 0x20
+#define POTATO_CONSOLE_IRQ_RX 0x01
+#define POTATO_CONSOLE_IRQ_TX 0x02
+
+/*
+ * Register definitionss for our standard (16550 style) UART
+ */
+#define UART_REG_RX 0x00
+#define UART_REG_TX 0x00
+#define UART_REG_DLL 0x00
+#define UART_REG_IER 0x04
+#define UART_REG_IER_RDI 0x01
+#define UART_REG_IER_THRI 0x02
+#define UART_REG_IER_RLSI 0x04
+#define UART_REG_IER_MSI 0x08
+#define UART_REG_DLM 0x04
+#define UART_REG_IIR 0x08
+#define UART_REG_FCR 0x08
+#define UART_REG_FCR_EN_FIFO 0x01
+#define UART_REG_FCR_CLR_RCVR 0x02
+#define UART_REG_FCR_CLR_XMIT 0x04
+#define UART_REG_FCR_TRIG1 0x00
+#define UART_REG_FCR_TRIG4 0x40
+#define UART_REG_FCR_TRIG8 0x80
+#define UART_REG_FCR_TRIG14 0xc0
+#define UART_REG_LCR 0x0c
+#define UART_REG_LCR_5BIT 0x00
+#define UART_REG_LCR_6BIT 0x01
+#define UART_REG_LCR_7BIT 0x02
+#define UART_REG_LCR_8BIT 0x03
+#define UART_REG_LCR_STOP 0x04
+#define UART_REG_LCR_PAR 0x08
+#define UART_REG_LCR_EVEN_PAR 0x10
+#define UART_REG_LCR_STIC_PAR 0x20
+#define UART_REG_LCR_BREAK 0x40
+#define UART_REG_LCR_DLAB 0x80
+#define UART_REG_MCR 0x10
+#define UART_REG_MCR_DTR 0x01
+#define UART_REG_MCR_RTS 0x02
+#define UART_REG_MCR_OUT1 0x04
+#define UART_REG_MCR_OUT2 0x08
+#define UART_REG_MCR_LOOP 0x10
+#define UART_REG_LSR 0x14
+#define UART_REG_LSR_DR 0x01
+#define UART_REG_LSR_OE 0x02
+#define UART_REG_LSR_PE 0x04
+#define UART_REG_LSR_FE 0x08
+#define UART_REG_LSR_BI 0x10
+#define UART_REG_LSR_THRE 0x20
+#define UART_REG_LSR_TEMT 0x40
+#define UART_REG_LSR_FIFOE 0x80
+#define UART_REG_MSR 0x18
+#define UART_REG_SCR 0x1c
+
+
+/*
+ * Register definitions for the SPI controller
+ */
+#define SPI_REG_DATA 0x00 /* Byte access: single wire transfer */
+#define SPI_REG_DATA_DUAL 0x01 /* Byte access: dual wire transfer */
+#define SPI_REG_DATA_QUAD 0x02 /* Byte access: quad wire transfer */
+#define SPI_REG_CTRL 0x04 /* Reset and manual mode control */
+#define SPI_REG_CTRL_RESET 0x01 /* reset all registers */
+#define SPI_REG_CTRL_MANUAL_CS 0x02 /* assert CS, enable manual mode */
+#define SPI_REG_CTRL_CKDIV_SHIFT 8 /* clock div */
+#define SPI_REG_CTRL_CKDIV_MASK (0xff << SPI_REG_CTRL_CKDIV_SHIFT)
+#define SPI_REG_AUTO_CFG 0x08 /* Automatic map configuration */
+#define SPI_REG_AUTO_CFG_CMD_SHIFT 0 /* Command to use for reads */
+#define SPI_REG_AUTO_CFG_CMD_MASK (0xff << SPI_REG_AUTO_CFG_CMD_SHIFT)
+#define SPI_REG_AUTO_CFG_DUMMIES_SHIFT 8 /* # dummy cycles */
+#define SPI_REG_AUTO_CFG_DUMMIES_MASK (0x7 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT)
+#define SPI_REG_AUTO_CFG_MODE_SHIFT 11 /* SPI wire mode */
+#define SPI_REG_AUTO_CFG_MODE_MASK (0x3 << SPI_REG_AUTO_CFG_MODE_SHIFT)
+#define SPI_REG_AUT_CFG_MODE_SINGLE (0 << 11)
+#define SPI_REG_AUT_CFG_MODE_DUAL (2 << 11)
+#define SPI_REG_AUT_CFG_MODE_QUAD (3 << 11)
+#define SPI_REG_AUTO_CFG_ADDR4 (1u << 13) /* 3 or 4 addr bytes */
+#define SPI_REG_AUTO_CFG_CKDIV_SHIFT 16 /* clock div */
+#define SPI_REG_AUTO_CFG_CKDIV_MASK (0xff << SPI_REG_AUTO_CFG_CKDIV_SHIFT)
+#define SPI_REG_AUTO_CFG_CSTOUT_SHIFT 24 /* CS timeout */
+#define SPI_REG_AUTO_CFG_CSTOUT_MASK (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
+
+
+#endif /* __MICROWATT_SOC_H */
diff --git a/verilog/dv/caravel/microwatt/include/microwatt_util.h b/verilog/dv/caravel/microwatt/include/microwatt_util.h
new file mode 100644
index 0000000..cd10a8c
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/microwatt_util.h
@@ -0,0 +1,34 @@
+#ifndef __MICROWATT_UTIL_H
+#define __MICROWATT_UTIL_H
+
+#include "io.h"
+
+#define LA_REG 0xc8020000
+
+#define LA_MICROWATT_START 0xbadc0ffe
+#define LA_MICROWATT_SUCCESS 0x0ddf00d5
+#define LA_MICROWATT_FAILURE 0x71077345
+
+#define GPIO1_MGMT_ENGINE_START 0x00010000
+#define GPIO1_MICROWATT_START 0x00020000
+#define GPIO1_SUCCESS 0x00030000
+#define GPIO1_FAILURE 0x00000000
+
+#ifdef __powerpc64__
+static inline void microwatt_alive(void)
+{
+ writel(LA_MICROWATT_START, LA_REG);
+}
+
+static inline void microwatt_success(void)
+{
+ writel(LA_MICROWATT_SUCCESS, LA_REG);
+}
+
+static inline void microwatt_failure(void)
+{
+ writel(LA_MICROWATT_FAILURE, LA_REG);
+}
+#endif
+
+#endif
diff --git a/verilog/dv/caravel/microwatt/lib/console.c b/verilog/dv/caravel/microwatt/lib/console.c
new file mode 100644
index 0000000..29bd749
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/lib/console.c
@@ -0,0 +1,131 @@
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "console.h"
+#include "microwatt_soc.h"
+#include "io.h"
+
+#define UART_BAUDS 115200
+
+/*
+ * Core UART functions to implement for a port
+ */
+
+static uint64_t uart_base;
+
+static unsigned long uart_divisor(unsigned long uart_freq, unsigned long bauds)
+{
+ return uart_freq / (bauds * 16);
+}
+
+static bool std_uart_rx_empty(void)
+{
+ return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_DR);
+}
+
+static uint8_t std_uart_read(void)
+{
+ return readb(uart_base + UART_REG_RX);
+}
+
+static bool std_uart_tx_full(void)
+{
+ return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_THRE);
+}
+
+static void std_uart_write(uint8_t c)
+{
+ writeb(c, uart_base + UART_REG_TX);
+}
+
+static void std_uart_set_irq_en(bool rx_irq, bool tx_irq)
+{
+ uint8_t ier = 0;
+
+ if (tx_irq)
+ ier |= UART_REG_IER_THRI;
+ if (rx_irq)
+ ier |= UART_REG_IER_RDI;
+ writeb(ier, uart_base + UART_REG_IER);
+}
+
+static void std_uart_init(uint64_t uart_freq)
+{
+ unsigned long div = uart_divisor(uart_freq, UART_BAUDS);
+
+ writeb(UART_REG_LCR_DLAB, uart_base + UART_REG_LCR);
+ writeb(div & 0xff, uart_base + UART_REG_DLL);
+ writeb(div >> 8, uart_base + UART_REG_DLM);
+ writeb(UART_REG_LCR_8BIT, uart_base + UART_REG_LCR);
+ writeb(UART_REG_MCR_DTR |
+ UART_REG_MCR_RTS, uart_base + UART_REG_MCR);
+ writeb(UART_REG_FCR_EN_FIFO |
+ UART_REG_FCR_CLR_RCVR |
+ UART_REG_FCR_CLR_XMIT, uart_base + UART_REG_FCR);
+}
+
+int getchar(void)
+{
+ while (std_uart_rx_empty())
+ /* Do nothing */ ;
+ return std_uart_read();
+}
+
+int putchar(int c)
+{
+ while(std_uart_tx_full())
+ /* Do Nothing */;
+ std_uart_write(c);
+ return c;
+}
+
+int puts(const char *str)
+{
+ unsigned int i;
+
+ for (i = 0; *str; i++) {
+ char c = *(str++);
+ if (c == 10)
+ putchar(13);
+ putchar(c);
+ }
+ return 0;
+}
+
+#ifndef __USE_LIBC
+size_t strlen(const char *s)
+{
+ size_t len = 0;
+
+ while (*s++)
+ len++;
+
+ return len;
+}
+#endif
+
+void console_init(void)
+{
+ uint64_t sys_info;
+ uint64_t proc_freq;
+ uint64_t uart_info = 0;
+ uint64_t uart_freq = 0;
+
+ proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
+ sys_info = readq(SYSCON_BASE + SYS_REG_INFO);
+
+ if (sys_info & SYS_REG_INFO_HAS_LARGE_SYSCON) {
+ uart_info = readq(SYSCON_BASE + SYS_REG_UART0_INFO);
+ uart_freq = uart_info & 0xffffffff;
+ }
+ if (uart_freq == 0)
+ uart_freq = proc_freq;
+
+ uart_base = UART_BASE;
+ std_uart_init(proc_freq);
+}
+
+void console_set_irq_en(bool rx_irq, bool tx_irq)
+{
+ std_uart_set_irq_en(rx_irq, tx_irq);
+}
diff --git a/verilog/dv/caravel/microwatt/lib/head.S b/verilog/dv/caravel/microwatt/lib/head.S
new file mode 100644
index 0000000..029e4be
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/lib/head.S
@@ -0,0 +1,59 @@
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define LA_REG 0xc8020000
+#define FLASH_AUTO_CFG_REG 0xc0006008
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e) \
+ lis r,(e)@highest; \
+ ori r,r,(e)@higher; \
+ rldicr r,r, 32, 31; \
+ oris r,r, (e)@h; \
+ ori r,r, (e)@l;
+
+ .section ".head","ax"
+ .global _start
+_start:
+ // Set SPI flash divider to 1
+ LOAD_IMM64(3, FLASH_AUTO_CFG_REG)
+ lwzcix %r5,0,%r3
+ lis %r0,0xF
+ andc %r5,%r5,%r0
+ lis %r4,0x1
+ or %r5,%r5,%r4
+ stwcix %r5,0,%r3
+
+ // Zero BSS
+ LOAD_IMM64(%r10,__bss_start)
+ LOAD_IMM64(%r11,__bss_end)
+ subf %r11,%r10,%r11
+ addi %r11,%r11,63
+ srdi. %r11,%r11,6
+ beq 2f
+ mtctr %r11
+1: dcbz 0,%r10
+ addi %r10,%r10,64
+ bdnz 1b
+
+2: LOAD_IMM64(%r1,__stack_top)
+ li %r0,0
+ stdu %r0,-16(%r1)
+ LOAD_IMM64(%r12, main)
+ mtctr %r12
+ bctrl
+ attn // terminate on exit
+ b .
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/Makefile b/verilog/dv/caravel/microwatt/logic_analyzer/Makefile
new file mode 100644
index 0000000..407840d
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = logic_analyzer
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s lfsr32.c
+ $(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s lfsr32.c $<
+
+mgmt_engine.hex: mgmt_engine.elf
+ $(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds lfsr32.c
+ $(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S lfsr32.c
+
+microwatt.hex: microwatt.elf
+ $(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@F000/@0000/g' $@
+
+clean:
+ rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.c b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.c
new file mode 100644
index 0000000..5f78425
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.c
@@ -0,0 +1,15 @@
+#include "lfsr32.h"
+#include <stdint.h>
+
+#define LFSR_32 ((1 << (32-1)) | (1 << (22-1)) | (1 << (2-1)) | (1 << (1-1)))
+
+uint32_t lfsr32(uint32_t prev)
+{
+ uint32_t lsb = prev & 1;
+
+ prev >>= 1;
+ if (lsb == 1)
+ prev ^= LFSR_32;
+
+ return prev;
+}
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.h b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.h
new file mode 100644
index 0000000..2679a78
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.h
@@ -0,0 +1,10 @@
+#ifndef __LFSR32_H
+#define __LFSR32_H
+
+#include <stdint.h>
+
+#define LFSR32_INIT 0x73983355
+
+uint32_t lfsr32(uint32_t prev);
+
+#endif
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/logic_analyzer_tb.v b/verilog/dv/caravel/microwatt/logic_analyzer/logic_analyzer_tb.v
new file mode 100644
index 0000000..77393c0
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/logic_analyzer_tb.v
@@ -0,0 +1,168 @@
+`default_nettype none
+/*
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ * Copyright (C) 2020 Anton Blanchard <anton@linux.ibm.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module logic_analyzer_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire user_flash_csb;
+ wire user_flash_clk;
+ inout user_flash_io0;
+ inout user_flash_io1;
+
+ assign user_flash_csb = mprj_io[8];
+ assign user_flash_clk = mprj_io[9];
+ assign user_flash_io0 = mprj_io[10];
+ assign mprj_io[11] = user_flash_io1;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ assign checkbits = mprj_io[17:16];
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ // 50 MHz clock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("logic_analyzer.vcd");
+ $dumpvars(0, logic_analyzer_tb);
+
+ $display("Microwatt logic analyzer test");
+
+ // Set the timeout at around 10x what the test should finish
+ // in
+ repeat (1000000) begin
+ @(posedge clock);
+ end
+
+ $display("Timeout, test failed");
+ $fatal;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ initial begin
+ wait(checkbits == 2'h1);
+ $display("Management engine started");
+
+ wait(checkbits == 2'h2);
+ $display("Microwatt alive!");
+
+ wait(checkbits == 2'h3);
+ $display("Success!");
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mgmt_engine.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ spiflash #(
+ .FILENAME("microwatt.hex")
+ ) spiflash_microwatt (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/mgmt_engine.c b/verilog/dv/caravel/microwatt/logic_analyzer/mgmt_engine.c
new file mode 100644
index 0000000..a8ec0ce
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/mgmt_engine.c
@@ -0,0 +1,44 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+#include "lfsr32.h"
+
+// --------------------------------------------------------
+
+void main(void)
+{
+ unsigned long lfsr = LFSR32_INIT;
+
+ mgmt_engine_io_setup(false, true);
+
+ // Take microwatt out of reset
+ reg_la2_data &= ~0x00000002;
+
+ while (reg_la0_data != LA_MICROWATT_START)
+ /* Do Nothing */ ;
+
+ // Signal to TB that microwatt is alive
+ reg_mprj_datal = GPIO1_MICROWATT_START;
+
+ for (unsigned long i = 0; i < 10; i++) {
+ // Send next LFSR in the sequence to Microwatt
+ reg_la1_data = lfsr;
+
+ lfsr = lfsr32(lfsr);
+
+ // Wait for next LFSR in the sequence from Microwatt
+ while (reg_la0_data != lfsr)
+ /* Do Nothing */ ;
+
+ lfsr = lfsr32(lfsr);
+ }
+
+ // Signal success to the TB
+ reg_mprj_datal = GPIO1_SUCCESS;
+
+ while (1)
+ /* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/microwatt.c b/verilog/dv/caravel/microwatt/logic_analyzer/microwatt.c
new file mode 100644
index 0000000..18be89b
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/microwatt.c
@@ -0,0 +1,26 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+#include "lfsr32.h"
+
+#define LA_OFFSET 0xc8020000
+
+int main(void)
+{
+ uint32_t lfsr = LFSR32_INIT;
+
+ microwatt_alive();
+
+ while (1) {
+ // Wait for next LFSR in the sequence from Microwatt
+ while (readl(LA_OFFSET) != lfsr)
+ /* Do Nothing */ ;
+
+ lfsr = lfsr32(lfsr);
+
+ // Send next LFSR in the sequence to Microwatt
+ writel(lfsr, LA_OFFSET);
+
+ lfsr = lfsr32(lfsr);
+ }
+}
diff --git a/verilog/dv/caravel/microwatt/memory_test/Makefile b/verilog/dv/caravel/microwatt/memory_test/Makefile
new file mode 100644
index 0000000..4959234
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = memory_test
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ $(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+ $(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds hash.h
+ $(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S
+
+microwatt.hex: microwatt.elf
+ $(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@F000/@0000/g' $@
+
+clean:
+ rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/memory_test/hash.h b/verilog/dv/caravel/microwatt/memory_test/hash.h
new file mode 100644
index 0000000..88c3d98
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/hash.h
@@ -0,0 +1,10 @@
+#ifndef __HASH_H
+#define __HASH_H
+
+#define GOLDEN_RATIO_64 0x61C8864680B583EBull
+
+static inline uint64_t hash_64(uint64_t val, uint32_t bits)
+{
+ return val * GOLDEN_RATIO_64 >> (64 - bits);
+}
+#endif
diff --git a/verilog/dv/caravel/microwatt/memory_test/memory_test_tb.v b/verilog/dv/caravel/microwatt/memory_test/memory_test_tb.v
new file mode 100644
index 0000000..67abecc
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/memory_test_tb.v
@@ -0,0 +1,185 @@
+`default_nettype none
+/*
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ * Copyright (C) 2020 Anton Blanchard <anton@linux.ibm.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart_modified.v"
+
+module memory_test;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [1:0] checkbits;
+ wire uart_tx;
+ wire user_flash_csb;
+ wire user_flash_clk;
+ inout user_flash_io0;
+ inout user_flash_io1;
+ inout user_flash_io2;
+ inout user_flash_io3;
+
+ assign user_flash_csb = mprj_io[8];
+ assign user_flash_clk = mprj_io[9];
+
+ // Without output enables, how can we hook up bidirectional pins?
+ assign user_flash_io0 = mprj_io[10];
+ assign mprj_io[11] = user_flash_io1;
+ assign user_flash_io2 = mprj_io[12];
+ assign user_flash_io3 = mprj_io[13];
+
+ assign checkbits = mprj_io[17:16];
+
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = 1'b1;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // 50 MHz clock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("memory_test.vcd");
+ $dumpvars(0, memory_test);
+
+ $display("Microwatt memory test");
+
+ repeat (500000) @(posedge clock);
+ $display("Timeout");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ wait(checkbits == 2'h1);
+ $display("Management engine started");
+
+ wait(checkbits == 2'h2);
+ $display("Microwatt alive!");
+
+ wait(checkbits != 2'h2);
+
+ if(checkbits == 2'h0) begin
+ $display("Fail");
+ $finish;
+ end
+
+ if(checkbits == 2'h3) begin
+ $display("Success");
+ $finish;
+ end
+
+ $display("Unknown Failure %x", checkbits);
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mgmt_engine.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ spiflash #(
+ .FILENAME("microwatt.hex")
+ ) spiflash_microwatt (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(user_flash_io2),
+ .io3(user_flash_io3)
+ );
+
+ tbuart_modified #(
+ .baud_rate(115200)
+ ) tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/memory_test/mgmt_engine.c b/verilog/dv/caravel/microwatt/memory_test/mgmt_engine.c
new file mode 100644
index 0000000..0711a5d
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/mgmt_engine.c
@@ -0,0 +1,39 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+// --------------------------------------------------------
+
+void main(void)
+{
+ mgmt_engine_io_setup(false, true);
+
+ // Take microwatt out of reset
+ reg_la2_data &= ~0x00000002;
+
+ while (reg_la0_data != LA_MICROWATT_START)
+ /* Do Nothing */ ;
+
+ // Signal to TB that microwatt is alive
+ reg_mprj_datal = GPIO1_MICROWATT_START;
+
+ while (1) {
+ if (reg_la0_data == LA_MICROWATT_SUCCESS) {
+ // Signal success to the TB
+ reg_mprj_datal = GPIO1_SUCCESS;
+ goto out;
+ }
+
+ if (reg_la0_data == LA_MICROWATT_FAILURE) {
+ // Signal failure to the TB
+ reg_mprj_datal = GPIO1_FAILURE;
+ goto out;
+ }
+ }
+
+out:
+ while (1)
+ /* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/memory_test/microwatt.c b/verilog/dv/caravel/microwatt/memory_test/microwatt.c
new file mode 100644
index 0000000..0fce0fe
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/microwatt.c
@@ -0,0 +1,53 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+#include "console.h"
+#include "hash.h"
+
+static void print_hex(unsigned long val)
+{
+ int i, x;
+
+ for (i = 60; i >= 0; i -= 4) {
+ x = (val >> i) & 0xf;
+ if (x >= 10)
+ putchar(x + 'a' - 10);
+ else
+ putchar(x + '0');
+ }
+}
+
+int main(void)
+{
+ console_init();
+ microwatt_alive();
+
+ // gcc will optimise away a NULL pointer access, so start at offset 1
+ for (unsigned long i = 1; i < 4096; i += 8)
+ *(unsigned long *)i = hash_64(i, 64);
+
+ for (unsigned long i = 1; i < 4096; i+=8) {
+ unsigned long exp;
+ unsigned long got;
+
+ exp = hash_64(i, 64);
+ got = *(unsigned long *)i;
+
+ if (exp != got) {
+ print_hex(exp);
+ putchar(' ');
+ print_hex(got);
+
+ /* Signal success to management engine */
+ microwatt_failure();
+ goto out;
+ }
+ }
+
+ /* Signal success to management engine */
+ microwatt_success();
+
+out:
+ while (1)
+ /* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/memory_test/tbuart_modified.v b/verilog/dv/caravel/microwatt/memory_test/tbuart_modified.v
new file mode 100644
index 0000000..ad9b8f9
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/tbuart_modified.v
@@ -0,0 +1,83 @@
+`default_nettype none
+/*
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud */
+/* and accepting ASCII characters for display. */
+
+/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */
+/* should be possible on a testing system to interface to the UART */
+/* pins on a Raspberry Pi, also running at 3.3V. */
+
+module tbuart_modified # (
+ parameter baud_rate = 115200
+) (
+ input ser_rx
+);
+ reg [3:0] recv_state;
+ reg [2:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+
+ reg clk;
+
+ initial begin
+ clk <= 1'b0;
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ end
+
+ // Our simulation is in nanosecond steps and we want 5 clocks per bit,
+ // ie 10 clock transitions
+ always #(1000000000/baud_rate/10) clk <= (clk === 1'b0);
+
+ always @(posedge clk) begin
+ recv_divcnt <= recv_divcnt + 1;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > 3'd3) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_state <= 0;
+ $write("%c", recv_pattern);
+ $fflush();
+ end
+ end
+ default: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+
+endmodule
diff --git a/verilog/dv/caravel/microwatt/microwatt-nia/Cargo.toml b/verilog/dv/caravel/microwatt/microwatt-nia/Cargo.toml
new file mode 100644
index 0000000..3bf1207
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt-nia/Cargo.toml
@@ -0,0 +1,8 @@
+[package]
+name = "microwatt-nia"
+version = "0.1.0"
+authors = ["Anton Blanchard <anton@linux.ibm.com>"]
+edition = "2018"
+
+[dependencies]
+vcd = "0.6.1"
diff --git a/verilog/dv/caravel/microwatt/microwatt-nia/README.md b/verilog/dv/caravel/microwatt/microwatt-nia/README.md
new file mode 100644
index 0000000..2b9807c
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt-nia/README.md
@@ -0,0 +1,8 @@
+# microwatt-nia
+
+Parses a caravel-microwatt VCD file and prints all the Microwatt NIAs. It requires
+a rust toolchain to build. To build:
+
+```
+cargo build --release
+```
diff --git a/verilog/dv/caravel/microwatt/microwatt-nia/src/main.rs b/verilog/dv/caravel/microwatt/microwatt-nia/src/main.rs
new file mode 100644
index 0000000..b367ac3
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt-nia/src/main.rs
@@ -0,0 +1,76 @@
+use std::env;
+use std::io::BufReader;
+use std::fs::File;
+use std::io;
+use std::io::ErrorKind::InvalidInput;
+use vcd::{ self, Value, ScopeItem };
+
+fn read_vcd<R: io::Read>(r: &mut R) -> io::Result<()> {
+ let mut parser = vcd::Parser::new(r);
+
+ let header = parser.parse_header()?;
+
+ // Find top level scope
+ let top_scope = match &header.items[0] {
+ ScopeItem::Scope(sc) => sc,
+ x => panic!("Expected Scope, found {:?}", x),
+ };
+
+ let reset = header.find_var(&[&top_scope.identifier[..], "uut", "mprj", "microwatt_0", "ext_rst"])
+ .ok_or_else(|| io::Error::new(InvalidInput, "Could not find microwatt reset"))?.code;
+
+ let nia = header.find_var(&[&top_scope.identifier[..], "uut", "mprj", "microwatt_0", "soc0", "processor", "debug_0", "nia"])
+ .ok_or_else(|| io::Error::new(InvalidInput, "Could not find microwatt nia signal"))?.code;
+
+ let mut nia_val : u64;
+ let mut in_reset = true;
+
+ for command_result in parser {
+ use vcd::Command::*;
+ let command = command_result?;
+ match command {
+ ChangeVector(i, v) if i == nia => {
+ if in_reset == false {
+ nia_val = 0;
+
+ for x in v.iter() {
+ match x {
+ Value::V1 => {
+ nia_val = (nia_val << 1) | 1;
+ }
+ Value::V0 => {
+ nia_val = (nia_val << 1) | 0;
+ }
+ _ => {
+ panic!("NIA is X or Z state");
+ }
+ }
+ }
+
+ println!("{:#018x}", nia_val);
+ }
+ }
+
+ ChangeScalar(i, v) if i == reset => {
+ if v == Value::V0{
+ in_reset = false;
+ }
+ }
+
+ _ => (),
+ }
+ }
+
+ Ok(())
+}
+
+fn main() -> std::io::Result<()> {
+ let filename = env::args().nth(1).expect("No VCD file given");
+ let file = File::open(filename)?;
+ // The VCD parser isn't buffering reads, this speeds things up a bunch
+ let mut reader = BufReader::new(file);
+
+ read_vcd(&mut reader).expect("Failed to parse VCD file");
+
+ Ok(())
+}
diff --git a/verilog/dv/caravel/microwatt/microwatt.lds b/verilog/dv/caravel/microwatt/microwatt.lds
new file mode 100644
index 0000000..e1fb499
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt.lds
@@ -0,0 +1,57 @@
+MEMORY {
+ FLASH(rx) : ORIGIN = 0xf0000000, LENGTH = 0x400000 /* 4MB */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x0400 /* 1024 kB */
+}
+
+SECTIONS
+{
+ . = 0xf0000000;
+ _start = .;
+ .text : {
+ KEEP(*(.head))
+ *(.text)
+ *(.text.*)
+ *(.sfpr)
+ *(.eh_frame)
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(8);
+ _etext = .; /* define a global symbol at end of code */
+ _sidata = _etext; /* This is used by the startup to initialize data */
+ } > FLASH
+
+ .data : AT ( _sidata ) {
+ . = ALIGN(8);
+ _sdata = .;
+ _ram_start = .;
+ . = ALIGN(8);
+ *(.data)
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ . = ALIGN(8);
+ _edata = .;
+ } > RAM
+
+ .bss : {
+ __bss_start = .;
+ *(.dynsbss)
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(.common)
+ *(.bss.*)
+
+ . = . + 0x300;
+ __stack_top = .;
+
+ . = ALIGN(0x80);
+ __bss_end = .;
+ } > RAM
+
+ /DISCARD/ :
+ {
+ *(.note.gnu.build-id)
+ }
+}
diff --git a/verilog/dv/caravel/microwatt/minimal/Makefile b/verilog/dv/caravel/microwatt/minimal/Makefile
new file mode 100644
index 0000000..348256e
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = minimal
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ $(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+ $(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: head.S ../microwatt.lds
+ $(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ head.S
+
+microwatt.hex: microwatt.elf
+ $(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@F000/@0000/g' $@
+
+clean:
+ rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/minimal/head.S b/verilog/dv/caravel/microwatt/minimal/head.S
new file mode 100644
index 0000000..4d1e0c2
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/head.S
@@ -0,0 +1,34 @@
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define LA_REG 0xc8020000
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e) \
+ lis r,(e)@highest; \
+ ori r,r,(e)@higher; \
+ rldicr r,r, 32, 31; \
+ oris r,r, (e)@h; \
+ ori r,r, (e)@l;
+
+ .section ".head","ax"
+ .global _start
+_start:
+ LOAD_IMM64(%r3, LA_REG)
+ LOAD_IMM64(%r4, 0xbadc0ffe)
+ stwcix %r4,0,%r3
+
+1: b 1b
diff --git a/verilog/dv/caravel/microwatt/minimal/mgmt_engine.c b/verilog/dv/caravel/microwatt/minimal/mgmt_engine.c
new file mode 100644
index 0000000..75fd72f
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/mgmt_engine.c
@@ -0,0 +1,22 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+void main(void)
+{
+ mgmt_engine_io_setup(false, true);
+
+ // Take microwatt out of reset
+ reg_la2_data &= ~0x00000002;
+
+ while (reg_la0_data != LA_MICROWATT_START)
+ /* Do Nothing */ ;
+
+ // Signal success to the tb
+ reg_mprj_datal = GPIO1_SUCCESS;
+
+ while (1)
+ /* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/minimal/minimal_tb.v b/verilog/dv/caravel/microwatt/minimal/minimal_tb.v
new file mode 100644
index 0000000..7287d46
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/minimal_tb.v
@@ -0,0 +1,160 @@
+`default_nettype none
+/*
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ * Copyright (C) 2020 Anton Blanchard <anton@linux.ibm.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module minimal;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [1:0] checkbits;
+ wire user_flash_csb;
+ wire user_flash_clk;
+ inout user_flash_io0;
+ inout user_flash_io1;
+
+ assign user_flash_csb = mprj_io[8];
+ assign user_flash_clk = mprj_io[9];
+ assign user_flash_io0 = mprj_io[10];
+ assign mprj_io[11] = user_flash_io1;
+
+ assign checkbits = mprj_io[17:16];
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // 50 MHz clock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("minimal.vcd");
+ $dumpvars(0, minimal);
+
+ $display("Microwatt minimal test");
+
+ // Set the timeout at around 10x what the test should finish
+ // in
+ repeat (200000) begin
+ @(posedge clock);
+ end
+
+ $display("Timeout, test failed");
+ $fatal;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ initial begin
+ wait(checkbits == 2'h1);
+ $display("Management engine started");
+
+ wait(checkbits == 2'h3);
+ $display("Microwatt alive!");
+
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mgmt_engine.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ spiflash #(
+ .FILENAME("microwatt.hex")
+ ) spiflash_microwatt (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/spi_flash/Makefile b/verilog/dv/caravel/microwatt/spi_flash/Makefile
new file mode 100644
index 0000000..379ed04
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/Makefile
@@ -0,0 +1,63 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = spi_flash
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+gen_hash: gen_hash.c
+ $(CC) -O2 -o $@ $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ $(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+ $(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds lfsr32.c
+ $(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S lfsr32.c
+
+microwatt.hex: microwatt.elf gen_hash
+ $(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@F000/@0000/g' $@
+ ./gen_hash >> $@
+
+clean:
+ rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex gen_hash
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/spi_flash/gen_hash.c b/verilog/dv/caravel/microwatt/spi_flash/gen_hash.c
new file mode 100644
index 0000000..34aab46
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/gen_hash.c
@@ -0,0 +1,22 @@
+#include <stdint.h>
+#include <stdio.h>
+#include "hash.h"
+
+#define START_OFFSET 0x2000UL
+#define END_OFFSET (16UL*1024*1024)
+
+int main(void)
+{
+ printf("@%lx\n", START_OFFSET);
+
+ for (uint64_t i = START_OFFSET; i < END_OFFSET; i += 8) {
+ uint64_t val = hash_64(i, 64);
+
+ for (unsigned long j = 0; j < 8; j++) {
+ printf("%02X ", (val >> (j*8) & 0xff));
+ }
+
+ if (i & 0xf)
+ printf("\n");
+ }
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/hash.h b/verilog/dv/caravel/microwatt/spi_flash/hash.h
new file mode 100644
index 0000000..88c3d98
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/hash.h
@@ -0,0 +1,10 @@
+#ifndef __HASH_H
+#define __HASH_H
+
+#define GOLDEN_RATIO_64 0x61C8864680B583EBull
+
+static inline uint64_t hash_64(uint64_t val, uint32_t bits)
+{
+ return val * GOLDEN_RATIO_64 >> (64 - bits);
+}
+#endif
diff --git a/verilog/dv/caravel/microwatt/spi_flash/lfsr32.c b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.c
new file mode 100644
index 0000000..5f78425
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.c
@@ -0,0 +1,15 @@
+#include "lfsr32.h"
+#include <stdint.h>
+
+#define LFSR_32 ((1 << (32-1)) | (1 << (22-1)) | (1 << (2-1)) | (1 << (1-1)))
+
+uint32_t lfsr32(uint32_t prev)
+{
+ uint32_t lsb = prev & 1;
+
+ prev >>= 1;
+ if (lsb == 1)
+ prev ^= LFSR_32;
+
+ return prev;
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/lfsr32.h b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.h
new file mode 100644
index 0000000..2679a78
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.h
@@ -0,0 +1,10 @@
+#ifndef __LFSR32_H
+#define __LFSR32_H
+
+#include <stdint.h>
+
+#define LFSR32_INIT 0x73983355
+
+uint32_t lfsr32(uint32_t prev);
+
+#endif
diff --git a/verilog/dv/caravel/microwatt/spi_flash/mgmt_engine.c b/verilog/dv/caravel/microwatt/spi_flash/mgmt_engine.c
new file mode 100644
index 0000000..ec3f375
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/mgmt_engine.c
@@ -0,0 +1,37 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+void main(void)
+{
+ mgmt_engine_io_setup(false, true);
+
+ // Take microwatt out of reset
+ reg_la2_data &= ~0x00000002;
+
+ while (reg_la0_data != LA_MICROWATT_START)
+ /* Do Nothing */ ;
+
+ // Signal to TB that microwatt is alive
+ reg_mprj_datal = GPIO1_MICROWATT_START;
+
+ while (1) {
+ if (reg_la0_data == LA_MICROWATT_SUCCESS) {
+ // Signal success to the TB
+ reg_mprj_datal = GPIO1_SUCCESS;
+ goto out;
+ }
+
+ if (reg_la0_data == LA_MICROWATT_FAILURE) {
+ // Signal failure to the TB
+ reg_mprj_datal = GPIO1_FAILURE;
+ goto out;
+ }
+ }
+
+out:
+ while (1)
+ /* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/microwatt.c b/verilog/dv/caravel/microwatt/spi_flash/microwatt.c
new file mode 100644
index 0000000..ad2944b
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/microwatt.c
@@ -0,0 +1,67 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+#include "console.h"
+#include "lfsr32.h"
+#include "hash.h"
+
+#define LA_OFFSET 0xc8020000
+
+#define FLASH_BASE 0xf0000000UL
+
+#define FLASH_OFFSET 0x2000
+#define FLASH_SIZE (16L*1024*1024)
+
+static void print_hex(unsigned long val)
+{
+ int i, x;
+
+ for (i = 60; i >= 0; i -= 4) {
+ x = (val >> i) & 0xf;
+ if (x >= 10)
+ putchar(x + 'a' - 10);
+ else
+ putchar(x + '0');
+ }
+}
+
+int main(void)
+{
+ uint32_t lfsr = LFSR32_INIT;
+
+ console_init();
+ microwatt_alive();
+
+ for (unsigned long i = 0; i < 16; i++) {
+ uint32_t o;
+ uint64_t exp;
+ uint64_t got;
+
+ o = lfsr % FLASH_SIZE;
+ // 16B align for now
+ o &= ~15UL;
+ if (o < FLASH_OFFSET)
+ o += FLASH_OFFSET;
+ lfsr = lfsr32(lfsr);
+
+ exp = hash_64(o, 64);
+
+ got = *(uint64_t *)(FLASH_BASE+o);
+ if (exp != got) {
+ print_hex(exp);
+ putchar(' ');
+ print_hex(got);
+ putchar('\n');
+ /* Signal success to management engine */
+ microwatt_failure();
+ goto out;
+ }
+ }
+
+ /* Signal success to management engine */
+ microwatt_success();
+
+out:
+ while (1)
+ /* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/spi_flash_tb.v b/verilog/dv/caravel/microwatt/spi_flash/spi_flash_tb.v
new file mode 100644
index 0000000..0861c93
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/spi_flash_tb.v
@@ -0,0 +1,185 @@
+`default_nettype none
+/*
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ * Copyright (C) 2020 Anton Blanchard <anton@linux.ibm.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart_modified.v"
+
+module spi_flash;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [1:0] checkbits;
+ wire uart_tx;
+ wire user_flash_csb;
+ wire user_flash_clk;
+ inout user_flash_io0;
+ inout user_flash_io1;
+ inout user_flash_io2;
+ inout user_flash_io3;
+
+ assign user_flash_csb = mprj_io[8];
+ assign user_flash_clk = mprj_io[9];
+
+ // Without output enables, how can we hook up bidirectional pins?
+ assign user_flash_io0 = mprj_io[10];
+ assign mprj_io[11] = user_flash_io1;
+ assign user_flash_io2 = mprj_io[12];
+ assign user_flash_io3 = mprj_io[13];
+
+ assign checkbits = mprj_io[17:16];
+
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = 1'b1;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // 50 MHz clock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("spi_flash.vcd");
+ $dumpvars(0, spi_flash);
+
+ $display("Microwatt SPI flash test");
+
+ repeat (1000000) @(posedge clock);
+ $display("Timeout");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ wait(checkbits == 2'h1);
+ $display("Management engine started");
+
+ wait(checkbits == 2'h2);
+ $display("Microwatt alive!");
+
+ wait(checkbits != 2'h2);
+
+ if(checkbits == 2'h0) begin
+ $display("Fail");
+ $finish;
+ end
+
+ if(checkbits == 2'h3) begin
+ $display("Success");
+ $finish;
+ end
+
+ $display("Unknown Failure %x", checkbits);
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mgmt_engine.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ spiflash #(
+ .FILENAME("microwatt.hex")
+ ) spiflash_microwatt (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(user_flash_io2),
+ .io3(user_flash_io3)
+ );
+
+ tbuart_modified #(
+ .baud_rate(115200)
+ ) tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/spi_flash/tbuart_modified.v b/verilog/dv/caravel/microwatt/spi_flash/tbuart_modified.v
new file mode 100644
index 0000000..ad9b8f9
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/tbuart_modified.v
@@ -0,0 +1,83 @@
+`default_nettype none
+/*
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud */
+/* and accepting ASCII characters for display. */
+
+/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */
+/* should be possible on a testing system to interface to the UART */
+/* pins on a Raspberry Pi, also running at 3.3V. */
+
+module tbuart_modified # (
+ parameter baud_rate = 115200
+) (
+ input ser_rx
+);
+ reg [3:0] recv_state;
+ reg [2:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+
+ reg clk;
+
+ initial begin
+ clk <= 1'b0;
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ end
+
+ // Our simulation is in nanosecond steps and we want 5 clocks per bit,
+ // ie 10 clock transitions
+ always #(1000000000/baud_rate/10) clk <= (clk === 1'b0);
+
+ always @(posedge clk) begin
+ recv_divcnt <= recv_divcnt + 1;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > 3'd3) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_state <= 0;
+ $write("%c", recv_pattern);
+ $fflush();
+ end
+ end
+ default: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+
+endmodule
diff --git a/verilog/dv/caravel/microwatt/uart/Makefile b/verilog/dv/caravel/microwatt/uart/Makefile
new file mode 100644
index 0000000..3aee23a
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = uart
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ $(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+ $(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds
+ $(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S
+
+microwatt.hex: microwatt.elf
+ $(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@F000/@0000/g' $@
+
+clean:
+ rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/uart/mgmt_engine.c b/verilog/dv/caravel/microwatt/uart/mgmt_engine.c
new file mode 100644
index 0000000..dcc4596
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/mgmt_engine.c
@@ -0,0 +1,22 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+void main(void)
+{
+ mgmt_engine_io_setup(false, true);
+
+ // Take microwatt out of reset
+ reg_la2_data &= ~0x00000002;
+
+ while (reg_la0_data != LA_MICROWATT_START)
+ /* Do Nothing */ ;
+
+ // Signal to TB that microwatt is alive
+ reg_mprj_datal = GPIO1_MICROWATT_START;
+
+ while (1)
+ /* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/uart/microwatt.c b/verilog/dv/caravel/microwatt/uart/microwatt.c
new file mode 100644
index 0000000..81ad8be
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/microwatt.c
@@ -0,0 +1,19 @@
+#include <stdint.h>
+
+#include "console.h"
+#include "microwatt_util.h"
+
+int main(void)
+{
+ console_init();
+
+ microwatt_alive();
+
+ /* Echo everything we receive back */
+ while (1) {
+ unsigned char c = getchar();
+ putchar(c);
+ if (c == 13) // if CR send LF
+ putchar(10);
+ }
+}
diff --git a/verilog/dv/caravel/microwatt/uart/uart_tb.v b/verilog/dv/caravel/microwatt/uart/uart_tb.v
new file mode 100644
index 0000000..309324a
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/uart_tb.v
@@ -0,0 +1,249 @@
+`default_nettype none
+/*
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ * Copyright (C) 2020 Anton Blanchard <anton@linux.ibm.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module tbuart_expect_seven # (
+ parameter baud_rate = 115200
+) (
+ input ser_rx
+);
+ reg [3:0] recv_state;
+ reg [2:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+
+ reg clk;
+
+ initial begin
+ clk <= 1'b0;
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ end
+
+ // Our simulation is in nanosecond steps and we want 5 clocks per bit,
+ // ie 10 clock transitions
+ always #(1000000000/baud_rate/10) clk <= (clk === 1'b0);
+
+ always @(posedge clk) begin
+ recv_divcnt <= recv_divcnt + 1;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > 3'd3) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_state <= 0;
+ $display("Got %c from Microwatt", recv_pattern);
+ // Expecting 7 back
+ if (recv_pattern == 55) begin
+ $finish;
+ end else begin
+ $fatal;
+ end
+ end
+ end
+ default: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+endmodule
+
+module uart_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg uart_rx;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [1:0] checkbits;
+ wire uart_tx;
+ wire user_flash_csb;
+ wire user_flash_clk;
+ inout user_flash_io0;
+ inout user_flash_io1;
+
+ assign user_flash_csb = mprj_io[8];
+ assign user_flash_clk = mprj_io[9];
+ assign user_flash_io0 = mprj_io[10];
+ assign mprj_io[11] = user_flash_io1;
+
+ assign checkbits = mprj_io[17:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+
+ // 50 MHz clock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("uart.vcd");
+ $dumpvars(0, uart_tb);
+
+ $display("Microwatt UART rx -> tx test");
+
+ repeat (150) begin
+ repeat (10000) @(posedge clock);
+ // Diagnostic. . . interrupts output pattern.
+ end
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ initial begin
+ uart_rx <= 1'b1;
+
+ wait(checkbits == 2'h1);
+ $display("Management engine started");
+
+ wait(checkbits == 2'h2);
+ $display("Microwatt alive!");
+
+ // 115200 = 8680 ns per bit
+ $display("Writing 7 to Microwatt uart");
+ uart_rx <= 1'b0;
+ #8680
+ uart_rx <= 1'b1;
+ #8680
+ uart_rx <= 1'b1;
+ #8680
+ uart_rx <= 1'b1;
+ #8680
+ uart_rx <= 1'b0;
+ #8680
+ uart_rx <= 1'b1;
+ #8680
+ uart_rx <= 1'b1;
+ #8680
+ uart_rx <= 1'b0;
+ #8680
+ uart_rx <= 1'b0;
+ #8680
+ $display("Done. Waiting for Microwatt to send 7 back");
+ uart_rx <= 1'b1;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mgmt_engine.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ spiflash #(
+ .FILENAME("microwatt.hex")
+ ) spiflash_microwatt (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart_expect_seven #(
+ .baud_rate(115200)
+ ) tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
index 29dde43..76969fb 100644
--- a/verilog/dv/caravel/spiflash.v
+++ b/verilog/dv/caravel/spiflash.v
@@ -107,6 +107,7 @@
initial begin
$display("Reading %s", FILENAME);
$readmemh(FILENAME, memory);
+ $display("%s loaded into memory", FILENAME);
end
task spi_action;
diff --git a/verilog/rtl/RAM_512x64.v b/verilog/rtl/RAM_512x64.v
index e019739..6a58b7c 100644
--- a/verilog/rtl/RAM_512x64.v
+++ b/verilog/rtl/RAM_512x64.v
@@ -1,13 +1,7 @@
module RAM_512x64 (
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
`endif
input CLK,
input [7:0] WE,
diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v
index 66e6207..478263b 100644
--- a/verilog/rtl/caravel_netlists.v
+++ b/verilog/rtl/caravel_netlists.v
@@ -48,6 +48,13 @@
`include "gl/mgmt_protect_hv.v"
`include "gl/gpio_control_block.v"
`include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+
+`default_nettype wire
+ `include "gl/icache.v"
+ `include "gl/dcache.v"
+ `include "gl/register_file.v"
+ `include "gl/multiply_4.v"
+ `include "gl/RAM_512x64.v"
`include "gl/user_project_wrapper.v"
`include "gl/caravel.v"
`else
@@ -70,6 +77,12 @@
`include "mgmt_protect_hv.v"
`include "gpio_control_block.v"
`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+ `include "icache.v"
+ `include "dcache.v"
+ `include "register_file.v"
+ `include "multiply_4.v"
+ `include "RAM_512x64.v"
+ `include "microwatt.v"
`include "user_project_wrapper.v"
`include "caravel.v"
`endif
@@ -77,11 +90,6 @@
`include "simple_por.v"
`include "sram_1rw1r_32_256_8_sky130.v"
-/*------------------------------*/
-/* Include user project here */
-/*------------------------------*/
-`include "user_proj_example.v"
-
// `ifdef USE_OPENRAM
// `include "sram_1rw1r_32_256_8_sky130.v"
// `endif
diff --git a/verilog/rtl/dcache.v b/verilog/rtl/dcache.v
new file mode 100644
index 0000000..09d6f52
--- /dev/null
+++ b/verilog/rtl/dcache.v
@@ -0,0 +1,2299 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+module plru_2(clk, rst, acc, acc_en, lru);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ input acc;
+ input acc_en;
+ input clk;
+ output lru;
+ input rst;
+ reg [1:0] tree;
+ assign _0_ = ~ acc;
+ assign _1_ = acc_en ? _0_ : tree[1];
+ assign _2_ = rst ? 1'h0 : tree[0];
+ assign _3_ = rst ? 1'h0 : _1_;
+ always @(posedge clk)
+ tree <= { _3_, _2_ };
+ assign lru = tree[1];
+endmodule
+
+module cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
+ reg [63:0] _00_;
+ wire [127:0] _01_;
+ wire [7:0] _02_;
+ wire [127:0] _03_;
+ wire [7:0] _04_;
+ wire [127:0] _05_;
+ wire [7:0] _06_;
+ wire [127:0] _07_;
+ wire [7:0] _08_;
+ wire [127:0] _09_;
+ wire [7:0] _10_;
+ wire [127:0] _11_;
+ wire [7:0] _12_;
+ wire [127:0] _13_;
+ wire [7:0] _14_;
+ wire [127:0] _15_;
+ wire [7:0] _16_;
+ input clk;
+ input [3:0] rd_addr;
+ output [63:0] rd_data;
+ input rd_en;
+ input [3:0] wr_addr;
+ input [63:0] wr_data;
+ input [7:0] wr_sel;
+ reg [7:0] \$mem$\25511 [15:0];
+ reg [7:0] \$mem$\25512 [15:0];
+ reg [7:0] \$mem$\25513 [15:0];
+ reg [7:0] \$mem$\25514 [15:0];
+ reg [7:0] \$mem$\25515 [15:0];
+ reg [7:0] \$mem$\25516 [15:0];
+ reg [7:0] \$mem$\25517 [15:0];
+ reg [7:0] \$mem$\25518 [15:0];
+ (* ram_style = "block" *)
+ reg [7:0] \25511 [15:0];
+ reg [7:0] _17_;
+ always @(posedge clk) begin
+ if (rd_en) _17_ <= \25511 [rd_addr];
+ if (wr_sel[0]) \25511 [wr_addr] <= wr_data[7:0];
+ end
+ assign _02_ = _17_;
+ (* ram_style = "block" *)
+ reg [7:0] \25512 [15:0];
+ reg [7:0] _18_;
+ always @(posedge clk) begin
+ if (rd_en) _18_ <= \25512 [rd_addr];
+ if (wr_sel[1]) \25512 [wr_addr] <= wr_data[15:8];
+ end
+ assign _04_ = _18_;
+ (* ram_style = "block" *)
+ reg [7:0] \25513 [15:0];
+ reg [7:0] _19_;
+ always @(posedge clk) begin
+ if (rd_en) _19_ <= \25513 [rd_addr];
+ if (wr_sel[2]) \25513 [wr_addr] <= wr_data[23:16];
+ end
+ assign _06_ = _19_;
+ (* ram_style = "block" *)
+ reg [7:0] \25514 [15:0];
+ reg [7:0] _20_;
+ always @(posedge clk) begin
+ if (rd_en) _20_ <= \25514 [rd_addr];
+ if (wr_sel[3]) \25514 [wr_addr] <= wr_data[31:24];
+ end
+ assign _08_ = _20_;
+ (* ram_style = "block" *)
+ reg [7:0] \25515 [15:0];
+ reg [7:0] _21_;
+ always @(posedge clk) begin
+ if (rd_en) _21_ <= \25515 [rd_addr];
+ if (wr_sel[4]) \25515 [wr_addr] <= wr_data[39:32];
+ end
+ assign _10_ = _21_;
+ (* ram_style = "block" *)
+ reg [7:0] \25516 [15:0];
+ reg [7:0] _22_;
+ always @(posedge clk) begin
+ if (rd_en) _22_ <= \25516 [rd_addr];
+ if (wr_sel[5]) \25516 [wr_addr] <= wr_data[47:40];
+ end
+ assign _12_ = _22_;
+ (* ram_style = "block" *)
+ reg [7:0] \25517 [15:0];
+ reg [7:0] _23_;
+ always @(posedge clk) begin
+ if (rd_en) _23_ <= \25517 [rd_addr];
+ if (wr_sel[6]) \25517 [wr_addr] <= wr_data[55:48];
+ end
+ assign _14_ = _23_;
+ (* ram_style = "block" *)
+ reg [7:0] \25518 [15:0];
+ reg [7:0] _24_;
+ always @(posedge clk) begin
+ if (rd_en) _24_ <= \25518 [rd_addr];
+ if (wr_sel[7]) \25518 [wr_addr] <= wr_data[63:56];
+ end
+ assign _16_ = _24_;
+ always @(posedge clk)
+ _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
+ assign rd_data = _00_;
+endmodule
+
+module dcache(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ wire _000_;
+ wire _001_;
+ wire [146:0] _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire [146:0] _006_;
+ wire _007_;
+ wire [146:0] _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire [1:0] _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire [3:0] _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire [3:0] _035_;
+ wire [3:0] _036_;
+ wire [3:0] _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire [2:0] _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire [2:0] _137_;
+ wire [2:0] _138_;
+ wire [2:0] _139_;
+ wire _140_;
+ wire [3:0] _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire [58:0] _151_;
+ wire _152_;
+ wire [57:0] _153_;
+ wire [58:0] _154_;
+ wire _155_;
+ wire [57:0] _156_;
+ wire [63:0] _157_;
+ wire _158_;
+ wire [7:0] _159_;
+ wire [7:0] _160_;
+ wire [7:0] _161_;
+ wire [7:0] _162_;
+ wire [7:0] _163_;
+ wire [7:0] _164_;
+ wire [7:0] _165_;
+ wire [7:0] _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire [63:0] _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire [63:0] _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire [1:0] _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ reg _197_;
+ reg [6:0] _198_;
+ reg _199_;
+ reg [2:0] _200_;
+ wire [7:0] _201_;
+ wire [7:0] _202_;
+ wire [63:0] _203_;
+ wire [63:0] _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire [63:0] _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire [7:0] _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire _233_;
+ wire [135:0] _234_;
+ wire [2:0] _235_;
+ wire _236_;
+ wire _237_;
+ wire _238_;
+ wire _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire _245_;
+ wire _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire [1:0] _250_;
+ wire _251_;
+ wire _252_;
+ wire _253_;
+ wire [2:0] _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire _259_;
+ wire _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire [1:0] _264_;
+ wire _265_;
+ wire _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire _270_;
+ wire [2:0] _271_;
+ wire _272_;
+ wire _273_;
+ wire _274_;
+ wire _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire _279_;
+ wire _280_;
+ wire _281_;
+ wire [2:0] _282_;
+ wire [31:0] _283_;
+ wire _284_;
+ wire _285_;
+ wire [2:0] _286_;
+ wire _287_;
+ wire _288_;
+ wire _289_;
+ wire _290_;
+ wire _291_;
+ wire _292_;
+ wire _293_;
+ wire _294_;
+ wire _295_;
+ wire _296_;
+ wire _297_;
+ wire _298_;
+ wire _299_;
+ wire [8:0] _300_;
+ wire _301_;
+ wire _302_;
+ wire _303_;
+ wire _304_;
+ wire _305_;
+ wire _306_;
+ wire [3:0] _307_;
+ wire [1:0] _308_;
+ wire _309_;
+ wire [2:0] _310_;
+ wire _311_;
+ wire _312_;
+ wire [10:0] _313_;
+ wire _314_;
+ wire _315_;
+ wire [3:0] _316_;
+ wire [7:0] _317_;
+ wire _318_;
+ wire _319_;
+ wire _320_;
+ wire _321_;
+ wire _322_;
+ wire [2:0] _323_;
+ wire [2:0] _324_;
+ wire [2:0] _325_;
+ wire [2:0] _326_;
+ wire _327_;
+ wire [6:0] _328_;
+ wire [71:0] _329_;
+ wire _330_;
+ wire _331_;
+ wire _332_;
+ wire _333_;
+ wire _334_;
+ wire _335_;
+ wire _336_;
+ wire _337_;
+ wire _338_;
+ wire _339_;
+ wire _340_;
+ wire _341_;
+ wire _342_;
+ wire _343_;
+ wire _344_;
+ wire _345_;
+ wire _346_;
+ wire [7:0] _347_;
+ wire _348_;
+ wire _349_;
+ wire _350_;
+ wire _351_;
+ wire _352_;
+ wire _353_;
+ wire _354_;
+ wire [1:0] _355_;
+ wire [1:0] _356_;
+ wire _357_;
+ wire [1:0] _358_;
+ wire _359_;
+ wire _360_;
+ wire _361_;
+ wire _362_;
+ wire _363_;
+ wire _364_;
+ wire _365_;
+ wire _366_;
+ wire [10:0] _367_;
+ wire _368_;
+ wire [1:0] _369_;
+ wire _370_;
+ wire _371_;
+ wire _372_;
+ wire [3:0] _373_;
+ wire _374_;
+ wire _375_;
+ wire _376_;
+ wire _377_;
+ wire _378_;
+ wire _379_;
+ wire [8:0] _380_;
+ wire [1:0] _381_;
+ wire _382_;
+ wire _383_;
+ wire _384_;
+ wire _385_;
+ wire [6:0] _386_;
+ wire [24:0] _387_;
+ wire [63:0] _388_;
+ wire [7:0] _389_;
+ wire _390_;
+ wire _391_;
+ wire _392_;
+ wire [48:0] _393_;
+ wire _394_;
+ wire [3:0] _395_;
+ wire _396_;
+ wire [2:0] _397_;
+ wire _398_;
+ wire _399_;
+ wire _400_;
+ wire _401_;
+ wire _402_;
+ wire _403_;
+ wire _404_;
+ wire _405_;
+ wire [2:0] _406_;
+ wire _407_;
+ wire _408_;
+ wire _409_;
+ wire _410_;
+ wire _411_;
+ wire _412_;
+ wire [133:0] _413_;
+ wire [133:0] _414_;
+ wire [3:0] _415_;
+ wire _416_;
+ wire [135:0] _417_;
+ wire _418_;
+ wire _419_;
+ wire [8:0] _420_;
+ wire [1:0] _421_;
+ wire [2:0] _422_;
+ wire [32:0] _423_;
+ wire [71:0] _424_;
+ wire [1:0] _425_;
+ wire [71:0] _426_;
+ wire _427_;
+ wire _428_;
+ wire [4:0] _429_;
+ wire [7:0] _430_;
+ wire _431_;
+ wire _432_;
+ wire _433_;
+ wire _434_;
+ reg _435_;
+ reg [135:0] _436_;
+ reg [335:0] _437_;
+ reg _438_;
+ wire [203:0] _439_;
+ wire [255:0] _440_;
+ wire [111:0] _441_;
+ wire [55:0] _442_;
+ wire [111:0] _443_;
+ wire [55:0] _444_;
+ wire [1:0] _445_;
+ wire [63:0] _446_;
+ wire _447_;
+ wire _448_;
+ wire _449_;
+ wire _450_;
+ wire _451_;
+ wire _452_;
+ wire _453_;
+ wire _454_;
+ wire _455_;
+ wire _456_;
+ wire _457_;
+ wire _458_;
+ wire [50:0] _459_;
+ wire [50:0] _460_;
+ wire _461_;
+ wire [63:0] _462_;
+ wire [63:0] _463_;
+ wire _464_;
+ wire _465_;
+ wire _466_;
+ wire _467_;
+ wire _468_;
+ wire _469_;
+ wire _470_;
+ wire _471_;
+ wire _472_;
+ wire _473_;
+ wire _474_;
+ wire _475_;
+ wire _476_;
+ wire _477_;
+ wire _478_;
+ wire _479_;
+ wire _480_;
+ wire _481_;
+ wire _482_;
+ wire _483_;
+ wire _484_;
+ wire _485_;
+ wire _486_;
+ wire [63:0] _487_;
+ wire _488_;
+ wire _489_;
+ wire _490_;
+ wire _491_;
+ wire _492_;
+ wire _493_;
+ wire _494_;
+ wire _495_;
+ wire _496_;
+ wire _497_;
+ wire _498_;
+ wire _499_;
+ wire _500_;
+ wire _501_;
+ wire _502_;
+ wire _503_;
+ wire _504_;
+ wire _505_;
+ wire _506_;
+ wire _507_;
+ wire _508_;
+ wire _509_;
+ wire _510_;
+ wire _511_;
+ wire _512_;
+ wire _513_;
+ wire _514_;
+ wire _515_;
+ wire _516_;
+ wire _517_;
+ wire _518_;
+ wire _519_;
+ wire _520_;
+ wire _521_;
+ wire _522_;
+ wire _523_;
+ wire _524_;
+ wire access_ok;
+ reg [3:0] cache_valids;
+ wire cancel_store;
+ wire clear_rsrv;
+ input clk;
+ input [142:0] d_in;
+ output [67:0] d_out;
+ reg [3:0] dtlb_valids;
+ wire [3:0] early_req_row;
+ input [131:0] m_in;
+ output [66:0] m_out;
+ wire \maybe_plrus.plrus:0.plru_acc_en ;
+ wire \maybe_plrus.plrus:0.plru_out ;
+ wire \maybe_plrus.plrus:1.plru_acc_en ;
+ wire \maybe_plrus.plrus:1.plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ;
+ wire [5:0] perm_attr;
+ wire perm_ok;
+ wire [63:0] pte;
+ reg [146:0] r0;
+ reg r0_full;
+ wire r0_stall;
+ wire r0_valid;
+ wire [55:0] ra;
+ wire \rams:0.do_write ;
+ wire [63:0] \rams:0.dout ;
+ wire [3:0] \rams:0.wr_addr ;
+ wire [63:0] \rams:0.wr_data ;
+ wire [7:0] \rams:0.wr_sel ;
+ wire [7:0] \rams:0.wr_sel_m ;
+ wire \rams:1.do_write ;
+ wire [63:0] \rams:1.dout ;
+ wire [3:0] \rams:1.wr_addr ;
+ wire [63:0] \rams:1.wr_data ;
+ wire [7:0] \rams:1.wr_sel ;
+ wire [7:0] \rams:1.wr_sel_m ;
+ wire rc_ok;
+ wire replace_way;
+ wire req_go;
+ wire req_hit_way;
+ wire [2:0] req_op;
+ wire req_same_tag;
+ reg [58:0] reservation;
+ input rst;
+ wire set_rsrv;
+ output stall_out;
+ wire tlb_hit;
+ wire tlb_hit_way;
+ wire [127:0] tlb_pte_way;
+ wire [101:0] tlb_tag_way;
+ reg [1:0] tlb_valid_way;
+ wire use_forward1_next;
+ wire use_forward2_next;
+ wire valid_ra;
+ input [65:0] wishbone_in;
+ output [106:0] wishbone_out;
+ reg [101:0] \$mem$\19357 [1:0];
+ reg [127:0] \$mem$\19360 [1:0];
+ reg [55:0] \$mem$\19363 [1:0];
+ reg [55:0] \$mem$\19364 [1:0];
+ (* ram_style = "distributed" *)
+ reg [101:0] \19357 [1:0];
+ reg [101:0] _531_;
+ always @(posedge clk) begin
+ if (_012_) _531_ <= \19357 [_011_];
+ if (_041_) \19357 [r0[19]] <= { _460_, _459_ };
+ end
+ assign tlb_tag_way = _531_;
+ (* ram_style = "distributed" *)
+ reg [127:0] \19360 [1:0];
+ reg [127:0] _532_;
+ always @(posedge clk) begin
+ if (_012_) _532_ <= \19360 [_011_];
+ if (_045_) \19360 [r0[19]] <= { _463_, _462_ };
+ end
+ assign tlb_pte_way = _532_;
+ (* ram_style = "distributed" *)
+ reg [55:0] \19363 [1:0];
+ reg [55:0] _533_;
+ always @(posedge clk) begin
+ _533_ <= \19363 [_049_];
+ if (_434_) \19363 [_437_[318]] <= { 7'h00, _437_[312:264] };
+ end
+ assign _442_ = _533_;
+ (* ram_style = "distributed" *)
+ reg [55:0] \19364 [1:0];
+ reg [55:0] _534_;
+ always @(posedge clk) begin
+ _534_ <= \19364 [_049_];
+ if (_433_) \19364 [_437_[318]] <= { 7'h00, _437_[312:264] };
+ end
+ assign _444_ = _534_;
+ assign _521_ = _110_[0] ? _437_[323] : _437_[322];
+ assign _522_ = _110_[0] ? _437_[327] : _437_[326];
+ assign _523_ = _110_[0] ? _437_[325] : _437_[324];
+ assign _524_ = _110_[0] ? _437_[329] : _437_[328];
+ assign _483_ = _110_[1] ? _523_ : _521_;
+ assign _484_ = _110_[1] ? _524_ : _522_;
+ assign _000_ = m_in[1] | m_in[3];
+ assign _001_ = ~ _000_;
+ assign _002_ = m_in[0] ? { 1'h1, m_in[3:1], 8'hff, m_in[131:4], 5'h10, _001_, 1'h1 } : { 4'h0, d_in };
+ assign _003_ = ~ _435_;
+ assign _004_ = ~ r0_full;
+ assign _005_ = _003_ | _004_;
+ assign _006_ = _005_ ? _002_ : r0;
+ assign _007_ = _005_ ? _002_[0] : r0_full;
+ assign _008_ = rst ? r0 : _006_;
+ assign _009_ = rst ? 1'h0 : _007_;
+ always @(posedge clk)
+ r0 <= _008_;
+ always @(posedge clk)
+ r0_full <= _009_;
+ assign r0_stall = r0_full & _435_;
+ assign _010_ = ~ _435_;
+ assign r0_valid = r0_full & _010_;
+ assign _011_ = m_in[0] ? m_in[16] : d_in[19];
+ assign _012_ = ~ r0_stall;
+ assign _013_ = 1'h1 - _011_;
+ assign _014_ = _012_ ? _445_ : tlb_valid_way;
+ always @(posedge clk)
+ tlb_valid_way <= _014_;
+ assign _015_ = { 31'h00000000, _198_[6] } == 32'd0;
+ assign \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en = _015_ ? _198_[4] : 1'h0;
+ assign _016_ = { 31'h00000000, _198_[6] } == 32'd1;
+ assign \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en = _016_ ? _198_[4] : 1'h0;
+ assign _017_ = tlb_tag_way[50:0] == r0[70:20];
+ assign _018_ = tlb_valid_way[0] & _017_;
+ assign _019_ = _018_ ? 1'h1 : 1'h0;
+ assign _020_ = tlb_tag_way[101:51] == r0[70:20];
+ assign _021_ = tlb_valid_way[1] & _020_;
+ assign tlb_hit_way = _021_ ? 1'h1 : 1'h0;
+ assign _022_ = _021_ ? 1'h1 : _019_;
+ assign _023_ = _022_ & r0_valid;
+ assign tlb_hit = _023_ & r0[5];
+ assign pte = tlb_hit ? _446_ : 64'h0000000000000000;
+ assign _024_ = ~ r0[5];
+ assign _025_ = r0_valid & _024_;
+ assign valid_ra = tlb_hit | _025_;
+ assign ra = tlb_hit ? { pte[55:12], r0[18:10], 3'h0 } : { r0[62:10], 3'h0 };
+ assign perm_attr = tlb_hit ? { pte[1], pte[2], pte[3], pte[5], pte[7], pte[8] } : 6'h3b;
+ assign _026_ = r0_valid & r0[143];
+ assign _027_ = r0_valid & r0[145];
+ assign _028_ = _026_ & r0[144];
+ assign _029_ = rst | _028_;
+ assign _030_ = 1'h1 - r0[19];
+ assign _031_ = tlb_hit ? { _456_, _455_, _454_, _453_ } : dtlb_valids;
+ assign _032_ = 1'h1 - r0[19];
+ assign _033_ = tlb_hit ? tlb_hit_way : _457_;
+ assign _034_ = 1'h1 - r0[19];
+ assign _035_ = _027_ ? { _473_, _472_, _471_, _470_ } : dtlb_valids;
+ assign _036_ = _026_ ? _031_ : _035_;
+ assign _037_ = _029_ ? 4'h0 : _036_;
+ always @(posedge clk)
+ dtlb_valids <= _037_;
+ assign _038_ = ~ _029_;
+ assign _039_ = ~ _026_;
+ assign _040_ = _038_ & _039_;
+ assign _041_ = _040_ & _027_;
+ assign _042_ = ~ _029_;
+ assign _043_ = ~ _026_;
+ assign _044_ = _042_ & _043_;
+ assign _045_ = _044_ & _027_;
+ assign _046_ = { 31'h00000000, _198_[2] } == 32'd0;
+ assign \maybe_plrus.plrus:0.plru_acc_en = _046_ ? _198_[3] : 1'h0;
+ assign _047_ = { 31'h00000000, _198_[2] } == 32'd1;
+ assign \maybe_plrus.plrus:1.plru_acc_en = _047_ ? _198_[3] : 1'h0;
+ assign _048_ = m_in[0] ? m_in[10] : d_in[13];
+ assign _049_ = r0_stall ? r0[13] : _048_;
+ assign _050_ = r0[143] | r0[145];
+ assign _051_ = ~ _050_;
+ assign _052_ = r0_valid & _051_;
+ assign _053_ = ~ _199_;
+ assign req_go = _052_ & _053_;
+ assign _054_ = 1'h1 - r0[13];
+ assign _055_ = req_go & _474_;
+ assign _056_ = _442_[48:0] == { tlb_pte_way[55:12], r0[18:14] };
+ assign _057_ = _055_ & _056_;
+ assign _058_ = _057_ & tlb_valid_way[0];
+ assign _059_ = _058_ ? 1'h1 : 1'h0;
+ assign _060_ = _058_ ? 1'h0 : 1'h0;
+ assign _061_ = 1'h1 - r0[13];
+ assign _062_ = req_go & _475_;
+ assign _063_ = _444_[48:0] == { tlb_pte_way[55:12], r0[18:14] };
+ assign _064_ = _062_ & _063_;
+ assign _065_ = _064_ & tlb_valid_way[0];
+ assign _066_ = _065_ ? 1'h1 : _059_;
+ assign _067_ = _065_ ? 1'h1 : _060_;
+ assign _068_ = { tlb_pte_way[55:12], r0[18:14] } == _437_[312:264];
+ assign _069_ = _068_ ? 1'h1 : 1'h0;
+ assign _070_ = 1'h1 - r0[13];
+ assign _071_ = req_go & _476_;
+ assign _072_ = _442_[48:0] == { tlb_pte_way[119:76], r0[18:14] };
+ assign _073_ = _071_ & _072_;
+ assign _074_ = _073_ & tlb_valid_way[1];
+ assign _075_ = _074_ ? 1'h1 : 1'h0;
+ assign _076_ = _074_ ? 1'h0 : 1'h0;
+ assign _077_ = 1'h1 - r0[13];
+ assign _078_ = req_go & _477_;
+ assign _079_ = _444_[48:0] == { tlb_pte_way[119:76], r0[18:14] };
+ assign _080_ = _078_ & _079_;
+ assign _081_ = _080_ & tlb_valid_way[1];
+ assign _082_ = _081_ ? 1'h1 : _075_;
+ assign _083_ = _081_ ? 1'h1 : _076_;
+ assign _084_ = { tlb_pte_way[119:76], r0[18:14] } == _437_[312:264];
+ assign _085_ = _084_ ? 1'h1 : 1'h0;
+ assign _086_ = 1'h1 - tlb_hit_way;
+ assign _087_ = tlb_hit ? _478_ : 1'h0;
+ assign _088_ = tlb_hit ? _479_ : 1'h0;
+ assign _089_ = tlb_hit ? _480_ : 1'h0;
+ assign _090_ = 1'h1 - r0[13];
+ assign _091_ = req_go & _481_;
+ assign _092_ = _442_[48:0] == r0[62:14];
+ assign _093_ = _091_ & _092_;
+ assign _094_ = _093_ ? 1'h1 : 1'h0;
+ assign _095_ = 1'h1 - r0[13];
+ assign _096_ = req_go & _482_;
+ assign _097_ = _444_[48:0] == r0[62:14];
+ assign _098_ = _096_ & _097_;
+ assign _099_ = _098_ ? 1'h1 : _094_;
+ assign _100_ = _098_ ? 1'h1 : 1'h0;
+ assign _101_ = r0[62:14] == _437_[312:264];
+ assign _102_ = _101_ ? 1'h1 : 1'h0;
+ assign _103_ = r0[5] ? _087_ : _099_;
+ assign _104_ = r0[5] ? _088_ : _100_;
+ assign req_same_tag = r0[5] ? _089_ : _102_;
+ assign _105_ = _437_[152:151] == 2'h1;
+ assign _106_ = { 31'h00000000, r0[13] } == { 31'h00000000, _437_[318] };
+ assign _107_ = _105_ & _106_;
+ assign _108_ = _107_ & req_same_tag;
+ assign _109_ = ~ r0[1];
+ assign _110_ = 3'h7 - r0[12:10];
+ assign _111_ = _109_ | _485_;
+ assign _112_ = _108_ ? _111_ : _103_;
+ assign req_hit_way = _108_ ? replace_way : _104_;
+ assign _113_ = { 28'h0000000, _436_[11:8] } == { 28'h0000000, r0[13:10] };
+ assign _114_ = { 31'h00000000, _436_[133] } == { 31'h00000000, req_hit_way };
+ assign _115_ = _113_ & _114_;
+ assign use_forward1_next = _115_ ? _437_[154] : 1'h0;
+ assign _116_ = { 28'h0000000, _437_[141:138] } == { 28'h0000000, r0[13:10] };
+ assign _117_ = { 31'h00000000, _437_[137] } == { 31'h00000000, req_hit_way };
+ assign _118_ = _116_ & _117_;
+ assign use_forward2_next = _118_ ? _437_[136] : 1'h0;
+ assign _119_ = 1'h1 - _437_[318];
+ assign replace_way = _437_[155] ? _486_ : _437_[313];
+ assign _120_ = r0[1] | perm_attr[1];
+ assign rc_ok = perm_attr[0] & _120_;
+ assign _121_ = r0[6] & r0[0];
+ assign _122_ = ~ perm_attr[3];
+ assign _123_ = _121_ | _122_;
+ assign _124_ = r0[1] & perm_attr[4];
+ assign _125_ = perm_attr[5] | _124_;
+ assign perm_ok = _123_ & _125_;
+ assign _126_ = valid_ra & perm_ok;
+ assign access_ok = _126_ & rc_ok;
+ assign _127_ = r0[3] | perm_attr[2];
+ assign _128_ = ~ access_ok;
+ assign _129_ = { r0[1], _127_, _112_ } == 3'h5;
+ assign _130_ = { r0[1], _127_, _112_ } == 3'h4;
+ assign _131_ = { r0[1], _127_, _112_ } == 3'h6;
+ assign _132_ = { r0[1], _127_, _112_ } == 3'h1;
+ assign _133_ = { r0[1], _127_, _112_ } == 3'h0;
+ assign _134_ = { r0[1], _127_, _112_ } == 3'h2;
+ assign _135_ = { r0[1], _127_, _112_ } == 3'h3;
+ assign _136_ = { r0[1], _127_, _112_ } == 3'h7;
+ function [2:0] \18202 ;
+ input [2:0] a;
+ input [23:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \18202 = b[2:0];
+ 8'b??????1?:
+ \18202 = b[5:3];
+ 8'b?????1??:
+ \18202 = b[8:6];
+ 8'b????1???:
+ \18202 = b[11:9];
+ 8'b???1????:
+ \18202 = b[14:12];
+ 8'b??1?????:
+ \18202 = b[17:15];
+ 8'b?1??????:
+ \18202 = b[20:18];
+ 8'b1???????:
+ \18202 = b[23:21];
+ default:
+ \18202 = a;
+ endcase
+ endfunction
+ assign _137_ = \18202 (3'h0, 24'h27fd63, { _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_ });
+ assign _138_ = cancel_store ? 3'h2 : _137_;
+ assign _139_ = _128_ ? 3'h1 : _138_;
+ assign req_op = req_go ? _139_ : 3'h0;
+ assign _140_ = ~ r0_stall;
+ assign _141_ = m_in[0] ? m_in[10:7] : d_in[13:10];
+ assign early_req_row = _140_ ? _141_ : r0[13:10];
+ assign _142_ = r0_valid & r0[4];
+ assign _143_ = ~ reservation[0];
+ assign _144_ = r0[70:13] != reservation[58:1];
+ assign _145_ = _143_ | _144_;
+ assign _146_ = _145_ ? 1'h1 : 1'h0;
+ assign _147_ = r0[1] ? 1'h0 : _146_;
+ assign _148_ = r0[1] ? 1'h1 : 1'h0;
+ assign _149_ = r0[1] ? 1'h0 : 1'h1;
+ assign cancel_store = _142_ ? _147_ : 1'h0;
+ assign set_rsrv = _142_ ? _148_ : 1'h0;
+ assign clear_rsrv = _142_ ? _149_ : 1'h0;
+ assign _150_ = r0_valid & access_ok;
+ assign _151_ = set_rsrv ? { r0[70:13], 1'h1 } : reservation;
+ assign _152_ = clear_rsrv ? 1'h0 : _151_[0];
+ assign _153_ = clear_rsrv ? reservation[58:1] : _151_[58:1];
+ assign _154_ = _150_ ? { _153_, _152_ } : reservation;
+ assign _155_ = rst ? 1'h0 : _154_[0];
+ assign _156_ = rst ? reservation[58:1] : _154_[58:1];
+ always @(posedge clk)
+ reservation <= { _156_, _155_ };
+ assign _157_ = _437_[142] ? _437_[63:0] : _437_[127:64];
+ assign _158_ = 1'h1 - _198_[0];
+ assign _159_ = _437_[143] ? _157_[7:0] : _487_[7:0];
+ assign _160_ = _437_[144] ? _157_[15:8] : _487_[15:8];
+ assign _161_ = _437_[145] ? _157_[23:16] : _487_[23:16];
+ assign _162_ = _437_[146] ? _157_[31:24] : _487_[31:24];
+ assign _163_ = _437_[147] ? _157_[39:32] : _487_[39:32];
+ assign _164_ = _437_[148] ? _157_[47:40] : _487_[47:40];
+ assign _165_ = _437_[149] ? _157_[55:48] : _487_[55:48];
+ assign _166_ = _437_[150] ? _157_[63:56] : _487_[63:56];
+ assign _167_ = ~ _200_[2];
+ assign _168_ = 32'd0 == { 31'h00000000, _436_[133] };
+ assign _169_ = _168_ ? 1'h1 : 1'h0;
+ assign _170_ = _437_[153] ? 64'h0000000000000000 : wishbone_in[63:0];
+ assign _171_ = _437_[152:151] == 2'h1;
+ assign _172_ = _171_ & wishbone_in[64];
+ assign _173_ = { 31'h00000000, replace_way } == 32'd0;
+ assign _174_ = _172_ & _173_;
+ assign _175_ = _174_ ? 1'h1 : 1'h0;
+ assign \rams:0.do_write = _437_[154] ? _169_ : _175_;
+ assign \rams:0.wr_addr = _437_[154] ? _436_[11:8] : _437_[317:314];
+ assign \rams:0.wr_data = _437_[154] ? _436_[124:61] : _170_;
+ assign \rams:0.wr_sel = _437_[154] ? _436_[132:125] : 8'hff;
+ assign \rams:0.wr_sel_m = \rams:0.do_write ? \rams:0.wr_sel : 8'h00;
+ assign _176_ = 32'd1 == { 31'h00000000, _436_[133] };
+ assign _177_ = _176_ ? 1'h1 : 1'h0;
+ assign _178_ = _437_[153] ? 64'h0000000000000000 : wishbone_in[63:0];
+ assign _179_ = _437_[152:151] == 2'h1;
+ assign _180_ = _179_ & wishbone_in[64];
+ assign _181_ = { 31'h00000000, replace_way } == 32'd1;
+ assign _182_ = _180_ & _181_;
+ assign _183_ = _182_ ? 1'h1 : 1'h0;
+ assign \rams:1.do_write = _437_[154] ? _177_ : _183_;
+ assign \rams:1.wr_addr = _437_[154] ? _436_[11:8] : _437_[317:314];
+ assign \rams:1.wr_data = _437_[154] ? _436_[124:61] : _178_;
+ assign \rams:1.wr_sel = _437_[154] ? _436_[132:125] : 8'hff;
+ assign \rams:1.wr_sel_m = \rams:1.do_write ? \rams:1.wr_sel : 8'h00;
+ assign _184_ = req_op == 3'h3;
+ assign _185_ = _184_ ? 1'h1 : 1'h0;
+ assign _186_ = req_op == 3'h3;
+ assign _187_ = req_op == 3'h6;
+ assign _188_ = _186_ | _187_;
+ assign _189_ = _188_ ? 1'h1 : 1'h0;
+ assign _190_ = req_op == 3'h1;
+ assign _191_ = ~ r0[146];
+ assign _192_ = _190_ ? _191_ : 1'h0;
+ assign _193_ = _190_ ? { access_ok, r0[146] } : 2'h0;
+ assign _194_ = req_op == 3'h2;
+ assign _195_ = _194_ ? 1'h1 : 1'h0;
+ assign _196_ = r0_valid ? r0[146] : _197_;
+ always @(posedge clk)
+ _197_ <= _196_;
+ always @(posedge clk)
+ _198_ <= { r0[19], tlb_hit_way, tlb_hit, _189_, r0[13], _185_, req_hit_way };
+ always @(posedge clk)
+ _199_ <= _192_;
+ always @(posedge clk)
+ _200_ <= { _195_, _193_ };
+ assign _201_ = use_forward2_next ? _437_[135:128] : 8'h00;
+ assign _202_ = use_forward1_next ? _436_[132:125] : _201_;
+ assign _203_ = _437_[153] ? 64'h0000000000000000 : wishbone_in[63:0];
+ assign _204_ = _437_[154] ? _436_[124:61] : _203_;
+ assign _205_ = r0[143] | r0[145];
+ assign _206_ = r0_valid & _205_;
+ assign _207_ = req_op == 3'h3;
+ assign _208_ = req_op == 3'h2;
+ assign _209_ = _207_ | _208_;
+ assign _210_ = ~ r0[146];
+ assign _211_ = _213_ ? 1'h1 : 1'h0;
+ assign _212_ = _210_ ? _206_ : 1'h1;
+ assign _213_ = _209_ & _210_;
+ assign _214_ = _209_ ? _212_ : _206_;
+ assign _215_ = 32'd0 == { 31'h00000000, replace_way };
+ assign _216_ = 32'd1 == { 31'h00000000, replace_way };
+ assign _217_ = _437_[155] ? 1'h0 : _437_[155];
+ assign _218_ = _437_[155] ? replace_way : _437_[313];
+ assign _219_ = ~ r0[2];
+ assign _220_ = _219_ ? r0[134:71] : 64'h0000000000000000;
+ assign _221_ = ~ r0[3];
+ assign _222_ = r0[1] & _221_;
+ assign _223_ = r0[2] | _222_;
+ assign _224_ = _223_ ? 8'hff : r0[142:135];
+ assign _225_ = req_op == 3'h4;
+ assign _226_ = req_op == 3'h5;
+ assign _227_ = _225_ | _226_;
+ assign _228_ = req_op == 3'h7;
+ assign _229_ = _227_ | _228_;
+ assign _230_ = req_op == 3'h6;
+ assign _231_ = _229_ | _230_;
+ assign _232_ = _231_ ? 1'h1 : _435_;
+ assign _233_ = _435_ ? _435_ : _232_;
+ assign _234_ = _435_ ? _436_ : { r0[146], req_same_tag, req_hit_way, _224_, _220_, ra, r0[2], req_go, req_op };
+ assign _235_ = _234_[10:8] - 3'h1;
+ assign _236_ = _234_[2:0] == 3'h6;
+ assign _237_ = _236_ ? _234_[133] : _218_;
+ assign _238_ = _234_[2:0] == 3'h3;
+ assign _239_ = _234_[2:0] == 3'h4;
+ assign _240_ = _234_[2:0] == 3'h5;
+ assign _241_ = ~ _234_[4];
+ assign _242_ = ~ _234_[135];
+ assign _243_ = _255_ ? 1'h1 : _211_;
+ assign _244_ = _242_ ? _214_ : 1'h1;
+ assign _245_ = _234_[2:0] == 3'h6;
+ assign _246_ = _251_ ? 1'h1 : 1'h0;
+ assign _247_ = _234_[2:0] == 3'h7;
+ assign _248_ = _247_ ? 1'h1 : _217_;
+ assign _249_ = _241_ ? 1'h0 : _233_;
+ assign _250_ = _241_ ? 2'h2 : 2'h1;
+ assign _251_ = _241_ & _245_;
+ assign _252_ = _241_ ? _217_ : _248_;
+ assign _253_ = _241_ ? 1'h1 : 1'h0;
+ assign _254_ = _241_ ? 3'h1 : _437_[332:330];
+ assign _255_ = _241_ & _242_;
+ assign _256_ = _241_ ? _244_ : _214_;
+ assign _257_ = _234_[2:0] == 3'h6;
+ assign _258_ = _234_[2:0] == 3'h7;
+ assign _259_ = _257_ | _258_;
+ assign _260_ = _234_[2:0] == 3'h0;
+ assign _261_ = _234_[2:0] == 3'h1;
+ assign _262_ = _234_[2:0] == 3'h2;
+ function [0:0] \18809 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18809 = b[0:0];
+ 7'b?????1?:
+ \18809 = b[1:1];
+ 7'b????1??:
+ \18809 = b[2:2];
+ 7'b???1???:
+ \18809 = b[3:3];
+ 7'b??1????:
+ \18809 = b[4:4];
+ 7'b?1?????:
+ \18809 = b[5:5];
+ 7'b1??????:
+ \18809 = b[6:6];
+ default:
+ \18809 = a;
+ endcase
+ endfunction
+ assign _263_ = \18809 (1'hx, { _233_, _233_, _233_, _249_, _233_, _233_, _233_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [1:0] \18812 ;
+ input [1:0] a;
+ input [13:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18812 = b[1:0];
+ 7'b?????1?:
+ \18812 = b[3:2];
+ 7'b????1??:
+ \18812 = b[5:4];
+ 7'b???1???:
+ \18812 = b[7:6];
+ 7'b??1????:
+ \18812 = b[9:8];
+ 7'b?1?????:
+ \18812 = b[11:10];
+ 7'b1??????:
+ \18812 = b[13:12];
+ default:
+ \18812 = a;
+ endcase
+ endfunction
+ assign _264_ = \18812 (2'hx, { _437_[152:151], _437_[152:151], _437_[152:151], _250_, 4'hd, _437_[152:151] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18814 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18814 = b[0:0];
+ 7'b?????1?:
+ \18814 = b[1:1];
+ 7'b????1??:
+ \18814 = b[2:2];
+ 7'b???1???:
+ \18814 = b[3:3];
+ 7'b??1????:
+ \18814 = b[4:4];
+ 7'b?1?????:
+ \18814 = b[5:5];
+ 7'b1??????:
+ \18814 = b[6:6];
+ default:
+ \18814 = a;
+ endcase
+ endfunction
+ assign _265_ = \18814 (1'hx, { 3'h0, _246_, 3'h0 }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18816 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18816 = b[0:0];
+ 7'b?????1?:
+ \18816 = b[1:1];
+ 7'b????1??:
+ \18816 = b[2:2];
+ 7'b???1???:
+ \18816 = b[3:3];
+ 7'b??1????:
+ \18816 = b[4:4];
+ 7'b?1?????:
+ \18816 = b[5:5];
+ 7'b1??????:
+ \18816 = b[6:6];
+ default:
+ \18816 = a;
+ endcase
+ endfunction
+ assign _266_ = \18816 (1'hx, { _217_, _217_, _217_, _252_, _217_, 1'h1, _217_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18818 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18818 = b[0:0];
+ 7'b?????1?:
+ \18818 = b[1:1];
+ 7'b????1??:
+ \18818 = b[2:2];
+ 7'b???1???:
+ \18818 = b[3:3];
+ 7'b??1????:
+ \18818 = b[4:4];
+ 7'b?1?????:
+ \18818 = b[5:5];
+ 7'b1??????:
+ \18818 = b[6:6];
+ default:
+ \18818 = a;
+ endcase
+ endfunction
+ assign _267_ = \18818 (1'hx, { 3'h0, _253_, 3'h0 }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18821 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18821 = b[0:0];
+ 7'b?????1?:
+ \18821 = b[1:1];
+ 7'b????1??:
+ \18821 = b[2:2];
+ 7'b???1???:
+ \18821 = b[3:3];
+ 7'b??1????:
+ \18821 = b[4:4];
+ 7'b?1?????:
+ \18821 = b[5:5];
+ 7'b1??????:
+ \18821 = b[6:6];
+ default:
+ \18821 = a;
+ endcase
+ endfunction
+ assign _268_ = \18821 (1'hx, { _437_[261], _437_[261], _437_[261], 3'h7, _437_[261] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18824 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18824 = b[0:0];
+ 7'b?????1?:
+ \18824 = b[1:1];
+ 7'b????1??:
+ \18824 = b[2:2];
+ 7'b???1???:
+ \18824 = b[3:3];
+ 7'b??1????:
+ \18824 = b[4:4];
+ 7'b?1?????:
+ \18824 = b[5:5];
+ 7'b1??????:
+ \18824 = b[6:6];
+ default:
+ \18824 = a;
+ endcase
+ endfunction
+ assign _269_ = \18824 (1'hx, { _437_[262], _437_[262], _437_[262], 3'h7, _437_[262] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18827 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18827 = b[0:0];
+ 7'b?????1?:
+ \18827 = b[1:1];
+ 7'b????1??:
+ \18827 = b[2:2];
+ 7'b???1???:
+ \18827 = b[3:3];
+ 7'b??1????:
+ \18827 = b[4:4];
+ 7'b?1?????:
+ \18827 = b[5:5];
+ 7'b1??????:
+ \18827 = b[6:6];
+ default:
+ \18827 = a;
+ endcase
+ endfunction
+ assign _270_ = \18827 (1'hx, { _437_[263], _437_[263], _437_[263], 3'h4, _437_[263] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [2:0] \18830 ;
+ input [2:0] a;
+ input [20:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18830 = b[2:0];
+ 7'b?????1?:
+ \18830 = b[5:3];
+ 7'b????1??:
+ \18830 = b[8:6];
+ 7'b???1???:
+ \18830 = b[11:9];
+ 7'b??1????:
+ \18830 = b[14:12];
+ 7'b?1?????:
+ \18830 = b[17:15];
+ 7'b1??????:
+ \18830 = b[20:18];
+ default:
+ \18830 = a;
+ endcase
+ endfunction
+ assign _271_ = \18830 (3'hx, { _437_[332:330], _437_[332:330], _437_[332:330], _254_, _437_[332:330], _437_[332:330], _437_[332:330] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18832 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18832 = b[0:0];
+ 7'b?????1?:
+ \18832 = b[1:1];
+ 7'b????1??:
+ \18832 = b[2:2];
+ 7'b???1???:
+ \18832 = b[3:3];
+ 7'b??1????:
+ \18832 = b[4:4];
+ 7'b?1?????:
+ \18832 = b[5:5];
+ 7'b1??????:
+ \18832 = b[6:6];
+ default:
+ \18832 = a;
+ endcase
+ endfunction
+ assign _272_ = \18832 (1'hx, { _211_, _211_, _211_, _243_, _211_, _211_, _211_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ function [0:0] \18834 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \18834 = b[0:0];
+ 7'b?????1?:
+ \18834 = b[1:1];
+ 7'b????1??:
+ \18834 = b[2:2];
+ 7'b???1???:
+ \18834 = b[3:3];
+ 7'b??1????:
+ \18834 = b[4:4];
+ 7'b?1?????:
+ \18834 = b[5:5];
+ 7'b1??????:
+ \18834 = b[6:6];
+ default:
+ \18834 = a;
+ endcase
+ endfunction
+ assign _273_ = \18834 (1'hx, { _214_, _214_, _214_, _256_, _214_, _214_, _214_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+ assign _274_ = _437_[152:151] == 2'h0;
+ assign _275_ = ~ _437_[262];
+ assign _276_ = ~ wishbone_in[65];
+ assign _277_ = ~ _275_;
+ assign _278_ = _276_ & _277_;
+ assign _279_ = _437_[162:160] == _437_[321:319];
+ assign _280_ = _284_ ? 1'h0 : _437_[262];
+ assign _281_ = _285_ ? 1'h1 : _275_;
+ assign _282_ = _437_[162:160] + 3'h1;
+ assign _283_ = _278_ ? { _437_[188:163], _282_, _437_[159:157] } : _437_[188:157];
+ assign _284_ = _278_ & _279_;
+ assign _285_ = _278_ & _279_;
+ assign _286_ = 3'h7 - _437_[316:314];
+ assign _287_ = _435_ & _436_[134];
+ assign _288_ = _437_[153] & _436_[4];
+ assign _289_ = ~ _437_[153];
+ assign _290_ = _436_[2:0] == 3'h4;
+ assign _291_ = _289_ & _290_;
+ assign _292_ = _288_ | _291_;
+ assign _293_ = _287_ & _292_;
+ assign _294_ = { 28'h0000000, _437_[317:314] } == { 28'h0000000, _436_[11:8] };
+ assign _295_ = _293_ & _294_;
+ assign _296_ = ~ _197_;
+ assign _297_ = _318_ ? 1'h1 : _211_;
+ assign _298_ = _296_ ? _214_ : 1'h1;
+ assign _299_ = _312_ ? 1'h0 : _233_;
+ assign _300_ = _295_ ? 9'h1ff : { _202_, use_forward1_next };
+ assign _301_ = _314_ ? 1'h1 : 1'h0;
+ assign _302_ = _295_ & _296_;
+ assign _303_ = _319_ ? _298_ : _214_;
+ assign _304_ = _437_[316:314] == _437_[321:319];
+ assign _305_ = _281_ & _304_;
+ assign _306_ = 1'h1 - _437_[318];
+ assign _307_ = _311_ ? { _520_, _519_, _518_, _517_ } : cache_valids;
+ assign _308_ = _305_ ? 2'h0 : _437_[152:151];
+ assign _309_ = _315_ ? 1'h0 : _437_[261];
+ assign _310_ = _437_[316:314] + 3'h1;
+ assign _311_ = wishbone_in[64] & _305_;
+ assign _312_ = wishbone_in[64] & _295_;
+ assign _313_ = wishbone_in[64] ? { _308_, _300_ } : { _437_[152:151], _202_, use_forward1_next };
+ assign _314_ = wishbone_in[64] & _295_;
+ assign _315_ = wishbone_in[64] & _305_;
+ assign _316_ = wishbone_in[64] ? { _437_[317], _310_ } : _437_[317:314];
+ assign _317_ = wishbone_in[64] ? { _510_, _509_, _508_, _507_, _506_, _505_, _504_, _503_ } : _437_[329:322];
+ assign _318_ = wishbone_in[64] & _302_;
+ assign _319_ = wishbone_in[64] & _295_;
+ assign _320_ = _437_[152:151] == 2'h1;
+ assign _321_ = ~ _437_[262];
+ assign _322_ = _437_[333] != _437_[334];
+ assign _323_ = _437_[332:330] + 3'h1;
+ assign _324_ = _437_[332:330] - 3'h1;
+ assign _325_ = _437_[333] ? _323_ : _324_;
+ assign _326_ = _322_ ? _325_ : _437_[332:330];
+ assign _327_ = ~ wishbone_in[65];
+ assign _328_ = _234_[3] ? _234_[11:5] : _437_[163:157];
+ assign _329_ = _348_ ? _234_[132:61] : _437_[260:189];
+ assign _330_ = _326_ < 3'h7;
+ assign _331_ = _330_ & _234_[134];
+ assign _332_ = _234_[2:0] == 3'h7;
+ assign _333_ = _234_[2:0] == 3'h6;
+ assign _334_ = _332_ | _333_;
+ assign _335_ = _331_ & _334_;
+ assign _336_ = _234_[2:0] == 3'h6;
+ assign _337_ = _346_ ? 1'h1 : 1'h0;
+ assign _338_ = _345_ ? 1'h0 : _233_;
+ assign _339_ = _335_ & _336_;
+ assign _340_ = _335_ ? 1'h1 : 1'h0;
+ assign _341_ = _335_ ? 1'h1 : 1'h0;
+ assign _342_ = _350_ ? 1'h1 : 1'h0;
+ assign _343_ = _351_ ? 1'h1 : _211_;
+ assign _344_ = _335_ ? 1'h0 : 1'h1;
+ assign _345_ = _327_ & _335_;
+ assign _346_ = _327_ & _339_;
+ assign _347_ = _327_ ? { _328_, _340_ } : { _437_[163:157], 1'h0 };
+ assign _348_ = _327_ & _234_[3];
+ assign _349_ = _327_ ? _341_ : _437_[262];
+ assign _350_ = _327_ & _335_;
+ assign _351_ = _327_ & _335_;
+ assign _352_ = _327_ ? _344_ : _321_;
+ assign _353_ = _326_ == 3'h1;
+ assign _354_ = _352_ & _353_;
+ assign _355_ = _357_ ? 2'h0 : _437_[152:151];
+ assign _356_ = _354_ ? 2'h0 : { _349_, _437_[261] };
+ assign _357_ = wishbone_in[64] & _354_;
+ assign _358_ = wishbone_in[64] ? _356_ : { _349_, _437_[261] };
+ assign _359_ = wishbone_in[64] ? 1'h1 : 1'h0;
+ assign _360_ = _437_[152:151] == 2'h2;
+ assign _361_ = ~ wishbone_in[65];
+ assign _362_ = _361_ ? 1'h0 : _437_[262];
+ assign _363_ = ~ _197_;
+ assign _364_ = _370_ ? 1'h1 : _211_;
+ assign _365_ = _363_ ? _214_ : 1'h1;
+ assign _366_ = wishbone_in[64] ? 1'h0 : _233_;
+ assign _367_ = wishbone_in[64] ? 11'h1ff : { _437_[152:151], _202_, use_forward1_next };
+ assign _368_ = wishbone_in[64] ? 1'h1 : 1'h0;
+ assign _369_ = wishbone_in[64] ? 2'h0 : { _362_, _437_[261] };
+ assign _370_ = wishbone_in[64] & _363_;
+ assign _371_ = wishbone_in[64] ? _365_ : _214_;
+ assign _372_ = _437_[152:151] == 2'h3;
+ function [3:0] \19137 ;
+ input [3:0] a;
+ input [15:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19137 = b[3:0];
+ 4'b??1?:
+ \19137 = b[7:4];
+ 4'b?1??:
+ \19137 = b[11:8];
+ 4'b1???:
+ \19137 = b[15:12];
+ default:
+ \19137 = a;
+ endcase
+ endfunction
+ assign _373_ = \19137 (4'hx, { cache_valids, cache_valids, _307_, cache_valids }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19139 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19139 = b[0:0];
+ 4'b??1?:
+ \19139 = b[1:1];
+ 4'b?1??:
+ \19139 = b[2:2];
+ 4'b1???:
+ \19139 = b[3:3];
+ default:
+ \19139 = a;
+ endcase
+ endfunction
+ assign _374_ = \19139 (1'hx, { _366_, _338_, _299_, _263_ }, { _372_, _360_, _320_, _274_ });
+ assign _375_ = _231_ ? req_same_tag : _436_[134];
+ assign _376_ = _435_ ? _436_[134] : _375_;
+ function [0:0] \19146 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19146 = b[0:0];
+ 4'b??1?:
+ \19146 = b[1:1];
+ 4'b?1??:
+ \19146 = b[2:2];
+ 4'b1???:
+ \19146 = b[3:3];
+ default:
+ \19146 = a;
+ endcase
+ endfunction
+ assign _377_ = \19146 (1'hx, { _376_, _376_, _376_, 1'h1 }, { _372_, _360_, _320_, _274_ });
+ assign _378_ = _437_[154] ? 1'h1 : 1'h0;
+ function [0:0] \19151 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19151 = b[0:0];
+ 4'b??1?:
+ \19151 = b[1:1];
+ 4'b?1??:
+ \19151 = b[2:2];
+ 4'b1???:
+ \19151 = b[3:3];
+ default:
+ \19151 = a;
+ endcase
+ endfunction
+ assign _379_ = \19151 (1'hx, { _378_, _378_, wishbone_in[64], _378_ }, { _372_, _360_, _320_, _274_ });
+ function [8:0] \19156 ;
+ input [8:0] a;
+ input [35:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19156 = b[8:0];
+ 4'b??1?:
+ \19156 = b[17:9];
+ 4'b?1??:
+ \19156 = b[26:18];
+ 4'b1???:
+ \19156 = b[35:27];
+ default:
+ \19156 = a;
+ endcase
+ endfunction
+ assign _380_ = \19156 (9'hxxx, { _367_[8:0], _202_, use_forward1_next, _313_[8:0], _202_, use_forward1_next }, { _372_, _360_, _320_, _274_ });
+ function [1:0] \19160 ;
+ input [1:0] a;
+ input [7:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19160 = b[1:0];
+ 4'b??1?:
+ \19160 = b[3:2];
+ 4'b?1??:
+ \19160 = b[5:4];
+ 4'b1???:
+ \19160 = b[7:6];
+ default:
+ \19160 = a;
+ endcase
+ endfunction
+ assign _381_ = \19160 (2'hx, { _367_[10:9], _355_, _313_[10:9], _264_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19163 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19163 = b[0:0];
+ 4'b??1?:
+ \19163 = b[1:1];
+ 4'b?1??:
+ \19163 = b[2:2];
+ 4'b1???:
+ \19163 = b[3:3];
+ default:
+ \19163 = a;
+ endcase
+ endfunction
+ assign _382_ = \19163 (1'hx, { _437_[153], _437_[153], _437_[153], _234_[4] }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19165 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19165 = b[0:0];
+ 4'b??1?:
+ \19165 = b[1:1];
+ 4'b?1??:
+ \19165 = b[2:2];
+ 4'b1???:
+ \19165 = b[3:3];
+ default:
+ \19165 = a;
+ endcase
+ endfunction
+ assign _383_ = \19165 (1'hx, { 1'h0, _337_, 1'h0, _265_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19167 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19167 = b[0:0];
+ 4'b??1?:
+ \19167 = b[1:1];
+ 4'b?1??:
+ \19167 = b[2:2];
+ 4'b1???:
+ \19167 = b[3:3];
+ default:
+ \19167 = a;
+ endcase
+ endfunction
+ assign _384_ = \19167 (1'hx, { _217_, _217_, _217_, _266_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19170 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19170 = b[0:0];
+ 4'b??1?:
+ \19170 = b[1:1];
+ 4'b?1??:
+ \19170 = b[2:2];
+ 4'b1???:
+ \19170 = b[3:3];
+ default:
+ \19170 = a;
+ endcase
+ endfunction
+ assign _385_ = \19170 (1'hx, { _368_, _347_[0], _301_, _267_ }, { _372_, _360_, _320_, _274_ });
+ function [6:0] \19176 ;
+ input [6:0] a;
+ input [27:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19176 = b[6:0];
+ 4'b??1?:
+ \19176 = b[13:7];
+ 4'b?1??:
+ \19176 = b[20:14];
+ 4'b1???:
+ \19176 = b[27:21];
+ default:
+ \19176 = a;
+ endcase
+ endfunction
+ assign _386_ = \19176 (7'hxx, { _437_[163:157], _347_[7:1], _283_[6:0], _234_[11:5] }, { _372_, _360_, _320_, _274_ });
+ function [24:0] \19181 ;
+ input [24:0] a;
+ input [99:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19181 = b[24:0];
+ 4'b??1?:
+ \19181 = b[49:25];
+ 4'b?1??:
+ \19181 = b[74:50];
+ 4'b1???:
+ \19181 = b[99:75];
+ default:
+ \19181 = a;
+ endcase
+ endfunction
+ assign _387_ = \19181 (25'hxxxxxxx, { _437_[188:164], _437_[188:164], _283_[31:7], _234_[36:12] }, { _372_, _360_, _320_, _274_ });
+ function [63:0] \19185 ;
+ input [63:0] a;
+ input [255:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19185 = b[63:0];
+ 4'b??1?:
+ \19185 = b[127:64];
+ 4'b?1??:
+ \19185 = b[191:128];
+ 4'b1???:
+ \19185 = b[255:192];
+ default:
+ \19185 = a;
+ endcase
+ endfunction
+ assign _388_ = \19185 (64'hxxxxxxxxxxxxxxxx, { _437_[252:189], _329_[63:0], _437_[252:189], _234_[124:61] }, { _372_, _360_, _320_, _274_ });
+ function [7:0] \19189 ;
+ input [7:0] a;
+ input [31:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19189 = b[7:0];
+ 4'b??1?:
+ \19189 = b[15:8];
+ 4'b?1??:
+ \19189 = b[23:16];
+ 4'b1???:
+ \19189 = b[31:24];
+ default:
+ \19189 = a;
+ endcase
+ endfunction
+ assign _389_ = \19189 (8'hxx, { _437_[260:253], _329_[71:64], _437_[260:253], _234_[132:125] }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19193 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19193 = b[0:0];
+ 4'b??1?:
+ \19193 = b[1:1];
+ 4'b?1??:
+ \19193 = b[2:2];
+ 4'b1???:
+ \19193 = b[3:3];
+ default:
+ \19193 = a;
+ endcase
+ endfunction
+ assign _390_ = \19193 (1'hx, { _369_[0], _358_[0], _309_, _268_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19197 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19197 = b[0:0];
+ 4'b??1?:
+ \19197 = b[1:1];
+ 4'b?1??:
+ \19197 = b[2:2];
+ 4'b1???:
+ \19197 = b[3:3];
+ default:
+ \19197 = a;
+ endcase
+ endfunction
+ assign _391_ = \19197 (1'hx, { _369_[1], _358_[1], _280_, _269_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19200 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19200 = b[0:0];
+ 4'b??1?:
+ \19200 = b[1:1];
+ 4'b?1??:
+ \19200 = b[2:2];
+ 4'b1???:
+ \19200 = b[3:3];
+ default:
+ \19200 = a;
+ endcase
+ endfunction
+ assign _392_ = \19200 (1'hx, { _437_[263], _437_[263], _437_[263], _270_ }, { _372_, _360_, _320_, _274_ });
+ function [48:0] \19203 ;
+ input [48:0] a;
+ input [195:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19203 = b[48:0];
+ 4'b??1?:
+ \19203 = b[97:49];
+ 4'b?1??:
+ \19203 = b[146:98];
+ 4'b1???:
+ \19203 = b[195:147];
+ default:
+ \19203 = a;
+ endcase
+ endfunction
+ assign _393_ = \19203 (49'hxxxxxxxxxxxxx, { _437_[312:264], _437_[312:264], _437_[312:264], _234_[60:12] }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19205 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19205 = b[0:0];
+ 4'b??1?:
+ \19205 = b[1:1];
+ 4'b?1??:
+ \19205 = b[2:2];
+ 4'b1???:
+ \19205 = b[3:3];
+ default:
+ \19205 = a;
+ endcase
+ endfunction
+ assign _394_ = \19205 (1'hx, { _218_, _218_, _218_, _237_ }, { _372_, _360_, _320_, _274_ });
+ function [3:0] \19208 ;
+ input [3:0] a;
+ input [15:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19208 = b[3:0];
+ 4'b??1?:
+ \19208 = b[7:4];
+ 4'b?1??:
+ \19208 = b[11:8];
+ 4'b1???:
+ \19208 = b[15:12];
+ default:
+ \19208 = a;
+ endcase
+ endfunction
+ assign _395_ = \19208 (4'hx, { _437_[317:314], _437_[317:314], _316_, _234_[11:8] }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19211 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19211 = b[0:0];
+ 4'b??1?:
+ \19211 = b[1:1];
+ 4'b?1??:
+ \19211 = b[2:2];
+ 4'b1???:
+ \19211 = b[3:3];
+ default:
+ \19211 = a;
+ endcase
+ endfunction
+ assign _396_ = \19211 (1'hx, { _437_[318], _437_[318], _437_[318], _234_[11] }, { _372_, _360_, _320_, _274_ });
+ function [2:0] \19214 ;
+ input [2:0] a;
+ input [11:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19214 = b[2:0];
+ 4'b??1?:
+ \19214 = b[5:3];
+ 4'b?1??:
+ \19214 = b[8:6];
+ 4'b1???:
+ \19214 = b[11:9];
+ default:
+ \19214 = a;
+ endcase
+ endfunction
+ assign _397_ = \19214 (3'hx, { _437_[321:319], _437_[321:319], _437_[321:319], _235_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19218 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19218 = b[0:0];
+ 4'b??1?:
+ \19218 = b[1:1];
+ 4'b?1??:
+ \19218 = b[2:2];
+ 4'b1???:
+ \19218 = b[3:3];
+ default:
+ \19218 = a;
+ endcase
+ endfunction
+ assign _398_ = \19218 (1'hx, { _437_[322], _437_[322], _317_[0], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19222 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19222 = b[0:0];
+ 4'b??1?:
+ \19222 = b[1:1];
+ 4'b?1??:
+ \19222 = b[2:2];
+ 4'b1???:
+ \19222 = b[3:3];
+ default:
+ \19222 = a;
+ endcase
+ endfunction
+ assign _399_ = \19222 (1'hx, { _437_[323], _437_[323], _317_[1], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19226 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19226 = b[0:0];
+ 4'b??1?:
+ \19226 = b[1:1];
+ 4'b?1??:
+ \19226 = b[2:2];
+ 4'b1???:
+ \19226 = b[3:3];
+ default:
+ \19226 = a;
+ endcase
+ endfunction
+ assign _400_ = \19226 (1'hx, { _437_[324], _437_[324], _317_[2], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19230 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19230 = b[0:0];
+ 4'b??1?:
+ \19230 = b[1:1];
+ 4'b?1??:
+ \19230 = b[2:2];
+ 4'b1???:
+ \19230 = b[3:3];
+ default:
+ \19230 = a;
+ endcase
+ endfunction
+ assign _401_ = \19230 (1'hx, { _437_[325], _437_[325], _317_[3], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19234 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19234 = b[0:0];
+ 4'b??1?:
+ \19234 = b[1:1];
+ 4'b?1??:
+ \19234 = b[2:2];
+ 4'b1???:
+ \19234 = b[3:3];
+ default:
+ \19234 = a;
+ endcase
+ endfunction
+ assign _402_ = \19234 (1'hx, { _437_[326], _437_[326], _317_[4], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19238 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19238 = b[0:0];
+ 4'b??1?:
+ \19238 = b[1:1];
+ 4'b?1??:
+ \19238 = b[2:2];
+ 4'b1???:
+ \19238 = b[3:3];
+ default:
+ \19238 = a;
+ endcase
+ endfunction
+ assign _403_ = \19238 (1'hx, { _437_[327], _437_[327], _317_[5], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19242 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19242 = b[0:0];
+ 4'b??1?:
+ \19242 = b[1:1];
+ 4'b?1??:
+ \19242 = b[2:2];
+ 4'b1???:
+ \19242 = b[3:3];
+ default:
+ \19242 = a;
+ endcase
+ endfunction
+ assign _404_ = \19242 (1'hx, { _437_[328], _437_[328], _317_[6], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19246 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19246 = b[0:0];
+ 4'b??1?:
+ \19246 = b[1:1];
+ 4'b?1??:
+ \19246 = b[2:2];
+ 4'b1???:
+ \19246 = b[3:3];
+ default:
+ \19246 = a;
+ endcase
+ endfunction
+ assign _405_ = \19246 (1'hx, { _437_[329], _437_[329], _317_[7], 1'h0 }, { _372_, _360_, _320_, _274_ });
+ function [2:0] \19249 ;
+ input [2:0] a;
+ input [11:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19249 = b[2:0];
+ 4'b??1?:
+ \19249 = b[5:3];
+ 4'b?1??:
+ \19249 = b[8:6];
+ 4'b1???:
+ \19249 = b[11:9];
+ default:
+ \19249 = a;
+ endcase
+ endfunction
+ assign _406_ = \19249 (3'hx, { _437_[332:330], _326_, _437_[332:330], _271_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19251 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19251 = b[0:0];
+ 4'b??1?:
+ \19251 = b[1:1];
+ 4'b?1??:
+ \19251 = b[2:2];
+ 4'b1???:
+ \19251 = b[3:3];
+ default:
+ \19251 = a;
+ endcase
+ endfunction
+ assign _407_ = \19251 (1'hx, { 1'h0, _342_, 2'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19253 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19253 = b[0:0];
+ 4'b??1?:
+ \19253 = b[1:1];
+ 4'b?1??:
+ \19253 = b[2:2];
+ 4'b1???:
+ \19253 = b[3:3];
+ default:
+ \19253 = a;
+ endcase
+ endfunction
+ assign _408_ = \19253 (1'hx, { 1'h0, _359_, 2'h0 }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19255 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19255 = b[0:0];
+ 4'b??1?:
+ \19255 = b[1:1];
+ 4'b?1??:
+ \19255 = b[2:2];
+ 4'b1???:
+ \19255 = b[3:3];
+ default:
+ \19255 = a;
+ endcase
+ endfunction
+ assign _409_ = \19255 (1'hx, { _364_, _343_, _297_, _272_ }, { _372_, _360_, _320_, _274_ });
+ function [0:0] \19257 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \19257 = b[0:0];
+ 4'b??1?:
+ \19257 = b[1:1];
+ 4'b?1??:
+ \19257 = b[2:2];
+ 4'b1???:
+ \19257 = b[3:3];
+ default:
+ \19257 = a;
+ endcase
+ endfunction
+ assign _410_ = \19257 (1'hx, { _371_, _214_, _303_, _273_ }, { _372_, _360_, _320_, _274_ });
+ assign _411_ = _231_ ? r0[146] : _436_[135];
+ assign _412_ = _435_ ? _436_[135] : _411_;
+ assign _413_ = _231_ ? { req_hit_way, _224_, _220_, ra, r0[2], req_go, req_op } : _436_[133:0];
+ assign _414_ = _435_ ? _436_[133:0] : _413_;
+ assign _415_ = rst ? 4'h0 : _373_;
+ assign _416_ = rst ? 1'h0 : _374_;
+ assign _417_ = rst ? _436_ : { _412_, _377_, _414_ };
+ assign _418_ = _437_[154] ? 1'h1 : 1'h0;
+ assign _419_ = rst ? _418_ : _379_;
+ assign _420_ = rst ? { _202_, use_forward1_next } : _380_;
+ assign _421_ = rst ? 2'h0 : _381_;
+ assign _422_ = rst ? _437_[155:153] : { _384_, _383_, _382_ };
+ assign _423_ = rst ? 33'h000000000 : { _387_, _386_, _385_ };
+ assign _424_ = rst ? _437_[260:189] : { _389_, _388_ };
+ assign _425_ = rst ? 2'h0 : { _391_, _390_ };
+ assign _426_ = rst ? _437_[334:263] : { _408_, _407_, _406_, _405_, _404_, _403_, _402_, _401_, _400_, _399_, _398_, _397_, _396_, _395_, _394_, _393_, _392_ };
+ assign _427_ = rst ? 1'h0 : _409_;
+ assign _428_ = rst ? 1'h0 : _410_;
+ assign _429_ = _437_[154] ? { _436_[11:8], _436_[133] } : { _437_[317:314], replace_way };
+ assign _430_ = _437_[154] ? _436_[132:125] : 8'hff;
+ assign _431_ = ~ rst;
+ assign _432_ = _431_ & _437_[155];
+ assign _433_ = _432_ & _216_;
+ assign _434_ = _432_ & _215_;
+ always @(posedge clk)
+ cache_valids <= _415_;
+ always @(posedge clk)
+ _435_ <= _416_;
+ always @(posedge clk)
+ _436_ <= _417_;
+ always @(posedge clk)
+ _437_ <= { _427_, _426_, _425_, _424_, _423_, _422_, _421_, _420_, _429_, _419_, _430_, _437_[63:0], _204_ };
+ always @(posedge clk)
+ _438_ <= _428_;
+ assign _445_ = _013_ ? dtlb_valids[3:2] : dtlb_valids[1:0];
+ assign _446_ = tlb_hit_way ? tlb_pte_way[127:64] : tlb_pte_way[63:0];
+ assign _447_ = ~ _030_;
+ assign _448_ = ~ tlb_hit_way;
+ assign _449_ = _447_ & _448_;
+ assign _450_ = _447_ & tlb_hit_way;
+ assign _451_ = _030_ & _448_;
+ assign _452_ = _030_ & tlb_hit_way;
+ assign _453_ = _449_ ? 1'h0 : dtlb_valids[0];
+ assign _454_ = _450_ ? 1'h0 : dtlb_valids[1];
+ assign _455_ = _451_ ? 1'h0 : dtlb_valids[2];
+ assign _456_ = _452_ ? 1'h0 : dtlb_valids[3];
+ assign _457_ = _032_ ? \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ;
+ assign _458_ = ~ _033_;
+ assign _459_ = _458_ ? r0[70:20] : tlb_tag_way[50:0];
+ assign _460_ = _033_ ? r0[70:20] : tlb_tag_way[101:51];
+ assign _461_ = ~ _033_;
+ assign _462_ = _461_ ? r0[134:71] : tlb_pte_way[63:0];
+ assign _463_ = _033_ ? r0[134:71] : tlb_pte_way[127:64];
+ assign _464_ = ~ _034_;
+ assign _465_ = ~ _033_;
+ assign _466_ = _464_ & _465_;
+ assign _467_ = _464_ & _033_;
+ assign _468_ = _034_ & _465_;
+ assign _469_ = _034_ & _033_;
+ assign _470_ = _466_ ? 1'h1 : dtlb_valids[0];
+ assign _471_ = _467_ ? 1'h1 : dtlb_valids[1];
+ assign _472_ = _468_ ? 1'h1 : dtlb_valids[2];
+ assign _473_ = _469_ ? 1'h1 : dtlb_valids[3];
+ assign _474_ = _054_ ? cache_valids[2] : cache_valids[0];
+ assign _475_ = _061_ ? cache_valids[3] : cache_valids[1];
+ assign _476_ = _070_ ? cache_valids[2] : cache_valids[0];
+ assign _477_ = _077_ ? cache_valids[3] : cache_valids[1];
+ assign _478_ = tlb_hit_way ? _082_ : _066_;
+ assign _479_ = _086_ ? _067_ : _083_;
+ assign _480_ = tlb_hit_way ? _085_ : _069_;
+ assign _481_ = _090_ ? cache_valids[2] : cache_valids[0];
+ assign _482_ = _095_ ? cache_valids[3] : cache_valids[1];
+ assign _485_ = _110_[2] ? _484_ : _483_;
+ assign _486_ = _119_ ? \maybe_plrus.plrus:0.plru_out : \maybe_plrus.plrus:1.plru_out ;
+ assign _487_ = _158_ ? \rams:0.dout : \rams:1.dout ;
+ assign _488_ = ~ _286_[2];
+ assign _489_ = ~ _286_[1];
+ assign _490_ = _488_ & _489_;
+ assign _491_ = _488_ & _286_[1];
+ assign _492_ = _286_[2] & _489_;
+ assign _493_ = _286_[2] & _286_[1];
+ assign _494_ = ~ _286_[0];
+ assign _495_ = _490_ & _494_;
+ assign _496_ = _490_ & _286_[0];
+ assign _497_ = _491_ & _494_;
+ assign _498_ = _491_ & _286_[0];
+ assign _499_ = _492_ & _494_;
+ assign _500_ = _492_ & _286_[0];
+ assign _501_ = _493_ & _494_;
+ assign _502_ = _493_ & _286_[0];
+ assign _503_ = _495_ ? 1'h1 : _437_[322];
+ assign _504_ = _496_ ? 1'h1 : _437_[323];
+ assign _505_ = _497_ ? 1'h1 : _437_[324];
+ assign _506_ = _498_ ? 1'h1 : _437_[325];
+ assign _507_ = _499_ ? 1'h1 : _437_[326];
+ assign _508_ = _500_ ? 1'h1 : _437_[327];
+ assign _509_ = _501_ ? 1'h1 : _437_[328];
+ assign _510_ = _502_ ? 1'h1 : _437_[329];
+ assign _511_ = ~ _306_;
+ assign _512_ = ~ _437_[313];
+ assign _513_ = _511_ & _512_;
+ assign _514_ = _511_ & _437_[313];
+ assign _515_ = _306_ & _512_;
+ assign _516_ = _306_ & _437_[313];
+ assign _517_ = _513_ ? 1'h1 : cache_valids[0];
+ assign _518_ = _514_ ? 1'h1 : cache_valids[1];
+ assign _519_ = _515_ ? 1'h1 : cache_valids[2];
+ assign _520_ = _516_ ? 1'h1 : cache_valids[3];
+ plru_2 \maybe_plrus.plrus:0.plru (
+ .acc(_198_[0]),
+ .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus:0.plru_out ),
+ .rst(rst)
+ );
+ plru_2 \maybe_plrus.plrus:1.plru (
+ .acc(_198_[0]),
+ .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus:1.plru_out ),
+ .rst(rst)
+ );
+ plru_2 \maybe_tlb_plrus.tlb_plrus:0.tlb_plru (
+ .acc(_198_[5]),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_2 \maybe_tlb_plrus.tlb_plrus:1.tlb_plru (
+ .acc(_198_[5]),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ),
+ .rst(rst)
+ );
+ cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 \rams:0.way (
+ .clk(clk),
+ .rd_addr(early_req_row),
+ .rd_data(\rams:0.dout ),
+ .rd_en(1'h1),
+ .wr_addr(\rams:0.wr_addr ),
+ .wr_data(\rams:0.wr_data ),
+ .wr_sel(\rams:0.wr_sel_m )
+ );
+ cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 \rams:1.way (
+ .clk(clk),
+ .rd_addr(early_req_row),
+ .rd_data(\rams:1.dout ),
+ .rd_en(1'h1),
+ .wr_addr(\rams:1.wr_addr ),
+ .wr_data(\rams:1.wr_data ),
+ .wr_sel(\rams:1.wr_sel_m )
+ );
+ assign d_out = { _200_[1], _199_, _167_, _166_, _165_, _164_, _163_, _162_, _161_, _160_, _159_, _437_[335] };
+ assign m_out = { _166_, _165_, _164_, _163_, _162_, _161_, _160_, _159_, _200_[0], _438_, 1'h0 };
+ assign stall_out = r0_stall;
+ assign wishbone_out = _437_[263:157];
+endmodule
diff --git a/verilog/rtl/icache.v b/verilog/rtl/icache.v
new file mode 100644
index 0000000..bef804f
--- /dev/null
+++ b/verilog/rtl/icache.v
@@ -0,0 +1,1027 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+module plru_1(clk, rst, acc, acc_en, lru);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ input acc;
+ input acc_en;
+ input clk;
+ output lru;
+ input rst;
+ reg [1:0] tree;
+ assign _0_ = ~ acc;
+ assign _1_ = acc_en ? _0_ : tree[1];
+ assign _2_ = rst ? 1'h0 : tree[0];
+ assign _3_ = rst ? 1'h0 : _1_;
+ always @(posedge clk)
+ tree <= { _3_, _2_ };
+ assign lru = tree[1];
+endmodule
+
+module cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
+ wire [127:0] _00_;
+ wire [7:0] _01_;
+ wire [127:0] _02_;
+ wire [7:0] _03_;
+ wire [127:0] _04_;
+ wire [7:0] _05_;
+ wire [127:0] _06_;
+ wire [7:0] _07_;
+ wire [127:0] _08_;
+ wire [7:0] _09_;
+ wire [127:0] _10_;
+ wire [7:0] _11_;
+ wire [127:0] _12_;
+ wire [7:0] _13_;
+ wire [127:0] _14_;
+ wire [7:0] _15_;
+ input clk;
+ input [3:0] rd_addr;
+ output [63:0] rd_data;
+ input rd_en;
+ input [3:0] wr_addr;
+ input [63:0] wr_data;
+ input [7:0] wr_sel;
+ reg [7:0] \$mem$\20409 [15:0];
+ reg [7:0] \$mem$\20410 [15:0];
+ reg [7:0] \$mem$\20411 [15:0];
+ reg [7:0] \$mem$\20412 [15:0];
+ reg [7:0] \$mem$\20413 [15:0];
+ reg [7:0] \$mem$\20414 [15:0];
+ reg [7:0] \$mem$\20415 [15:0];
+ reg [7:0] \$mem$\20416 [15:0];
+ (* ram_style = "block" *)
+ reg [7:0] \20409 [15:0];
+ reg [7:0] _16_;
+ always @(posedge clk) begin
+ if (rd_en) _16_ <= \20409 [rd_addr];
+ if (wr_sel[0]) \20409 [wr_addr] <= wr_data[7:0];
+ end
+ assign _01_ = _16_;
+ (* ram_style = "block" *)
+ reg [7:0] \20410 [15:0];
+ reg [7:0] _17_;
+ always @(posedge clk) begin
+ if (rd_en) _17_ <= \20410 [rd_addr];
+ if (wr_sel[1]) \20410 [wr_addr] <= wr_data[15:8];
+ end
+ assign _03_ = _17_;
+ (* ram_style = "block" *)
+ reg [7:0] \20411 [15:0];
+ reg [7:0] _18_;
+ always @(posedge clk) begin
+ if (rd_en) _18_ <= \20411 [rd_addr];
+ if (wr_sel[2]) \20411 [wr_addr] <= wr_data[23:16];
+ end
+ assign _05_ = _18_;
+ (* ram_style = "block" *)
+ reg [7:0] \20412 [15:0];
+ reg [7:0] _19_;
+ always @(posedge clk) begin
+ if (rd_en) _19_ <= \20412 [rd_addr];
+ if (wr_sel[3]) \20412 [wr_addr] <= wr_data[31:24];
+ end
+ assign _07_ = _19_;
+ (* ram_style = "block" *)
+ reg [7:0] \20413 [15:0];
+ reg [7:0] _20_;
+ always @(posedge clk) begin
+ if (rd_en) _20_ <= \20413 [rd_addr];
+ if (wr_sel[4]) \20413 [wr_addr] <= wr_data[39:32];
+ end
+ assign _09_ = _20_;
+ (* ram_style = "block" *)
+ reg [7:0] \20414 [15:0];
+ reg [7:0] _21_;
+ always @(posedge clk) begin
+ if (rd_en) _21_ <= \20414 [rd_addr];
+ if (wr_sel[5]) \20414 [wr_addr] <= wr_data[47:40];
+ end
+ assign _11_ = _21_;
+ (* ram_style = "block" *)
+ reg [7:0] \20415 [15:0];
+ reg [7:0] _22_;
+ always @(posedge clk) begin
+ if (rd_en) _22_ <= \20415 [rd_addr];
+ if (wr_sel[6]) \20415 [wr_addr] <= wr_data[55:48];
+ end
+ assign _13_ = _22_;
+ (* ram_style = "block" *)
+ reg [7:0] \20416 [15:0];
+ reg [7:0] _23_;
+ always @(posedge clk) begin
+ if (rd_en) _23_ <= \20416 [rd_addr];
+ if (wr_sel[7]) \20416 [wr_addr] <= wr_data[63:56];
+ end
+ assign _15_ = _23_;
+ assign rd_data = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
+endmodule
+
+module icache(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, rst, i_in, m_in, stall_in, flush_in, inval_in, wishbone_in, i_out, stall_out, wishbone_out);
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire [1:0] _010_;
+ wire _011_;
+ wire [1:0] _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire [1:0] _016_;
+ wire [1:0] _017_;
+ wire _018_;
+ wire _019_;
+ wire [1:0] _020_;
+ wire [1:0] _021_;
+ wire [3:0] _022_;
+ wire [3:0] _023_;
+ wire [3:0] _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire [2:0] _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire [2:0] _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire [64:0] _082_;
+ reg [66:0] _083_;
+ wire [3:0] _084_;
+ wire _085_;
+ wire [2:0] _086_;
+ wire [33:0] _087_;
+ wire [1:0] _088_;
+ wire [58:0] _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire [199:0] _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire [199:0] _100_;
+ wire [199:0] _101_;
+ wire [3:0] _102_;
+ wire [1:0] _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire [2:0] _112_;
+ wire [31:0] _113_;
+ wire _114_;
+ wire _115_;
+ wire [2:0] _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire [3:0] _122_;
+ wire [1:0] _123_;
+ wire _124_;
+ wire [2:0] _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire [3:0] _129_;
+ wire [7:0] _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire [199:0] _134_;
+ wire [3:0] _135_;
+ wire [1:0] _136_;
+ wire [31:0] _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire [3:0] _142_;
+ wire [53:0] _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire [199:0] _152_;
+ wire [3:0] _153_;
+ wire [33:0] _154_;
+ wire [71:0] _155_;
+ wire [1:0] _156_;
+ wire _157_;
+ wire [67:0] _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ reg [177:0] _167_;
+ wire [255:0] _168_;
+ wire [63:0] _169_;
+ wire [199:0] _170_;
+ wire [49:0] _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire [99:0] _197_;
+ wire _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire [99:0] _202_;
+ wire _203_;
+ wire [63:0] _204_;
+ wire [31:0] _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire [99:0] _216_;
+ wire _217_;
+ wire [99:0] _218_;
+ wire [99:0] _219_;
+ wire [99:0] _220_;
+ wire _221_;
+ wire [99:0] _222_;
+ wire [99:0] _223_;
+ wire _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire _233_;
+ wire _234_;
+ wire _235_;
+ wire _236_;
+ wire _237_;
+ wire _238_;
+ wire _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire _245_;
+ wire _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire _250_;
+ wire _251_;
+ wire _252_;
+ wire _253_;
+ wire _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire _259_;
+ wire _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire _264_;
+ wire _265_;
+ wire _266_;
+ wire access_ok;
+ reg [199:0] cache_tags;
+ reg [3:0] cache_valids;
+ input clk;
+ wire eaa_priv;
+ input flush_in;
+ input [69:0] i_in;
+ output [98:0] i_out;
+ input inval_in;
+ reg [3:0] itlb_valids;
+ input [130:0] m_in;
+ wire \maybe_plrus.plrus:0.plru_acc_en ;
+ wire \maybe_plrus.plrus:0.plru_out ;
+ wire \maybe_plrus.plrus:1.plru_acc_en ;
+ wire \maybe_plrus.plrus:1.plru_out ;
+ wire priv_fault;
+ wire ra_valid;
+ wire \rams:0.do_read ;
+ wire \rams:0.do_write ;
+ wire [63:0] \rams:0.dout ;
+ wire [63:0] \rams:0.wr_dat ;
+ wire \rams:1.do_read ;
+ wire \rams:1.do_write ;
+ wire [63:0] \rams:1.dout ;
+ wire [63:0] \rams:1.wr_dat ;
+ wire [55:0] real_addr;
+ wire replace_way;
+ wire req_hit_way;
+ wire req_is_hit;
+ wire req_is_miss;
+ input rst;
+ input stall_in;
+ output stall_out;
+ wire [1:0] tlb_req_index;
+ wire use_previous;
+ input [65:0] wishbone_in;
+ output [106:0] wishbone_out;
+ reg [63:0] \$mem$\8207 [3:0];
+ reg [49:0] \$mem$\8210 [3:0];
+ (* ram_style = "distributed" *)
+ reg [63:0] \8207 [3:0];
+ always @(posedge clk) begin
+ if (_032_) \8207 [_017_] <= m_in[130:67];
+ end
+ assign _169_ = \8207 [tlb_req_index];
+ (* ram_style = "distributed" *)
+ reg [49:0] \8210 [3:0];
+ always @(posedge clk) begin
+ if (_028_) \8210 [_017_] <= m_in[66:17];
+ end
+ assign _171_ = \8210 [tlb_req_index];
+ assign _257_ = _012_[0] ? itlb_valids[1] : itlb_valids[0];
+ assign _258_ = _041_[0] ? _167_[170] : _167_[169];
+ assign _259_ = _041_[0] ? _167_[174] : _167_[173];
+ assign _260_ = _055_[0] ? _167_[170] : _167_[169];
+ assign _261_ = _055_[0] ? _167_[174] : _167_[173];
+ assign _262_ = _012_[0] ? itlb_valids[3] : itlb_valids[2];
+ assign _263_ = _041_[0] ? _167_[172] : _167_[171];
+ assign _264_ = _041_[0] ? _167_[176] : _167_[175];
+ assign _265_ = _055_[0] ? _167_[172] : _167_[171];
+ assign _266_ = _055_[0] ? _167_[176] : _167_[175];
+ assign _172_ = _012_[1] ? _262_ : _257_;
+ assign _194_ = _041_[1] ? _263_ : _258_;
+ assign _195_ = _041_[1] ? _264_ : _259_;
+ assign _199_ = _055_[1] ? _265_ : _260_;
+ assign _200_ = _055_[1] ? _266_ : _261_;
+ assign _000_ = ~ _167_[164];
+ assign \rams:0.wr_dat = _000_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
+ assign _001_ = stall_in | use_previous;
+ assign \rams:0.do_read = ~ _001_;
+ assign _002_ = { 31'h00000000, replace_way } == 32'd0;
+ assign _003_ = wishbone_in[64] & _002_;
+ assign \rams:0.do_write = _003_ ? 1'h1 : 1'h0;
+ assign _004_ = ~ _167_[164];
+ assign \rams:1.wr_dat = _004_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
+ assign _005_ = stall_in | use_previous;
+ assign \rams:1.do_read = ~ _005_;
+ assign _006_ = { 31'h00000000, replace_way } == 32'd1;
+ assign _007_ = wishbone_in[64] & _006_;
+ assign \rams:1.do_write = _007_ ? 1'h1 : 1'h0;
+ assign _008_ = { 31'h00000000, _083_[7] } == 32'd0;
+ assign \maybe_plrus.plrus:0.plru_acc_en = _008_ ? _083_[66] : 1'h0;
+ assign _009_ = { 31'h00000000, _083_[7] } == 32'd1;
+ assign \maybe_plrus.plrus:1.plru_acc_en = _009_ ? _083_[66] : 1'h0;
+ assign _010_ = i_in[19:18] ^ i_in[21:20];
+ assign tlb_req_index = _010_ ^ i_in[23:22];
+ assign _011_ = _171_ == i_in[69:20];
+ assign _012_ = 2'h3 - tlb_req_index;
+ assign _013_ = _011_ ? _172_ : 1'h0;
+ assign eaa_priv = i_in[1] ? _169_[3] : 1'h1;
+ assign real_addr = i_in[1] ? { _169_[55:12], i_in[17:6] } : i_in[61:6];
+ assign ra_valid = i_in[1] ? _013_ : 1'h1;
+ assign _014_ = ~ i_in[2];
+ assign priv_fault = eaa_priv & _014_;
+ assign _015_ = ~ priv_fault;
+ assign access_ok = ra_valid & _015_;
+ assign _016_ = m_in[16:15] ^ m_in[18:17];
+ assign _017_ = _016_ ^ m_in[20:19];
+ assign _018_ = m_in[1] & m_in[2];
+ assign _019_ = rst | _018_;
+ assign _020_ = 2'h3 - _017_;
+ assign _021_ = 2'h3 - _017_;
+ assign _022_ = m_in[0] ? { _192_, _191_, _190_, _189_ } : itlb_valids;
+ assign _023_ = m_in[1] ? { _182_, _181_, _180_, _179_ } : _022_;
+ assign _024_ = _019_ ? 4'h0 : _023_;
+ always @(posedge clk)
+ itlb_valids <= _024_;
+ assign _025_ = ~ _019_;
+ assign _026_ = ~ m_in[1];
+ assign _027_ = _025_ & _026_;
+ assign _028_ = _027_ & m_in[0];
+ assign _029_ = ~ _019_;
+ assign _030_ = ~ m_in[1];
+ assign _031_ = _029_ & _030_;
+ assign _032_ = _031_ & m_in[0];
+ assign _033_ = i_in[8] != 1'h0;
+ assign _034_ = i_in[5] & _083_[66];
+ assign use_previous = _033_ ? _034_ : 1'h0;
+ assign _035_ = 1'h1 - i_in[12];
+ assign _036_ = _167_[1:0] == 2'h2;
+ assign _037_ = { 31'h00000000, i_in[12] } == { 31'h00000000, _167_[110] };
+ assign _038_ = _036_ & _037_;
+ assign _039_ = 32'd0 == { 31'h00000000, _167_[109] };
+ assign _040_ = _038_ & _039_;
+ assign _041_ = 3'h7 - i_in[11:9];
+ assign _042_ = _040_ & _196_;
+ assign _043_ = _193_ | _042_;
+ assign _044_ = i_in[0] & _043_;
+ assign _045_ = 1'h1 - i_in[12];
+ assign _046_ = _197_[49:0] == { i_in[3], real_addr[55:7] };
+ assign _047_ = _046_ ? 1'h1 : 1'h0;
+ assign _048_ = _044_ ? _047_ : 1'h0;
+ assign _049_ = 1'h1 - i_in[12];
+ assign _050_ = _167_[1:0] == 2'h2;
+ assign _051_ = { 31'h00000000, i_in[12] } == { 31'h00000000, _167_[110] };
+ assign _052_ = _050_ & _051_;
+ assign _053_ = 32'd1 == { 31'h00000000, _167_[109] };
+ assign _054_ = _052_ & _053_;
+ assign _055_ = 3'h7 - i_in[11:9];
+ assign _056_ = _054_ & _201_;
+ assign _057_ = _198_ | _056_;
+ assign _058_ = i_in[0] & _057_;
+ assign _059_ = 1'h1 - i_in[12];
+ assign _060_ = _202_[99:50] == { i_in[3], real_addr[55:7] };
+ assign _061_ = _063_ ? 1'h1 : _048_;
+ assign _062_ = _060_ ? 1'h1 : 1'h0;
+ assign _063_ = _058_ & _060_;
+ assign req_hit_way = _058_ ? _062_ : 1'h0;
+ assign _064_ = i_in[0] & access_ok;
+ assign _065_ = ~ flush_in;
+ assign _066_ = _064_ & _065_;
+ assign _067_ = ~ rst;
+ assign _068_ = _066_ & _067_;
+ assign _069_ = ~ _061_;
+ assign req_is_hit = _068_ ? _061_ : 1'h0;
+ assign req_is_miss = _068_ ? _069_ : 1'h0;
+ assign _070_ = _167_[1:0] == 2'h1;
+ assign _071_ = 1'h1 - _167_[110];
+ assign replace_way = _070_ ? _203_ : _167_[109];
+ assign _072_ = 1'h1 - _083_[0];
+ assign _073_ = _061_ & access_ok;
+ assign _074_ = ~ _073_;
+ assign _075_ = stall_in | use_previous;
+ assign _076_ = rst | flush_in;
+ assign _077_ = _076_ ? 1'h0 : _083_[66];
+ assign _078_ = req_is_hit ? req_hit_way : _083_[0];
+ assign _079_ = _075_ ? _083_[0] : _078_;
+ assign _080_ = _075_ ? _077_ : req_is_hit;
+ assign _081_ = ~ stall_in;
+ assign _082_ = _081_ ? { i_in[4], i_in[69:6] } : _083_[65:1];
+ always @(posedge clk)
+ _083_ <= { _080_, _082_, _079_ };
+ assign _084_ = inval_in ? 4'h0 : cache_valids;
+ assign _085_ = inval_in ? 1'h0 : _167_[165];
+ assign _086_ = real_addr[5:3] - 3'h1;
+ assign _087_ = req_is_miss ? { real_addr[31:3], 5'h01 } : _167_[33:0];
+ assign _088_ = req_is_miss ? 2'h3 : _167_[107:106];
+ assign _089_ = req_is_miss ? { _086_, 1'h1, i_in[3], real_addr[55:3], i_in[12] } : { _167_[168:166], _085_, _167_[164:110] };
+ assign _090_ = _167_[1:0] == 2'h0;
+ assign _091_ = _167_[1:0] == 2'h1;
+ assign _092_ = 1'h1 - i_in[12];
+ assign _093_ = 32'd0 == { 31'h00000000, replace_way };
+ assign _094_ = 1'h1 - _167_[110];
+ assign _095_ = 1'h1 - _167_[110];
+ assign _096_ = _093_ ? { _219_, _218_ } : cache_tags;
+ assign _097_ = 32'd1 == { 31'h00000000, replace_way };
+ assign _098_ = 1'h1 - _167_[110];
+ assign _099_ = 1'h1 - _167_[110];
+ assign _100_ = _097_ ? { _223_, _222_ } : _096_;
+ assign _101_ = _091_ ? _100_ : cache_tags;
+ assign _102_ = _091_ ? { _215_, _214_, _213_, _212_ } : _084_;
+ assign _103_ = _091_ ? 2'h2 : _167_[1:0];
+ assign _104_ = _091_ ? replace_way : _167_[109];
+ assign _105_ = ~ _167_[107];
+ assign _106_ = ~ wishbone_in[65];
+ assign _107_ = ~ _105_;
+ assign _108_ = _106_ & _107_;
+ assign _109_ = _167_[7:5] == _167_[168:166];
+ assign _110_ = _114_ ? 1'h0 : _167_[107];
+ assign _111_ = _115_ ? 1'h1 : _105_;
+ assign _112_ = _167_[7:5] + 3'h1;
+ assign _113_ = _108_ ? { _167_[33:8], _112_, _167_[4:2] } : _167_[33:2];
+ assign _114_ = _108_ & _109_;
+ assign _115_ = _108_ & _109_;
+ assign _116_ = 3'h7 - _167_[113:111];
+ assign _117_ = _167_[113:111] == _167_[168:166];
+ assign _118_ = _111_ & _117_;
+ assign _119_ = 1'h1 - _167_[110];
+ assign _120_ = ~ inval_in;
+ assign _121_ = _167_[165] & _120_;
+ assign _122_ = _126_ ? { _256_, _255_, _254_, _253_ } : _102_;
+ assign _123_ = _127_ ? 2'h0 : _103_;
+ assign _124_ = _128_ ? 1'h0 : _167_[106];
+ assign _125_ = _167_[113:111] + 3'h1;
+ assign _126_ = wishbone_in[64] & _118_;
+ assign _127_ = wishbone_in[64] & _118_;
+ assign _128_ = wishbone_in[64] & _118_;
+ assign _129_ = wishbone_in[64] ? { _167_[114], _125_ } : _167_[114:111];
+ assign _130_ = wishbone_in[64] ? { _246_, _245_, _244_, _243_, _242_, _241_, _240_, _239_ } : _167_[176:169];
+ assign _131_ = _167_[1:0] == 2'h1;
+ assign _132_ = _167_[1:0] == 2'h2;
+ assign _133_ = _131_ | _132_;
+ function [199:0] \8094 ;
+ input [199:0] a;
+ input [399:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8094 = b[199:0];
+ 2'b1?:
+ \8094 = b[399:200];
+ default:
+ \8094 = a;
+ endcase
+ endfunction
+ assign _134_ = \8094 (200'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _101_, cache_tags }, { _133_, _090_ });
+ function [3:0] \8096 ;
+ input [3:0] a;
+ input [7:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8096 = b[3:0];
+ 2'b1?:
+ \8096 = b[7:4];
+ default:
+ \8096 = a;
+ endcase
+ endfunction
+ assign _135_ = \8096 (4'hx, { _122_, _084_ }, { _133_, _090_ });
+ function [1:0] \8099 ;
+ input [1:0] a;
+ input [3:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8099 = b[1:0];
+ 2'b1?:
+ \8099 = b[3:2];
+ default:
+ \8099 = a;
+ endcase
+ endfunction
+ assign _136_ = \8099 (2'hx, { _123_, _087_[1:0] }, { _133_, _090_ });
+ function [31:0] \8102 ;
+ input [31:0] a;
+ input [63:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8102 = b[31:0];
+ 2'b1?:
+ \8102 = b[63:32];
+ default:
+ \8102 = a;
+ endcase
+ endfunction
+ assign _137_ = \8102 (32'hxxxxxxxx, { _113_, _087_[33:2] }, { _133_, _090_ });
+ function [0:0] \8105 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8105 = b[0:0];
+ 2'b1?:
+ \8105 = b[1:1];
+ default:
+ \8105 = a;
+ endcase
+ endfunction
+ assign _138_ = \8105 (1'hx, { _124_, _088_[0] }, { _133_, _090_ });
+ function [0:0] \8108 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8108 = b[0:0];
+ 2'b1?:
+ \8108 = b[1:1];
+ default:
+ \8108 = a;
+ endcase
+ endfunction
+ assign _139_ = \8108 (1'hx, { _110_, _088_[1] }, { _133_, _090_ });
+ function [0:0] \8111 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8111 = b[0:0];
+ 2'b1?:
+ \8111 = b[1:1];
+ default:
+ \8111 = a;
+ endcase
+ endfunction
+ assign _140_ = \8111 (1'hx, { _104_, _167_[109] }, { _133_, _090_ });
+ function [0:0] \8115 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8115 = b[0:0];
+ 2'b1?:
+ \8115 = b[1:1];
+ default:
+ \8115 = a;
+ endcase
+ endfunction
+ assign _141_ = \8115 (1'hx, { _167_[110], _089_[0] }, { _133_, _090_ });
+ function [3:0] \8118 ;
+ input [3:0] a;
+ input [7:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8118 = b[3:0];
+ 2'b1?:
+ \8118 = b[7:4];
+ default:
+ \8118 = a;
+ endcase
+ endfunction
+ assign _142_ = \8118 (4'hx, { _129_, _089_[4:1] }, { _133_, _090_ });
+ function [53:0] \8124 ;
+ input [53:0] a;
+ input [107:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8124 = b[53:0];
+ 2'b1?:
+ \8124 = b[107:54];
+ default:
+ \8124 = a;
+ endcase
+ endfunction
+ assign _143_ = \8124 (54'hxxxxxxxxxxxxxx, { _167_[168:166], _085_, _167_[164:115], _089_[58:5] }, { _133_, _090_ });
+ function [0:0] \8127 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8127 = b[0:0];
+ 2'b1?:
+ \8127 = b[1:1];
+ default:
+ \8127 = a;
+ endcase
+ endfunction
+ assign _144_ = \8127 (1'hx, { _130_[0], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8130 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8130 = b[0:0];
+ 2'b1?:
+ \8130 = b[1:1];
+ default:
+ \8130 = a;
+ endcase
+ endfunction
+ assign _145_ = \8130 (1'hx, { _130_[1], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8133 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8133 = b[0:0];
+ 2'b1?:
+ \8133 = b[1:1];
+ default:
+ \8133 = a;
+ endcase
+ endfunction
+ assign _146_ = \8133 (1'hx, { _130_[2], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8136 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8136 = b[0:0];
+ 2'b1?:
+ \8136 = b[1:1];
+ default:
+ \8136 = a;
+ endcase
+ endfunction
+ assign _147_ = \8136 (1'hx, { _130_[3], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8139 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8139 = b[0:0];
+ 2'b1?:
+ \8139 = b[1:1];
+ default:
+ \8139 = a;
+ endcase
+ endfunction
+ assign _148_ = \8139 (1'hx, { _130_[4], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8142 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8142 = b[0:0];
+ 2'b1?:
+ \8142 = b[1:1];
+ default:
+ \8142 = a;
+ endcase
+ endfunction
+ assign _149_ = \8142 (1'hx, { _130_[5], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8145 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8145 = b[0:0];
+ 2'b1?:
+ \8145 = b[1:1];
+ default:
+ \8145 = a;
+ endcase
+ endfunction
+ assign _150_ = \8145 (1'hx, { _130_[6], 1'h0 }, { _133_, _090_ });
+ function [0:0] \8148 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \8148 = b[0:0];
+ 2'b1?:
+ \8148 = b[1:1];
+ default:
+ \8148 = a;
+ endcase
+ endfunction
+ assign _151_ = \8148 (1'hx, { _130_[7], 1'h0 }, { _133_, _090_ });
+ assign _152_ = rst ? cache_tags : _134_;
+ assign _153_ = rst ? 4'h0 : _135_;
+ assign _154_ = rst ? 34'h000000000 : { _137_, _136_ };
+ assign _155_ = rst ? 72'hff0000000000000000 : _167_[105:34];
+ assign _156_ = rst ? 2'h0 : { _139_, _138_ };
+ assign _157_ = rst ? 1'h0 : _167_[108];
+ assign _158_ = rst ? _167_[176:109] : { _151_, _150_, _149_, _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_ };
+ assign _159_ = rst | flush_in;
+ assign _160_ = _159_ | m_in[0];
+ assign _161_ = ~ access_ok;
+ assign _162_ = i_in[0] & _161_;
+ assign _163_ = ~ stall_in;
+ assign _164_ = _162_ & _163_;
+ assign _165_ = _164_ ? 1'h1 : _167_[177];
+ assign _166_ = _160_ ? 1'h0 : _165_;
+ always @(posedge clk)
+ cache_tags <= _152_;
+ always @(posedge clk)
+ cache_valids <= _153_;
+ always @(posedge clk)
+ _167_ <= { _166_, _158_, _157_, _156_, _155_, _154_ };
+ assign _173_ = ~ _020_[1];
+ assign _174_ = ~ _020_[0];
+ assign _175_ = _173_ & _174_;
+ assign _176_ = _173_ & _020_[0];
+ assign _177_ = _020_[1] & _174_;
+ assign _178_ = _020_[1] & _020_[0];
+ assign _179_ = _175_ ? 1'h0 : itlb_valids[0];
+ assign _180_ = _176_ ? 1'h0 : itlb_valids[1];
+ assign _181_ = _177_ ? 1'h0 : itlb_valids[2];
+ assign _182_ = _178_ ? 1'h0 : itlb_valids[3];
+ assign _183_ = ~ _021_[1];
+ assign _184_ = ~ _021_[0];
+ assign _185_ = _183_ & _184_;
+ assign _186_ = _183_ & _021_[0];
+ assign _187_ = _021_[1] & _184_;
+ assign _188_ = _021_[1] & _021_[0];
+ assign _189_ = _185_ ? 1'h1 : itlb_valids[0];
+ assign _190_ = _186_ ? 1'h1 : itlb_valids[1];
+ assign _191_ = _187_ ? 1'h1 : itlb_valids[2];
+ assign _192_ = _188_ ? 1'h1 : itlb_valids[3];
+ assign _193_ = _035_ ? cache_valids[2] : cache_valids[0];
+ assign _196_ = _041_[2] ? _195_ : _194_;
+ assign _197_ = _045_ ? cache_tags[199:100] : cache_tags[99:0];
+ assign _198_ = _049_ ? cache_valids[3] : cache_valids[1];
+ assign _201_ = _055_[2] ? _200_ : _199_;
+ assign _202_ = _059_ ? cache_tags[199:100] : cache_tags[99:0];
+ assign _203_ = _071_ ? \maybe_plrus.plrus:0.plru_out : \maybe_plrus.plrus:1.plru_out ;
+ assign _204_ = _072_ ? \rams:0.dout : \rams:1.dout ;
+ assign _205_ = _083_[3] ? _204_[63:32] : _204_[31:0];
+ assign _206_ = ~ _092_;
+ assign _207_ = ~ replace_way;
+ assign _208_ = _206_ & _207_;
+ assign _209_ = _206_ & replace_way;
+ assign _210_ = _092_ & _207_;
+ assign _211_ = _092_ & replace_way;
+ assign _212_ = _208_ ? 1'h0 : _084_[0];
+ assign _213_ = _209_ ? 1'h0 : _084_[1];
+ assign _214_ = _210_ ? 1'h0 : _084_[2];
+ assign _215_ = _211_ ? 1'h0 : _084_[3];
+ assign _216_ = _094_ ? cache_tags[199:100] : cache_tags[99:0];
+ assign _217_ = ~ _095_;
+ assign _218_ = _217_ ? { _216_[99:50], _167_[164:115] } : cache_tags[99:0];
+ assign _219_ = _095_ ? { _216_[99:50], _167_[164:115] } : cache_tags[199:100];
+ assign _220_ = _098_ ? cache_tags[199:100] : cache_tags[99:0];
+ assign _221_ = ~ _099_;
+ assign _222_ = _221_ ? { _167_[164:115], _220_[49:0] } : _096_[99:0];
+ assign _223_ = _099_ ? { _167_[164:115], _220_[49:0] } : _096_[199:100];
+ assign _224_ = ~ _116_[2];
+ assign _225_ = ~ _116_[1];
+ assign _226_ = _224_ & _225_;
+ assign _227_ = _224_ & _116_[1];
+ assign _228_ = _116_[2] & _225_;
+ assign _229_ = _116_[2] & _116_[1];
+ assign _230_ = ~ _116_[0];
+ assign _231_ = _226_ & _230_;
+ assign _232_ = _226_ & _116_[0];
+ assign _233_ = _227_ & _230_;
+ assign _234_ = _227_ & _116_[0];
+ assign _235_ = _228_ & _230_;
+ assign _236_ = _228_ & _116_[0];
+ assign _237_ = _229_ & _230_;
+ assign _238_ = _229_ & _116_[0];
+ assign _239_ = _231_ ? 1'h1 : _167_[169];
+ assign _240_ = _232_ ? 1'h1 : _167_[170];
+ assign _241_ = _233_ ? 1'h1 : _167_[171];
+ assign _242_ = _234_ ? 1'h1 : _167_[172];
+ assign _243_ = _235_ ? 1'h1 : _167_[173];
+ assign _244_ = _236_ ? 1'h1 : _167_[174];
+ assign _245_ = _237_ ? 1'h1 : _167_[175];
+ assign _246_ = _238_ ? 1'h1 : _167_[176];
+ assign _247_ = ~ _119_;
+ assign _248_ = ~ replace_way;
+ assign _249_ = _247_ & _248_;
+ assign _250_ = _247_ & replace_way;
+ assign _251_ = _119_ & _248_;
+ assign _252_ = _119_ & replace_way;
+ assign _253_ = _249_ ? _121_ : _102_[0];
+ assign _254_ = _250_ ? _121_ : _102_[1];
+ assign _255_ = _251_ ? _121_ : _102_[2];
+ assign _256_ = _252_ ? _121_ : _102_[3];
+ plru_1 \maybe_plrus.plrus:0.plru (
+ .acc(_083_[0]),
+ .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus:0.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus:1.plru (
+ .acc(_083_[0]),
+ .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus:1.plru_out ),
+ .rst(rst)
+ );
+ cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:0.way (
+ .clk(clk),
+ .rd_addr(i_in[12:9]),
+ .rd_data(\rams:0.dout ),
+ .rd_en(\rams:0.do_read ),
+ .wr_addr(_167_[114:111]),
+ .wr_data(\rams:0.wr_dat ),
+ .wr_sel({ \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write })
+ );
+ cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:1.way (
+ .clk(clk),
+ .rd_addr(i_in[12:9]),
+ .rd_data(\rams:1.dout ),
+ .rd_en(\rams:1.do_read ),
+ .wr_addr(_167_[114:111]),
+ .wr_data(\rams:1.wr_dat ),
+ .wr_sel({ \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write })
+ );
+ assign i_out = { _205_, _083_[64:1], _167_[177], _083_[65], _083_[66] };
+ assign stall_out = _074_;
+ assign wishbone_out = _167_[108:2];
+endmodule
diff --git a/verilog/rtl/microwatt.v b/verilog/rtl/microwatt.v
new file mode 100644
index 0000000..e4df252
--- /dev/null
+++ b/verilog/rtl/microwatt.v
@@ -0,0 +1,30284 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+/* JTAG */
+`include "tap_top.v"
+
+/* UART */
+`include "raminfr.v"
+`include "uart_receiver.v"
+`include "uart_rfifo.v"
+`include "uart_tfifo.v"
+`include "uart_transmitter.v"
+`include "uart_defines.v"
+`include "uart_regs.v"
+`include "uart_sync_flops.v"
+`include "uart_wb.v"
+`include "uart_top.v"
+
+
+
+module control_1(clk, rst, complete_in, valid_in, flush_in, busy_in, deferred, sgl_pipe_in, stop_mark_in, gpr_write_valid_in, gpr_write_in, gpr_bypassable, update_gpr_write_valid, update_gpr_write_reg, gpr_a_read_valid_in, gpr_a_read_in, gpr_b_read_valid_in, gpr_b_read_in, gpr_c_read_valid_in, gpr_c_read_in, cr_read_in, cr_write_in, cr_bypassable, valid_out, stall_out, stopped_out, gpr_bypass_a, gpr_bypass_b, gpr_bypass_c, cr_bypass);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [31:0] _06_;
+ wire [2:0] _07_;
+ wire [2:0] _08_;
+ wire [4:0] _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire [1:0] _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire [1:0] _20_;
+ wire [1:0] _21_;
+ wire _22_;
+ wire [1:0] _23_;
+ wire [1:0] _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire [1:0] _28_;
+ wire [1:0] _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire [2:0] _33_;
+ wire _34_;
+ wire [1:0] _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire [1:0] _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire [1:0] _44_;
+ wire [1:0] _45_;
+ wire _46_;
+ wire _47_;
+ wire [1:0] _48_;
+ wire [2:0] _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire [31:0] _53_;
+ wire [2:0] _54_;
+ wire _55_;
+ wire _56_;
+ input busy_in;
+ input clk;
+ input complete_in;
+ output cr_bypass;
+ input cr_bypassable;
+ input cr_read_in;
+ wire cr_stall_out;
+ input cr_write_in;
+ wire cr_write_valid;
+ input deferred;
+ input flush_in;
+ input [6:0] gpr_a_read_in;
+ input gpr_a_read_valid_in;
+ input [6:0] gpr_b_read_in;
+ input gpr_b_read_valid_in;
+ output gpr_bypass_a;
+ output gpr_bypass_b;
+ output gpr_bypass_c;
+ input gpr_bypassable;
+ input [6:0] gpr_c_read_in;
+ input gpr_c_read_valid_in;
+ input [6:0] gpr_write_in;
+ wire gpr_write_valid;
+ input gpr_write_valid_in;
+ reg [4:0] r_int = 5'h00;
+ input rst;
+ input sgl_pipe_in;
+ wire stall_a_out;
+ wire stall_b_out;
+ wire stall_c_out;
+ output stall_out;
+ input stop_mark_in;
+ output stopped_out;
+ input [6:0] update_gpr_write_reg;
+ input update_gpr_write_valid;
+ input valid_in;
+ output valid_out;
+ always @(posedge clk)
+ r_int <= { _54_, _48_ };
+ assign _04_ = ~ flush_in;
+ assign _05_ = valid_in & _04_;
+ assign _06_ = { r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] } - 32'd1;
+ assign _07_ = complete_in ? _06_[2:0] : r_int[4:2];
+ assign _08_ = flush_in ? 3'h1 : _07_;
+ assign _09_ = rst ? 5'h00 : { _08_, r_int[1:0] };
+ assign _10_ = rst ? 1'h0 : _05_;
+ assign _11_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } == 32'd0;
+ assign _12_ = stop_mark_in & _11_;
+ assign _13_ = _12_ ? 1'h1 : 1'h0;
+ assign _14_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } != 32'd0;
+ assign _15_ = _14_ ? 2'h1 : 2'h2;
+ assign _16_ = _14_ ? 1'h1 : 1'h0;
+ assign _17_ = stall_a_out | stall_b_out;
+ assign _18_ = _17_ | stall_c_out;
+ assign _19_ = _18_ | cr_stall_out;
+ assign _20_ = rst ? 2'h0 : r_int[1:0];
+ assign _21_ = sgl_pipe_in ? _15_ : _20_;
+ assign _22_ = sgl_pipe_in ? _16_ : _19_;
+ assign _23_ = rst ? 2'h0 : r_int[1:0];
+ assign _24_ = _10_ ? _21_ : _23_;
+ assign _25_ = _10_ ? _22_ : 1'h0;
+ assign _26_ = r_int[1:0] == 2'h0;
+ assign _27_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } == 32'd0;
+ assign _28_ = rst ? 2'h0 : r_int[1:0];
+ assign _29_ = _27_ ? 2'h2 : _28_;
+ assign _30_ = _27_ ? 1'h0 : 1'h1;
+ assign _31_ = r_int[1:0] == 2'h1;
+ assign _32_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } == 32'd0;
+ assign _33_ = rst ? 3'h0 : _08_;
+ assign _34_ = { _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_ } != 32'd0;
+ assign _35_ = _34_ ? 2'h1 : 2'h2;
+ assign _36_ = _34_ ? 1'h1 : 1'h0;
+ assign _37_ = stall_a_out | stall_b_out;
+ assign _38_ = _37_ | stall_c_out;
+ assign _39_ = _38_ | cr_stall_out;
+ assign _40_ = _42_ ? _35_ : 2'h0;
+ assign _41_ = sgl_pipe_in ? _36_ : _39_;
+ assign _42_ = _10_ & sgl_pipe_in;
+ assign _43_ = _10_ ? _41_ : 1'h0;
+ assign _44_ = rst ? 2'h0 : r_int[1:0];
+ assign _45_ = _32_ ? _40_ : _44_;
+ assign _46_ = _32_ ? _43_ : 1'h1;
+ assign _47_ = r_int[1:0] == 2'h2;
+ function [1:0] \20544 ;
+ input [1:0] a;
+ input [5:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20544 = b[1:0];
+ 3'b?1?:
+ \20544 = b[3:2];
+ 3'b1??:
+ \20544 = b[5:4];
+ default:
+ \20544 = a;
+ endcase
+ endfunction
+ assign _48_ = \20544 (2'hx, { _45_, _29_, _24_ }, { _47_, _31_, _26_ });
+ assign _49_ = rst ? 3'h0 : _08_;
+ function [0:0] \20549 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20549 = b[0:0];
+ 3'b?1?:
+ \20549 = b[1:1];
+ 3'b1??:
+ \20549 = b[2:2];
+ default:
+ \20549 = a;
+ endcase
+ endfunction
+ assign _50_ = \20549 (1'hx, { _46_, _30_, _25_ }, { _47_, _31_, _26_ });
+ assign _51_ = _50_ ? 1'h0 : _10_;
+ assign _52_ = ~ deferred;
+ assign _53_ = { _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_ } + 32'd1;
+ assign _54_ = _55_ ? _53_[2:0] : _49_;
+ assign gpr_write_valid = _51_ ? gpr_write_valid_in : 1'h0;
+ assign cr_write_valid = _51_ ? cr_write_in : 1'h0;
+ assign _55_ = _51_ & _52_;
+ assign _56_ = _50_ | deferred;
+ cr_hazard_1 cr_hazard0 (
+ .busy_in(busy_in),
+ .bypassable(cr_bypassable),
+ .clk(clk),
+ .complete_in(complete_in),
+ .cr_read_in(cr_read_in),
+ .cr_write_in(cr_write_valid),
+ .deferred(deferred),
+ .flush_in(flush_in),
+ .issuing(_51_),
+ .stall_out(cr_stall_out),
+ .use_bypass(_03_)
+ );
+ gpr_hazard_1 gpr_hazard0 (
+ .busy_in(busy_in),
+ .bypass_avail(gpr_bypassable),
+ .clk(clk),
+ .complete_in(complete_in),
+ .deferred(deferred),
+ .flush_in(flush_in),
+ .gpr_read_in(gpr_a_read_in),
+ .gpr_read_valid_in(gpr_a_read_valid_in),
+ .gpr_write_in(gpr_write_in),
+ .gpr_write_valid_in(gpr_write_valid),
+ .issuing(_51_),
+ .stall_out(stall_a_out),
+ .ugpr_write_reg(update_gpr_write_reg),
+ .ugpr_write_valid(update_gpr_write_valid),
+ .use_bypass(_00_)
+ );
+ gpr_hazard_1 gpr_hazard1 (
+ .busy_in(busy_in),
+ .bypass_avail(gpr_bypassable),
+ .clk(clk),
+ .complete_in(complete_in),
+ .deferred(deferred),
+ .flush_in(flush_in),
+ .gpr_read_in(gpr_b_read_in),
+ .gpr_read_valid_in(gpr_b_read_valid_in),
+ .gpr_write_in(gpr_write_in),
+ .gpr_write_valid_in(gpr_write_valid),
+ .issuing(_51_),
+ .stall_out(stall_b_out),
+ .ugpr_write_reg(update_gpr_write_reg),
+ .ugpr_write_valid(update_gpr_write_valid),
+ .use_bypass(_01_)
+ );
+ gpr_hazard_1 gpr_hazard2 (
+ .busy_in(busy_in),
+ .bypass_avail(gpr_bypassable),
+ .clk(clk),
+ .complete_in(complete_in),
+ .deferred(deferred),
+ .flush_in(flush_in),
+ .gpr_read_in(gpr_c_read_in),
+ .gpr_read_valid_in(gpr_c_read_valid_in),
+ .gpr_write_in(gpr_write_in),
+ .gpr_write_valid_in(gpr_write_valid),
+ .issuing(_51_),
+ .stall_out(stall_c_out),
+ .ugpr_write_reg(update_gpr_write_reg),
+ .ugpr_write_valid(update_gpr_write_valid),
+ .use_bypass(_02_)
+ );
+ assign valid_out = _51_;
+ assign stall_out = _56_;
+ assign stopped_out = _13_;
+ assign gpr_bypass_a = _00_;
+ assign gpr_bypass_b = _01_;
+ assign gpr_bypass_c = _02_;
+ assign cr_bypass = _03_;
+endmodule
+
+module core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, rst, alt_reset, wishbone_insn_in, wishbone_data_in, dmi_addr, dmi_din, dmi_req, dmi_wr, ext_irq, wishbone_insn_out, wishbone_data_out, dmi_dout, dmi_ack, terminated_out);
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
+ wire [42:0] _00_;
+ wire [106:0] _01_;
+ wire [53:0] _02_;
+ wire _03_;
+ wire [12:0] _04_;
+ wire [9:0] _05_;
+ wire [71:0] _06_;
+ wire [12:0] _07_;
+ wire [306:0] _08_;
+ wire [14:0] _09_;
+ wire [9:0] _10_;
+ wire [106:0] _11_;
+ wire [19:0] _12_;
+ wire [63:0] _13_;
+ wire _14_;
+ wire _15_;
+ input alt_reset;
+ reg alt_reset_d;
+ input clk;
+ wire complete;
+ wire core_rst;
+ wire [36:0] cr_file_to_decode2;
+ wire dbg_core_is_stopped;
+ wire dbg_core_rst;
+ wire dbg_core_stop;
+ wire dbg_gpr_ack;
+ wire [6:0] dbg_gpr_addr;
+ wire [63:0] dbg_gpr_data;
+ wire dbg_gpr_req;
+ wire dbg_icache_rst;
+ wire dcache_stall_out;
+ wire [67:0] dcache_to_loadstore1;
+ wire [66:0] dcache_to_mmu;
+ wire decode1_busy;
+ wire decode1_flush;
+ wire [153:0] decode1_to_decode2;
+ wire [64:0] decode1_to_fetch1;
+ wire decode2_stall_out;
+ wire decode2_to_cr_file;
+ wire [379:0] decode2_to_execute1;
+ wire [23:0] decode2_to_register_file;
+ output dmi_ack;
+ input [3:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ input dmi_req;
+ input dmi_wr;
+ wire ex1_busy_out;
+ wire ex1_icache_inval;
+ wire [68:0] execute1_to_fetch1;
+ wire [325:0] execute1_to_loadstore1;
+ wire [193:0] execute1_to_writeback;
+ input ext_irq;
+ wire fetch1_flush;
+ wire fetch1_stall_in;
+ wire [69:0] fetch1_to_icache;
+ wire flush;
+ wire icache_stall_out;
+ wire [98:0] icache_to_decode1;
+ wire [142:0] loadstore1_to_dcache;
+ wire [8:0] loadstore1_to_execute1;
+ wire [144:0] loadstore1_to_mmu;
+ wire [79:0] loadstore1_to_writeback;
+ wire [31:0] log_rd_addr;
+ wire [63:0] log_rd_data;
+ wire [31:0] log_wr_addr;
+ wire [131:0] mmu_to_dcache;
+ wire [130:0] mmu_to_icache;
+ wire [70:0] mmu_to_loadstore1;
+ wire [63:0] msr;
+ wire [191:0] register_file_to_decode2;
+ input rst;
+ reg rst_dbg = 1'h1;
+ reg rst_dcache = 1'h1;
+ reg rst_dec1 = 1'h1;
+ reg rst_dec2 = 1'h1;
+ reg rst_ex1 = 1'h1;
+ reg rst_fetch1 = 1'h1;
+ reg rst_icache = 1'h1;
+ reg rst_ls1 = 1'h1;
+ wire sim_cr_dump;
+ wire terminate;
+ output terminated_out;
+ input [65:0] wishbone_data_in;
+ output [106:0] wishbone_data_out;
+ input [65:0] wishbone_insn_in;
+ output [106:0] wishbone_insn_out;
+ wire [46:0] writeback_to_cr_file;
+ wire [71:0] writeback_to_register_file;
+ assign core_rst = dbg_core_rst | rst;
+ always @(posedge clk)
+ rst_fetch1 <= core_rst;
+ always @(posedge clk)
+ rst_icache <= core_rst;
+ always @(posedge clk)
+ rst_dcache <= core_rst;
+ always @(posedge clk)
+ rst_dec1 <= core_rst;
+ always @(posedge clk)
+ rst_dec2 <= core_rst;
+ always @(posedge clk)
+ rst_ex1 <= core_rst;
+ always @(posedge clk)
+ rst_ls1 <= core_rst;
+ always @(posedge clk)
+ rst_dbg <= rst;
+ always @(posedge clk)
+ alt_reset_d <= alt_reset;
+ assign fetch1_stall_in = icache_stall_out | decode1_busy;
+ assign fetch1_flush = flush | decode1_flush;
+ assign _03_ = dbg_icache_rst | ex1_icache_inval;
+ cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f cr_file_0 (
+ .clk(clk),
+ .d_in(decode2_to_cr_file),
+ .d_out(cr_file_to_decode2),
+ .log_out(_07_),
+ .sim_dump(sim_cr_dump),
+ .w_in(writeback_to_cr_file)
+ );
+ dcache dcache_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .clk(clk),
+ .d_in(loadstore1_to_dcache),
+ .d_out(dcache_to_loadstore1),
+ .m_in(mmu_to_dcache),
+ .m_out(dcache_to_mmu),
+ .rst(rst_dcache),
+ .stall_out(dcache_stall_out),
+ .wishbone_in(wishbone_data_in),
+ .wishbone_out(_11_)
+ );
+ core_debug_0 debug_0 (
+ .clk(clk),
+ .core_rst(dbg_core_rst),
+ .core_stop(dbg_core_stop),
+ .core_stopped(dbg_core_is_stopped),
+ .dbg_gpr_ack(dbg_gpr_ack),
+ .dbg_gpr_addr(dbg_gpr_addr),
+ .dbg_gpr_data(dbg_gpr_data),
+ .dbg_gpr_req(dbg_gpr_req),
+ .dmi_ack(_14_),
+ .dmi_addr(dmi_addr),
+ .dmi_din(dmi_din),
+ .dmi_dout(_13_),
+ .dmi_req(dmi_req),
+ .dmi_wr(dmi_wr),
+ .icache_rst(dbg_icache_rst),
+ .log_data({ _06_, _07_, _12_, 1'h0, _10_, 5'h00, _09_, _05_, _04_, _02_, _00_ }),
+ .log_read_addr(log_rd_addr),
+ .log_read_data(log_rd_data),
+ .log_write_addr(log_wr_addr),
+ .msr(msr),
+ .nia(fetch1_to_icache[69:6]),
+ .rst(rst_dbg),
+ .terminate(terminate),
+ .terminated_out(_15_)
+ );
+ decode1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f decode1_0 (
+ .busy_out(decode1_busy),
+ .clk(clk),
+ .d_out(decode1_to_decode2),
+ .f_in(icache_to_decode1),
+ .f_out(decode1_to_fetch1),
+ .flush_in(flush),
+ .flush_out(decode1_flush),
+ .log_out(_04_),
+ .rst(rst_dec1),
+ .stall_in(decode2_stall_out)
+ );
+ decode2_0_0e356ba505631fbf715758bed27d503f8b260e3a decode2_0 (
+ .busy_in(ex1_busy_out),
+ .c_in(cr_file_to_decode2),
+ .c_out(decode2_to_cr_file),
+ .clk(clk),
+ .complete_in(complete),
+ .d_in(decode1_to_decode2),
+ .e_out(decode2_to_execute1),
+ .flush_in(flush),
+ .log_out(_05_),
+ .r_in(register_file_to_decode2),
+ .r_out(decode2_to_register_file),
+ .rst(rst_dec2),
+ .stall_out(decode2_stall_out),
+ .stopped_out(dbg_core_is_stopped)
+ );
+ execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a execute1_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .busy_out(ex1_busy_out),
+ .clk(clk),
+ .dbg_msr_out(msr),
+ .e_in(decode2_to_execute1),
+ .e_out(execute1_to_writeback),
+ .ext_irq_in(ext_irq),
+ .f_out(execute1_to_fetch1),
+ .flush_out(flush),
+ .fp_in(4'h0),
+ .fp_out(_08_),
+ .icache_inval(ex1_icache_inval),
+ .l_in(loadstore1_to_execute1),
+ .l_out(execute1_to_loadstore1),
+ .log_out(_09_),
+ .log_rd_addr(log_rd_addr),
+ .log_rd_data(log_rd_data),
+ .log_wr_addr(log_wr_addr),
+ .rst(rst_ex1),
+ .terminate_out(terminate)
+ );
+ fetch1_05c2030ccbceb505e9c9c1e14c8b4fa317497e84 fetch1_0 (
+ .alt_reset_in(alt_reset_d),
+ .clk(clk),
+ .d_in(decode1_to_fetch1),
+ .e_in(execute1_to_fetch1),
+ .flush_in(fetch1_flush),
+ .i_out(fetch1_to_icache),
+ .log_out(_00_),
+ .rst(rst_fetch1),
+ .stall_in(fetch1_stall_in),
+ .stop_in(dbg_core_stop)
+ );
+ icache icache_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .clk(clk),
+ .flush_in(fetch1_flush),
+ .i_in(fetch1_to_icache),
+ .i_out(icache_to_decode1),
+ .inval_in(_03_),
+ .m_in(mmu_to_icache),
+ .rst(rst_icache),
+ .stall_in(decode1_busy),
+ .stall_out(icache_stall_out),
+ .wishbone_in(wishbone_insn_in),
+ .wishbone_out(_01_)
+ );
+ loadstore1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f loadstore1_0 (
+ .clk(clk),
+ .d_in(dcache_to_loadstore1),
+ .d_out(loadstore1_to_dcache),
+ .dc_stall(dcache_stall_out),
+ .e_out(loadstore1_to_execute1),
+ .l_in(execute1_to_loadstore1),
+ .l_out(loadstore1_to_writeback),
+ .log_out(_10_),
+ .m_in(mmu_to_loadstore1),
+ .m_out(loadstore1_to_mmu),
+ .rst(rst_ls1)
+ );
+ mmu mmu_0 (
+ .clk(clk),
+ .d_in(dcache_to_mmu),
+ .d_out(mmu_to_dcache),
+ .i_out(mmu_to_icache),
+ .l_in(loadstore1_to_mmu),
+ .l_out(mmu_to_loadstore1),
+ .rst(core_rst)
+ );
+ register_file register_file_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .clk(clk),
+ .d_in(decode2_to_register_file),
+ .d_out(register_file_to_decode2),
+ .w_in(writeback_to_register_file)
+ );
+ writeback writeback_0 (
+ .c_out(writeback_to_cr_file),
+ .clk(clk),
+ .complete_out(complete),
+ .e_in(execute1_to_writeback),
+ .fp_in(114'h00000000000000000000000000000),
+ .l_in(loadstore1_to_writeback),
+ .w_out(writeback_to_register_file)
+ );
+ assign wishbone_insn_out = _01_;
+ assign wishbone_data_out = _11_;
+ assign dmi_dout = _13_;
+ assign dmi_ack = _14_;
+ assign terminated_out = _15_;
+endmodule
+
+module core_debug_0(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, terminate, core_stopped, nia, msr, dbg_gpr_ack, dbg_gpr_data, log_data, log_read_addr, dmi_dout, dmi_ack, core_stop, core_rst, icache_rst, dbg_gpr_req, dbg_gpr_addr, log_read_data, log_write_addr, terminated_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire [63:0] _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire [31:0] _24_;
+ wire [6:0] _25_;
+ wire [31:0] _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire [6:0] _32_;
+ wire [31:0] _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire [6:0] _39_;
+ wire [31:0] _40_;
+ wire _41_;
+ wire _42_;
+ wire [1:0] _43_;
+ wire [1:0] _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire [1:0] _51_;
+ wire [29:0] _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire _62_;
+ wire _63_;
+ wire [6:0] _64_;
+ wire [31:0] _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ input clk;
+ output core_rst;
+ output core_stop;
+ input core_stopped;
+ input dbg_gpr_ack;
+ output [6:0] dbg_gpr_addr;
+ input [63:0] dbg_gpr_data;
+ output dbg_gpr_req;
+ output dmi_ack;
+ input [3:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ reg dmi_read_log_data;
+ reg dmi_read_log_data_1;
+ input dmi_req;
+ reg dmi_req_1;
+ input dmi_wr;
+ reg do_icreset;
+ reg do_reset;
+ reg do_step;
+ reg [6:0] gspr_index;
+ output icache_rst;
+ input [255:0] log_data;
+ reg [31:0] log_dmi_addr = 32'd0;
+ input [31:0] log_read_addr;
+ output [63:0] log_read_data;
+ output [31:0] log_write_addr;
+ input [63:0] msr;
+ input [63:0] nia;
+ input rst;
+ reg stopping;
+ input terminate;
+ reg terminated;
+ output terminated_out;
+ assign _00_ = dmi_addr != 4'h5;
+ assign _01_ = _00_ ? dmi_req : dbg_gpr_ack;
+ assign _02_ = dmi_addr == 4'h5;
+ assign _03_ = _02_ ? dmi_req : 1'h0;
+ assign _04_ = dmi_addr == 4'h1;
+ assign _05_ = dmi_addr == 4'h2;
+ assign _06_ = dmi_addr == 4'h3;
+ assign _07_ = dmi_addr == 4'h5;
+ assign _08_ = dmi_addr == 4'h6;
+ assign _09_ = dmi_addr == 4'h7;
+ function [63:0] \19764 ;
+ input [63:0] a;
+ input [383:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \19764 = b[63:0];
+ 6'b????1?:
+ \19764 = b[127:64];
+ 6'b???1??:
+ \19764 = b[191:128];
+ 6'b??1???:
+ \19764 = b[255:192];
+ 6'b?1????:
+ \19764 = b[319:256];
+ 6'b1?????:
+ \19764 = b[383:320];
+ default:
+ \19764 = a;
+ endcase
+ endfunction
+ assign _10_ = \19764 (64'h0000000000000000, { 96'h000000000000000000000001, log_dmi_addr, dbg_gpr_data, msr, nia, 61'h0000000000000000, terminated, core_stopped, stopping }, { _09_, _08_, _07_, _06_, _05_, _04_ });
+ assign _11_ = ~ dmi_req_1;
+ assign _12_ = dmi_req & _11_;
+ assign _13_ = dmi_addr == 4'h0;
+ assign _14_ = dmi_din[1] ? 1'h1 : 1'h0;
+ assign _15_ = dmi_din[1] ? 1'h0 : terminated;
+ assign _16_ = dmi_din[0] ? 1'h1 : stopping;
+ assign _17_ = dmi_din[3] ? 1'h1 : 1'h0;
+ assign _18_ = dmi_din[3] ? 1'h0 : _15_;
+ assign _19_ = dmi_din[2] ? 1'h1 : 1'h0;
+ assign _20_ = dmi_din[4] ? 1'h0 : _16_;
+ assign _21_ = dmi_din[4] ? 1'h0 : _18_;
+ assign _22_ = dmi_addr == 4'h4;
+ assign _23_ = dmi_addr == 4'h6;
+ assign _24_ = _23_ ? dmi_din[31:0] : log_dmi_addr;
+ assign _25_ = _22_ ? dmi_din[6:0] : gspr_index;
+ assign _26_ = _22_ ? log_dmi_addr : _24_;
+ assign _27_ = _45_ ? _20_ : stopping;
+ assign _28_ = _13_ ? _17_ : 1'h0;
+ assign _29_ = _13_ ? _14_ : 1'h0;
+ assign _30_ = _13_ ? _19_ : 1'h0;
+ assign _31_ = _49_ ? _21_ : terminated;
+ assign _32_ = _13_ ? gspr_index : _25_;
+ assign _33_ = _13_ ? log_dmi_addr : _26_;
+ assign _34_ = dmi_wr & _13_;
+ assign _35_ = dmi_wr ? _28_ : 1'h0;
+ assign _36_ = dmi_wr ? _29_ : 1'h0;
+ assign _37_ = dmi_wr ? _30_ : 1'h0;
+ assign _38_ = dmi_wr & _13_;
+ assign _39_ = _50_ ? _32_ : gspr_index;
+ assign _40_ = dmi_wr ? _33_ : log_dmi_addr;
+ assign _41_ = ~ dmi_read_log_data;
+ assign _42_ = _41_ & dmi_read_log_data_1;
+ assign _43_ = log_dmi_addr[1:0] + 2'h1;
+ assign _44_ = _42_ ? _43_ : log_dmi_addr[1:0];
+ assign _45_ = _12_ & _34_;
+ assign _46_ = _12_ ? _35_ : 1'h0;
+ assign _47_ = _12_ ? _36_ : 1'h0;
+ assign _48_ = _12_ ? _37_ : 1'h0;
+ assign _49_ = _12_ & _38_;
+ assign _50_ = _12_ & dmi_wr;
+ assign _51_ = _12_ ? _40_[1:0] : _44_;
+ assign _52_ = _12_ ? _40_[31:2] : log_dmi_addr[31:2];
+ assign _53_ = dmi_addr == 4'h7;
+ assign _54_ = dmi_req & _53_;
+ assign _55_ = _54_ ? 1'h1 : 1'h0;
+ assign _56_ = terminate ? 1'h1 : _27_;
+ assign _57_ = terminate ? 1'h1 : _31_;
+ assign _58_ = rst ? dmi_req_1 : dmi_req;
+ assign _59_ = rst ? 1'h0 : _56_;
+ assign _60_ = rst ? 1'h0 : _46_;
+ assign _61_ = rst ? 1'h0 : _47_;
+ assign _62_ = rst ? 1'h0 : _48_;
+ assign _63_ = rst ? 1'h0 : _57_;
+ assign _64_ = rst ? gspr_index : _39_;
+ assign _65_ = rst ? log_dmi_addr : { _52_, _51_ };
+ assign _66_ = rst ? dmi_read_log_data : _55_;
+ assign _67_ = rst ? dmi_read_log_data_1 : dmi_read_log_data;
+ always @(posedge clk)
+ dmi_req_1 <= _58_;
+ always @(posedge clk)
+ stopping <= _59_;
+ always @(posedge clk)
+ do_step <= _60_;
+ always @(posedge clk)
+ do_reset <= _61_;
+ always @(posedge clk)
+ do_icreset <= _62_;
+ always @(posedge clk)
+ terminated <= _63_;
+ always @(posedge clk)
+ gspr_index <= _64_;
+ always @(posedge clk)
+ log_dmi_addr <= _65_;
+ always @(posedge clk)
+ dmi_read_log_data <= _66_;
+ always @(posedge clk)
+ dmi_read_log_data_1 <= _67_;
+ assign _68_ = ~ do_step;
+ assign _69_ = stopping & _68_;
+ assign dmi_dout = _10_;
+ assign dmi_ack = _01_;
+ assign core_stop = _69_;
+ assign core_rst = do_reset;
+ assign icache_rst = do_icreset;
+ assign dbg_gpr_req = _03_;
+ assign dbg_gpr_addr = gspr_index;
+ assign log_read_data = 64'h0000000000000000;
+ assign log_write_addr = 32'd1;
+ assign terminated_out = terminated;
+endmodule
+
+module cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, sim_dump, d_out, log_out);
+ wire [3:0] _0_;
+ wire [3:0] _1_;
+ wire [3:0] _2_;
+ wire [3:0] _3_;
+ wire [3:0] _4_;
+ wire [3:0] _5_;
+ wire [3:0] _6_;
+ wire [3:0] _7_;
+ wire [31:0] _8_;
+ wire [4:0] _9_;
+ input clk;
+ reg [31:0] crs = 32'd0;
+ input d_in;
+ output [36:0] d_out;
+ output [12:0] log_out;
+ input sim_dump;
+ input [46:0] w_in;
+ reg [4:0] xerc = 5'h00;
+ wire [4:0] xerc_updated;
+ assign _0_ = w_in[1] ? w_in[12:9] : crs[3:0];
+ assign _1_ = w_in[2] ? w_in[16:13] : crs[7:4];
+ assign _2_ = w_in[3] ? w_in[20:17] : crs[11:8];
+ assign _3_ = w_in[4] ? w_in[24:21] : crs[15:12];
+ assign _4_ = w_in[5] ? w_in[28:25] : crs[19:16];
+ assign _5_ = w_in[6] ? w_in[32:29] : crs[23:20];
+ assign _6_ = w_in[7] ? w_in[36:33] : crs[27:24];
+ assign _7_ = w_in[8] ? w_in[40:37] : crs[31:28];
+ assign xerc_updated = w_in[41] ? w_in[46:42] : xerc;
+ assign _8_ = w_in[0] ? { _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ } : crs;
+ always @(posedge clk)
+ crs <= _8_;
+ assign _9_ = w_in[41] ? xerc_updated : xerc;
+ always @(posedge clk)
+ xerc <= _9_;
+ assign d_out = { xerc_updated, _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ };
+ assign log_out = 13'hzzzz;
+endmodule
+
+module cr_hazard_1(clk, busy_in, deferred, complete_in, flush_in, issuing, cr_read_in, cr_write_in, bypassable, stall_out, use_bypass);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ input busy_in;
+ input bypassable;
+ input clk;
+ input complete_in;
+ input cr_read_in;
+ input cr_write_in;
+ input deferred;
+ input flush_in;
+ input issuing;
+ reg [3:0] r = 4'h0;
+ output stall_out;
+ output use_bypass;
+ always @(posedge clk)
+ r <= { _20_, _18_, _19_, _16_ };
+ assign _00_ = complete_in ? 1'h0 : r[0];
+ assign _01_ = r[3] ? 1'h0 : 1'h1;
+ assign _02_ = r[3] ? 1'h1 : 1'h0;
+ assign _03_ = r[2] ? _01_ : 1'h0;
+ assign _04_ = r[2] ? _02_ : 1'h0;
+ assign _05_ = r[1] ? _03_ : 1'h1;
+ assign _06_ = _08_ ? 1'h1 : _04_;
+ assign _07_ = _00_ ? _05_ : _03_;
+ assign _08_ = _00_ & r[1];
+ assign _09_ = cr_read_in ? _07_ : 1'h0;
+ assign _10_ = cr_read_in ? _06_ : 1'h0;
+ assign _11_ = ~ busy_in;
+ assign _12_ = ~ deferred;
+ assign _13_ = _12_ & issuing;
+ assign _14_ = _11_ ? 1'h0 : r[2];
+ assign _15_ = _11_ ? r[2] : _00_;
+ assign _16_ = flush_in ? 1'h0 : _15_;
+ assign _17_ = _13_ ? cr_write_in : _14_;
+ assign _18_ = flush_in ? 1'h0 : _17_;
+ assign _19_ = _11_ ? r[3] : r[1];
+ assign _20_ = _13_ ? bypassable : r[3];
+ assign stall_out = _09_;
+ assign use_bypass = _10_;
+endmodule
+
+
+module decode1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst, stall_in, flush_in, f_in, busy_out, flush_out, f_out, d_out, log_out);
+ wire _000_;
+ wire [153:0] _001_;
+ wire _002_;
+ wire [43:0] _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire [153:0] _009_;
+ wire [43:0] _010_;
+ wire [153:0] _011_;
+ wire _012_;
+ wire [152:0] _013_;
+ wire [43:0] _014_;
+ wire [43:0] _015_;
+ wire _016_;
+ wire [152:0] _017_;
+ wire _018_;
+ wire [152:0] _019_;
+ wire [43:0] _020_;
+ wire [43:0] _021_;
+ wire [153:0] _022_;
+ wire [153:0] _023_;
+ wire [43:0] _024_;
+ wire [43:0] _025_;
+ wire [5:0] _026_;
+ wire [10:0] _027_;
+ wire _028_;
+ wire [5:0] _029_;
+ wire _030_;
+ wire [9:0] _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire [6:0] _049_;
+ wire [4:0] _050_;
+ wire [4:0] _051_;
+ wire [6:0] _052_;
+ wire [9:0] _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire [1:0] _063_;
+ wire _064_;
+ wire [1:0] _065_;
+ wire [1:0] _066_;
+ wire [1:0] _067_;
+ wire [1:0] _068_;
+ wire _069_;
+ wire _070_;
+ wire [6:0] _071_;
+ wire _072_;
+ wire _073_;
+ wire [9:0] _074_;
+ wire _075_;
+ wire [2:0] _076_;
+ wire _077_;
+ wire _078_;
+ wire [6:0] _079_;
+ wire _080_;
+ wire _081_;
+ wire [6:0] _082_;
+ wire [6:0] _083_;
+ wire [13:0] _084_;
+ wire _085_;
+ wire [3:0] _086_;
+ wire _087_;
+ wire [31:0] _088_;
+ wire _089_;
+ wire [41:0] _090_;
+ wire _091_;
+ wire [1:0] _092_;
+ wire _093_;
+ wire _094_;
+ wire [1:0] _095_;
+ wire _096_;
+ wire _097_;
+ wire [6:0] _098_;
+ wire [6:0] _099_;
+ wire [40:0] _100_;
+ wire _101_;
+ wire _102_;
+ wire [1:0] _103_;
+ wire [38:0] _104_;
+ wire [1:0] _105_;
+ wire [23:0] _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire [41:0] _111_;
+ wire [61:0] _112_;
+ wire [61:0] _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire [1:0] _119_;
+ wire [1:0] _120_;
+ wire _121_;
+ wire _122_;
+ wire [37:0] _123_;
+ wire [2623:0] _124_;
+ wire [40:0] _125_;
+ wire [2047:0] _126_;
+ wire _127_;
+ wire [2623:0] _128_;
+ wire [40:0] _129_;
+ wire [41983:0] _130_;
+ wire [40:0] _131_;
+ wire [1023:0] _132_;
+ wire _133_;
+ wire [327:0] _134_;
+ wire [40:0] _135_;
+ wire [655:0] _136_;
+ wire [40:0] _137_;
+ wire [163:0] _138_;
+ wire [40:0] _139_;
+ wire [163:0] _140_;
+ wire [40:0] _141_;
+ output busy_out;
+ input clk;
+ output [153:0] d_out;
+ input [98:0] f_in;
+ output [64:0] f_out;
+ input flush_in;
+ output flush_out;
+ output [12:0] log_out;
+ reg [153:0] r;
+ reg [43:0] ri;
+ input rst;
+ reg [153:0] s;
+ reg [43:0] si;
+ input stall_in;
+ reg [40:0] \$mem$\8810 [63:0];
+ reg [0:0] \$mem$\8812 [2047:0];
+ reg [40:0] \$mem$\8814 [63:0];
+ reg [40:0] \$mem$\8816 [1023:0];
+ reg [0:0] \$mem$\8818 [1023:0];
+ reg [40:0] \$mem$\8820 [7:0];
+ reg [40:0] \$mem$\8822 [15:0];
+ reg [40:0] \$mem$\8824 [3:0];
+ reg [40:0] \$mem$\8826 [3:0];
+ reg [40:0] \8810 [63:0];
+ initial begin
+ \8810 [0] = 41'h00000000000;
+ \8810 [1] = 41'h00000000000;
+ \8810 [2] = 41'h00000000000;
+ \8810 [3] = 41'h00000000000;
+ \8810 [4] = 41'h00000000000;
+ \8810 [5] = 41'h00000000000;
+ \8810 [6] = 41'h00000000000;
+ \8810 [7] = 41'h00000000000;
+ \8810 [8] = 41'h00240021a8a;
+ \8810 [9] = 41'h00040021a8a;
+ \8810 [10] = 41'h00a30021a8a;
+ \8810 [11] = 41'h00830021a8a;
+ \8810 [12] = 41'h00240101a86;
+ \8810 [13] = 41'h00040101a86;
+ \8810 [14] = 41'h00a30101a86;
+ \8810 [15] = 41'h00830101a86;
+ \8810 [16] = 41'h00000000000;
+ \8810 [17] = 41'h00000000000;
+ \8810 [18] = 41'h00220009a82;
+ \8810 [19] = 41'h00020009a82;
+ \8810 [20] = 41'h00320041a7e;
+ \8810 [21] = 41'h00120041a7e;
+ \8810 [22] = 41'h00220041a7e;
+ \8810 [23] = 41'h00020041a7e;
+ \8810 [24] = 41'h00210009a82;
+ \8810 [25] = 41'h00010009a82;
+ \8810 [26] = 41'h00230009a82;
+ \8810 [27] = 41'h00030009a82;
+ \8810 [28] = 41'h00210041a7e;
+ \8810 [29] = 41'h00010041a7e;
+ \8810 [30] = 41'h00230041a7e;
+ \8810 [31] = 41'h00030041a7e;
+ \8810 [32] = 41'h00000000000;
+ \8810 [33] = 41'h00000000000;
+ \8810 [34] = 41'h0200008a80d;
+ \8810 [35] = 41'h0200008900d;
+ \8810 [36] = 41'h0000008a8f1;
+ \8810 [37] = 41'h000000890f1;
+ \8810 [38] = 41'h0000008a8b9;
+ \8810 [39] = 41'h000000890b9;
+ \8810 [40] = 41'h048000888c9;
+ \8810 [41] = 41'h00000000000;
+ \8810 [42] = 41'h0480008e0c9;
+ \8810 [43] = 41'h0480008e1c9;
+ \8810 [44] = 41'h00000000000;
+ \8810 [45] = 41'h08000003015;
+ \8810 [46] = 41'h000000000d5;
+ \8810 [47] = 41'h080002c3b19;
+ \8810 [48] = 41'h00000042209;
+ \8810 [49] = 41'h00000041a09;
+ \8810 [50] = 41'h02008041909;
+ \8810 [51] = 41'h00008041909;
+ \8810 [52] = 41'h01006c01925;
+ \8810 [53] = 41'h00006c01125;
+ \8810 [54] = 41'h00000000000;
+ \8810 [55] = 41'h0000e841909;
+ \8810 [56] = 41'h010000419ad;
+ \8810 [57] = 41'h00000000000;
+ \8810 [58] = 41'h00000000000;
+ \8810 [59] = 41'h00000000000;
+ \8810 [60] = 41'h108000019ed;
+ \8810 [61] = 41'h100000019ed;
+ \8810 [62] = 41'h00000000000;
+ \8810 [63] = 41'h10000000011;
+ end
+ assign _125_ = \8810 [_026_];
+ reg [0:0] \8812 [2047:0];
+ initial begin
+ \8812 [0] = 1'h0;
+ \8812 [1] = 1'h0;
+ \8812 [2] = 1'h0;
+ \8812 [3] = 1'h0;
+ \8812 [4] = 1'h0;
+ \8812 [5] = 1'h0;
+ \8812 [6] = 1'h0;
+ \8812 [7] = 1'h0;
+ \8812 [8] = 1'h0;
+ \8812 [9] = 1'h0;
+ \8812 [10] = 1'h0;
+ \8812 [11] = 1'h0;
+ \8812 [12] = 1'h0;
+ \8812 [13] = 1'h0;
+ \8812 [14] = 1'h0;
+ \8812 [15] = 1'h0;
+ \8812 [16] = 1'h0;
+ \8812 [17] = 1'h0;
+ \8812 [18] = 1'h0;
+ \8812 [19] = 1'h0;
+ \8812 [20] = 1'h0;
+ \8812 [21] = 1'h0;
+ \8812 [22] = 1'h0;
+ \8812 [23] = 1'h0;
+ \8812 [24] = 1'h0;
+ \8812 [25] = 1'h0;
+ \8812 [26] = 1'h0;
+ \8812 [27] = 1'h0;
+ \8812 [28] = 1'h0;
+ \8812 [29] = 1'h0;
+ \8812 [30] = 1'h0;
+ \8812 [31] = 1'h0;
+ \8812 [32] = 1'h0;
+ \8812 [33] = 1'h0;
+ \8812 [34] = 1'h0;
+ \8812 [35] = 1'h0;
+ \8812 [36] = 1'h0;
+ \8812 [37] = 1'h0;
+ \8812 [38] = 1'h0;
+ \8812 [39] = 1'h0;
+ \8812 [40] = 1'h0;
+ \8812 [41] = 1'h0;
+ \8812 [42] = 1'h0;
+ \8812 [43] = 1'h0;
+ \8812 [44] = 1'h0;
+ \8812 [45] = 1'h0;
+ \8812 [46] = 1'h0;
+ \8812 [47] = 1'h0;
+ \8812 [48] = 1'h0;
+ \8812 [49] = 1'h0;
+ \8812 [50] = 1'h0;
+ \8812 [51] = 1'h0;
+ \8812 [52] = 1'h0;
+ \8812 [53] = 1'h0;
+ \8812 [54] = 1'h0;
+ \8812 [55] = 1'h0;
+ \8812 [56] = 1'h0;
+ \8812 [57] = 1'h0;
+ \8812 [58] = 1'h0;
+ \8812 [59] = 1'h0;
+ \8812 [60] = 1'h0;
+ \8812 [61] = 1'h0;
+ \8812 [62] = 1'h0;
+ \8812 [63] = 1'h0;
+ \8812 [64] = 1'h0;
+ \8812 [65] = 1'h0;
+ \8812 [66] = 1'h0;
+ \8812 [67] = 1'h0;
+ \8812 [68] = 1'h0;
+ \8812 [69] = 1'h0;
+ \8812 [70] = 1'h0;
+ \8812 [71] = 1'h0;
+ \8812 [72] = 1'h0;
+ \8812 [73] = 1'h0;
+ \8812 [74] = 1'h0;
+ \8812 [75] = 1'h0;
+ \8812 [76] = 1'h0;
+ \8812 [77] = 1'h0;
+ \8812 [78] = 1'h0;
+ \8812 [79] = 1'h0;
+ \8812 [80] = 1'h0;
+ \8812 [81] = 1'h0;
+ \8812 [82] = 1'h0;
+ \8812 [83] = 1'h0;
+ \8812 [84] = 1'h0;
+ \8812 [85] = 1'h0;
+ \8812 [86] = 1'h0;
+ \8812 [87] = 1'h0;
+ \8812 [88] = 1'h0;
+ \8812 [89] = 1'h0;
+ \8812 [90] = 1'h0;
+ \8812 [91] = 1'h0;
+ \8812 [92] = 1'h0;
+ \8812 [93] = 1'h0;
+ \8812 [94] = 1'h0;
+ \8812 [95] = 1'h0;
+ \8812 [96] = 1'h0;
+ \8812 [97] = 1'h0;
+ \8812 [98] = 1'h0;
+ \8812 [99] = 1'h0;
+ \8812 [100] = 1'h0;
+ \8812 [101] = 1'h0;
+ \8812 [102] = 1'h0;
+ \8812 [103] = 1'h0;
+ \8812 [104] = 1'h0;
+ \8812 [105] = 1'h0;
+ \8812 [106] = 1'h0;
+ \8812 [107] = 1'h0;
+ \8812 [108] = 1'h0;
+ \8812 [109] = 1'h0;
+ \8812 [110] = 1'h0;
+ \8812 [111] = 1'h0;
+ \8812 [112] = 1'h0;
+ \8812 [113] = 1'h0;
+ \8812 [114] = 1'h0;
+ \8812 [115] = 1'h0;
+ \8812 [116] = 1'h0;
+ \8812 [117] = 1'h0;
+ \8812 [118] = 1'h0;
+ \8812 [119] = 1'h0;
+ \8812 [120] = 1'h0;
+ \8812 [121] = 1'h0;
+ \8812 [122] = 1'h0;
+ \8812 [123] = 1'h0;
+ \8812 [124] = 1'h0;
+ \8812 [125] = 1'h0;
+ \8812 [126] = 1'h0;
+ \8812 [127] = 1'h0;
+ \8812 [128] = 1'h0;
+ \8812 [129] = 1'h0;
+ \8812 [130] = 1'h0;
+ \8812 [131] = 1'h0;
+ \8812 [132] = 1'h0;
+ \8812 [133] = 1'h0;
+ \8812 [134] = 1'h0;
+ \8812 [135] = 1'h0;
+ \8812 [136] = 1'h0;
+ \8812 [137] = 1'h0;
+ \8812 [138] = 1'h0;
+ \8812 [139] = 1'h0;
+ \8812 [140] = 1'h0;
+ \8812 [141] = 1'h0;
+ \8812 [142] = 1'h0;
+ \8812 [143] = 1'h0;
+ \8812 [144] = 1'h0;
+ \8812 [145] = 1'h0;
+ \8812 [146] = 1'h0;
+ \8812 [147] = 1'h0;
+ \8812 [148] = 1'h0;
+ \8812 [149] = 1'h0;
+ \8812 [150] = 1'h0;
+ \8812 [151] = 1'h0;
+ \8812 [152] = 1'h0;
+ \8812 [153] = 1'h0;
+ \8812 [154] = 1'h0;
+ \8812 [155] = 1'h0;
+ \8812 [156] = 1'h0;
+ \8812 [157] = 1'h0;
+ \8812 [158] = 1'h0;
+ \8812 [159] = 1'h0;
+ \8812 [160] = 1'h0;
+ \8812 [161] = 1'h0;
+ \8812 [162] = 1'h0;
+ \8812 [163] = 1'h0;
+ \8812 [164] = 1'h0;
+ \8812 [165] = 1'h0;
+ \8812 [166] = 1'h0;
+ \8812 [167] = 1'h0;
+ \8812 [168] = 1'h0;
+ \8812 [169] = 1'h0;
+ \8812 [170] = 1'h0;
+ \8812 [171] = 1'h0;
+ \8812 [172] = 1'h0;
+ \8812 [173] = 1'h0;
+ \8812 [174] = 1'h0;
+ \8812 [175] = 1'h0;
+ \8812 [176] = 1'h0;
+ \8812 [177] = 1'h0;
+ \8812 [178] = 1'h0;
+ \8812 [179] = 1'h0;
+ \8812 [180] = 1'h0;
+ \8812 [181] = 1'h0;
+ \8812 [182] = 1'h0;
+ \8812 [183] = 1'h0;
+ \8812 [184] = 1'h0;
+ \8812 [185] = 1'h0;
+ \8812 [186] = 1'h0;
+ \8812 [187] = 1'h0;
+ \8812 [188] = 1'h0;
+ \8812 [189] = 1'h0;
+ \8812 [190] = 1'h0;
+ \8812 [191] = 1'h0;
+ \8812 [192] = 1'h0;
+ \8812 [193] = 1'h0;
+ \8812 [194] = 1'h0;
+ \8812 [195] = 1'h0;
+ \8812 [196] = 1'h0;
+ \8812 [197] = 1'h0;
+ \8812 [198] = 1'h0;
+ \8812 [199] = 1'h0;
+ \8812 [200] = 1'h0;
+ \8812 [201] = 1'h0;
+ \8812 [202] = 1'h0;
+ \8812 [203] = 1'h0;
+ \8812 [204] = 1'h0;
+ \8812 [205] = 1'h0;
+ \8812 [206] = 1'h0;
+ \8812 [207] = 1'h0;
+ \8812 [208] = 1'h0;
+ \8812 [209] = 1'h0;
+ \8812 [210] = 1'h0;
+ \8812 [211] = 1'h0;
+ \8812 [212] = 1'h0;
+ \8812 [213] = 1'h0;
+ \8812 [214] = 1'h0;
+ \8812 [215] = 1'h0;
+ \8812 [216] = 1'h0;
+ \8812 [217] = 1'h0;
+ \8812 [218] = 1'h0;
+ \8812 [219] = 1'h0;
+ \8812 [220] = 1'h0;
+ \8812 [221] = 1'h0;
+ \8812 [222] = 1'h0;
+ \8812 [223] = 1'h0;
+ \8812 [224] = 1'h0;
+ \8812 [225] = 1'h0;
+ \8812 [226] = 1'h0;
+ \8812 [227] = 1'h0;
+ \8812 [228] = 1'h0;
+ \8812 [229] = 1'h0;
+ \8812 [230] = 1'h0;
+ \8812 [231] = 1'h0;
+ \8812 [232] = 1'h0;
+ \8812 [233] = 1'h0;
+ \8812 [234] = 1'h0;
+ \8812 [235] = 1'h0;
+ \8812 [236] = 1'h0;
+ \8812 [237] = 1'h0;
+ \8812 [238] = 1'h0;
+ \8812 [239] = 1'h0;
+ \8812 [240] = 1'h0;
+ \8812 [241] = 1'h0;
+ \8812 [242] = 1'h0;
+ \8812 [243] = 1'h0;
+ \8812 [244] = 1'h0;
+ \8812 [245] = 1'h0;
+ \8812 [246] = 1'h0;
+ \8812 [247] = 1'h0;
+ \8812 [248] = 1'h0;
+ \8812 [249] = 1'h0;
+ \8812 [250] = 1'h0;
+ \8812 [251] = 1'h0;
+ \8812 [252] = 1'h0;
+ \8812 [253] = 1'h0;
+ \8812 [254] = 1'h0;
+ \8812 [255] = 1'h0;
+ \8812 [256] = 1'h0;
+ \8812 [257] = 1'h0;
+ \8812 [258] = 1'h0;
+ \8812 [259] = 1'h0;
+ \8812 [260] = 1'h0;
+ \8812 [261] = 1'h0;
+ \8812 [262] = 1'h0;
+ \8812 [263] = 1'h0;
+ \8812 [264] = 1'h0;
+ \8812 [265] = 1'h0;
+ \8812 [266] = 1'h0;
+ \8812 [267] = 1'h0;
+ \8812 [268] = 1'h0;
+ \8812 [269] = 1'h0;
+ \8812 [270] = 1'h0;
+ \8812 [271] = 1'h0;
+ \8812 [272] = 1'h0;
+ \8812 [273] = 1'h0;
+ \8812 [274] = 1'h0;
+ \8812 [275] = 1'h0;
+ \8812 [276] = 1'h0;
+ \8812 [277] = 1'h0;
+ \8812 [278] = 1'h0;
+ \8812 [279] = 1'h0;
+ \8812 [280] = 1'h0;
+ \8812 [281] = 1'h0;
+ \8812 [282] = 1'h0;
+ \8812 [283] = 1'h0;
+ \8812 [284] = 1'h0;
+ \8812 [285] = 1'h0;
+ \8812 [286] = 1'h0;
+ \8812 [287] = 1'h0;
+ \8812 [288] = 1'h0;
+ \8812 [289] = 1'h0;
+ \8812 [290] = 1'h0;
+ \8812 [291] = 1'h0;
+ \8812 [292] = 1'h0;
+ \8812 [293] = 1'h0;
+ \8812 [294] = 1'h0;
+ \8812 [295] = 1'h0;
+ \8812 [296] = 1'h0;
+ \8812 [297] = 1'h0;
+ \8812 [298] = 1'h0;
+ \8812 [299] = 1'h0;
+ \8812 [300] = 1'h0;
+ \8812 [301] = 1'h0;
+ \8812 [302] = 1'h0;
+ \8812 [303] = 1'h0;
+ \8812 [304] = 1'h0;
+ \8812 [305] = 1'h0;
+ \8812 [306] = 1'h0;
+ \8812 [307] = 1'h0;
+ \8812 [308] = 1'h0;
+ \8812 [309] = 1'h0;
+ \8812 [310] = 1'h0;
+ \8812 [311] = 1'h0;
+ \8812 [312] = 1'h0;
+ \8812 [313] = 1'h0;
+ \8812 [314] = 1'h0;
+ \8812 [315] = 1'h0;
+ \8812 [316] = 1'h0;
+ \8812 [317] = 1'h0;
+ \8812 [318] = 1'h0;
+ \8812 [319] = 1'h0;
+ \8812 [320] = 1'h0;
+ \8812 [321] = 1'h0;
+ \8812 [322] = 1'h0;
+ \8812 [323] = 1'h0;
+ \8812 [324] = 1'h0;
+ \8812 [325] = 1'h0;
+ \8812 [326] = 1'h0;
+ \8812 [327] = 1'h0;
+ \8812 [328] = 1'h0;
+ \8812 [329] = 1'h0;
+ \8812 [330] = 1'h0;
+ \8812 [331] = 1'h0;
+ \8812 [332] = 1'h0;
+ \8812 [333] = 1'h0;
+ \8812 [334] = 1'h0;
+ \8812 [335] = 1'h0;
+ \8812 [336] = 1'h0;
+ \8812 [337] = 1'h0;
+ \8812 [338] = 1'h0;
+ \8812 [339] = 1'h0;
+ \8812 [340] = 1'h0;
+ \8812 [341] = 1'h0;
+ \8812 [342] = 1'h0;
+ \8812 [343] = 1'h0;
+ \8812 [344] = 1'h0;
+ \8812 [345] = 1'h0;
+ \8812 [346] = 1'h0;
+ \8812 [347] = 1'h0;
+ \8812 [348] = 1'h0;
+ \8812 [349] = 1'h0;
+ \8812 [350] = 1'h0;
+ \8812 [351] = 1'h0;
+ \8812 [352] = 1'h0;
+ \8812 [353] = 1'h0;
+ \8812 [354] = 1'h0;
+ \8812 [355] = 1'h0;
+ \8812 [356] = 1'h0;
+ \8812 [357] = 1'h0;
+ \8812 [358] = 1'h0;
+ \8812 [359] = 1'h0;
+ \8812 [360] = 1'h0;
+ \8812 [361] = 1'h0;
+ \8812 [362] = 1'h0;
+ \8812 [363] = 1'h0;
+ \8812 [364] = 1'h0;
+ \8812 [365] = 1'h0;
+ \8812 [366] = 1'h0;
+ \8812 [367] = 1'h0;
+ \8812 [368] = 1'h0;
+ \8812 [369] = 1'h0;
+ \8812 [370] = 1'h0;
+ \8812 [371] = 1'h0;
+ \8812 [372] = 1'h0;
+ \8812 [373] = 1'h0;
+ \8812 [374] = 1'h0;
+ \8812 [375] = 1'h0;
+ \8812 [376] = 1'h0;
+ \8812 [377] = 1'h0;
+ \8812 [378] = 1'h0;
+ \8812 [379] = 1'h0;
+ \8812 [380] = 1'h0;
+ \8812 [381] = 1'h0;
+ \8812 [382] = 1'h0;
+ \8812 [383] = 1'h0;
+ \8812 [384] = 1'h1;
+ \8812 [385] = 1'h1;
+ \8812 [386] = 1'h1;
+ \8812 [387] = 1'h1;
+ \8812 [388] = 1'h1;
+ \8812 [389] = 1'h1;
+ \8812 [390] = 1'h1;
+ \8812 [391] = 1'h1;
+ \8812 [392] = 1'h1;
+ \8812 [393] = 1'h1;
+ \8812 [394] = 1'h1;
+ \8812 [395] = 1'h1;
+ \8812 [396] = 1'h1;
+ \8812 [397] = 1'h1;
+ \8812 [398] = 1'h1;
+ \8812 [399] = 1'h1;
+ \8812 [400] = 1'h1;
+ \8812 [401] = 1'h1;
+ \8812 [402] = 1'h1;
+ \8812 [403] = 1'h1;
+ \8812 [404] = 1'h1;
+ \8812 [405] = 1'h1;
+ \8812 [406] = 1'h1;
+ \8812 [407] = 1'h1;
+ \8812 [408] = 1'h1;
+ \8812 [409] = 1'h1;
+ \8812 [410] = 1'h1;
+ \8812 [411] = 1'h1;
+ \8812 [412] = 1'h1;
+ \8812 [413] = 1'h1;
+ \8812 [414] = 1'h1;
+ \8812 [415] = 1'h1;
+ \8812 [416] = 1'h0;
+ \8812 [417] = 1'h0;
+ \8812 [418] = 1'h0;
+ \8812 [419] = 1'h0;
+ \8812 [420] = 1'h0;
+ \8812 [421] = 1'h0;
+ \8812 [422] = 1'h0;
+ \8812 [423] = 1'h0;
+ \8812 [424] = 1'h0;
+ \8812 [425] = 1'h0;
+ \8812 [426] = 1'h0;
+ \8812 [427] = 1'h0;
+ \8812 [428] = 1'h0;
+ \8812 [429] = 1'h0;
+ \8812 [430] = 1'h0;
+ \8812 [431] = 1'h0;
+ \8812 [432] = 1'h0;
+ \8812 [433] = 1'h0;
+ \8812 [434] = 1'h0;
+ \8812 [435] = 1'h0;
+ \8812 [436] = 1'h0;
+ \8812 [437] = 1'h0;
+ \8812 [438] = 1'h0;
+ \8812 [439] = 1'h0;
+ \8812 [440] = 1'h0;
+ \8812 [441] = 1'h0;
+ \8812 [442] = 1'h0;
+ \8812 [443] = 1'h0;
+ \8812 [444] = 1'h0;
+ \8812 [445] = 1'h0;
+ \8812 [446] = 1'h0;
+ \8812 [447] = 1'h0;
+ \8812 [448] = 1'h1;
+ \8812 [449] = 1'h1;
+ \8812 [450] = 1'h1;
+ \8812 [451] = 1'h1;
+ \8812 [452] = 1'h1;
+ \8812 [453] = 1'h1;
+ \8812 [454] = 1'h1;
+ \8812 [455] = 1'h1;
+ \8812 [456] = 1'h1;
+ \8812 [457] = 1'h1;
+ \8812 [458] = 1'h1;
+ \8812 [459] = 1'h1;
+ \8812 [460] = 1'h1;
+ \8812 [461] = 1'h1;
+ \8812 [462] = 1'h1;
+ \8812 [463] = 1'h1;
+ \8812 [464] = 1'h1;
+ \8812 [465] = 1'h1;
+ \8812 [466] = 1'h1;
+ \8812 [467] = 1'h1;
+ \8812 [468] = 1'h1;
+ \8812 [469] = 1'h1;
+ \8812 [470] = 1'h1;
+ \8812 [471] = 1'h1;
+ \8812 [472] = 1'h1;
+ \8812 [473] = 1'h1;
+ \8812 [474] = 1'h1;
+ \8812 [475] = 1'h1;
+ \8812 [476] = 1'h1;
+ \8812 [477] = 1'h1;
+ \8812 [478] = 1'h1;
+ \8812 [479] = 1'h1;
+ \8812 [480] = 1'h1;
+ \8812 [481] = 1'h1;
+ \8812 [482] = 1'h1;
+ \8812 [483] = 1'h1;
+ \8812 [484] = 1'h1;
+ \8812 [485] = 1'h1;
+ \8812 [486] = 1'h1;
+ \8812 [487] = 1'h1;
+ \8812 [488] = 1'h1;
+ \8812 [489] = 1'h1;
+ \8812 [490] = 1'h1;
+ \8812 [491] = 1'h1;
+ \8812 [492] = 1'h1;
+ \8812 [493] = 1'h1;
+ \8812 [494] = 1'h1;
+ \8812 [495] = 1'h1;
+ \8812 [496] = 1'h1;
+ \8812 [497] = 1'h1;
+ \8812 [498] = 1'h1;
+ \8812 [499] = 1'h1;
+ \8812 [500] = 1'h1;
+ \8812 [501] = 1'h1;
+ \8812 [502] = 1'h1;
+ \8812 [503] = 1'h1;
+ \8812 [504] = 1'h1;
+ \8812 [505] = 1'h1;
+ \8812 [506] = 1'h1;
+ \8812 [507] = 1'h1;
+ \8812 [508] = 1'h1;
+ \8812 [509] = 1'h1;
+ \8812 [510] = 1'h1;
+ \8812 [511] = 1'h1;
+ \8812 [512] = 1'h0;
+ \8812 [513] = 1'h0;
+ \8812 [514] = 1'h0;
+ \8812 [515] = 1'h0;
+ \8812 [516] = 1'h0;
+ \8812 [517] = 1'h0;
+ \8812 [518] = 1'h0;
+ \8812 [519] = 1'h0;
+ \8812 [520] = 1'h0;
+ \8812 [521] = 1'h0;
+ \8812 [522] = 1'h0;
+ \8812 [523] = 1'h0;
+ \8812 [524] = 1'h0;
+ \8812 [525] = 1'h0;
+ \8812 [526] = 1'h0;
+ \8812 [527] = 1'h0;
+ \8812 [528] = 1'h0;
+ \8812 [529] = 1'h0;
+ \8812 [530] = 1'h0;
+ \8812 [531] = 1'h0;
+ \8812 [532] = 1'h0;
+ \8812 [533] = 1'h0;
+ \8812 [534] = 1'h0;
+ \8812 [535] = 1'h0;
+ \8812 [536] = 1'h0;
+ \8812 [537] = 1'h0;
+ \8812 [538] = 1'h0;
+ \8812 [539] = 1'h0;
+ \8812 [540] = 1'h0;
+ \8812 [541] = 1'h0;
+ \8812 [542] = 1'h0;
+ \8812 [543] = 1'h0;
+ \8812 [544] = 1'h0;
+ \8812 [545] = 1'h0;
+ \8812 [546] = 1'h0;
+ \8812 [547] = 1'h0;
+ \8812 [548] = 1'h0;
+ \8812 [549] = 1'h0;
+ \8812 [550] = 1'h0;
+ \8812 [551] = 1'h0;
+ \8812 [552] = 1'h0;
+ \8812 [553] = 1'h0;
+ \8812 [554] = 1'h0;
+ \8812 [555] = 1'h0;
+ \8812 [556] = 1'h0;
+ \8812 [557] = 1'h0;
+ \8812 [558] = 1'h0;
+ \8812 [559] = 1'h0;
+ \8812 [560] = 1'h0;
+ \8812 [561] = 1'h0;
+ \8812 [562] = 1'h0;
+ \8812 [563] = 1'h0;
+ \8812 [564] = 1'h0;
+ \8812 [565] = 1'h0;
+ \8812 [566] = 1'h0;
+ \8812 [567] = 1'h0;
+ \8812 [568] = 1'h0;
+ \8812 [569] = 1'h0;
+ \8812 [570] = 1'h0;
+ \8812 [571] = 1'h0;
+ \8812 [572] = 1'h0;
+ \8812 [573] = 1'h0;
+ \8812 [574] = 1'h0;
+ \8812 [575] = 1'h0;
+ \8812 [576] = 1'h0;
+ \8812 [577] = 1'h0;
+ \8812 [578] = 1'h0;
+ \8812 [579] = 1'h0;
+ \8812 [580] = 1'h0;
+ \8812 [581] = 1'h0;
+ \8812 [582] = 1'h0;
+ \8812 [583] = 1'h0;
+ \8812 [584] = 1'h0;
+ \8812 [585] = 1'h0;
+ \8812 [586] = 1'h0;
+ \8812 [587] = 1'h0;
+ \8812 [588] = 1'h0;
+ \8812 [589] = 1'h0;
+ \8812 [590] = 1'h0;
+ \8812 [591] = 1'h0;
+ \8812 [592] = 1'h0;
+ \8812 [593] = 1'h0;
+ \8812 [594] = 1'h0;
+ \8812 [595] = 1'h0;
+ \8812 [596] = 1'h0;
+ \8812 [597] = 1'h0;
+ \8812 [598] = 1'h0;
+ \8812 [599] = 1'h0;
+ \8812 [600] = 1'h0;
+ \8812 [601] = 1'h0;
+ \8812 [602] = 1'h0;
+ \8812 [603] = 1'h0;
+ \8812 [604] = 1'h0;
+ \8812 [605] = 1'h0;
+ \8812 [606] = 1'h0;
+ \8812 [607] = 1'h0;
+ \8812 [608] = 1'h0;
+ \8812 [609] = 1'h0;
+ \8812 [610] = 1'h0;
+ \8812 [611] = 1'h0;
+ \8812 [612] = 1'h0;
+ \8812 [613] = 1'h0;
+ \8812 [614] = 1'h0;
+ \8812 [615] = 1'h0;
+ \8812 [616] = 1'h0;
+ \8812 [617] = 1'h0;
+ \8812 [618] = 1'h0;
+ \8812 [619] = 1'h0;
+ \8812 [620] = 1'h0;
+ \8812 [621] = 1'h0;
+ \8812 [622] = 1'h0;
+ \8812 [623] = 1'h0;
+ \8812 [624] = 1'h0;
+ \8812 [625] = 1'h0;
+ \8812 [626] = 1'h0;
+ \8812 [627] = 1'h0;
+ \8812 [628] = 1'h0;
+ \8812 [629] = 1'h0;
+ \8812 [630] = 1'h0;
+ \8812 [631] = 1'h0;
+ \8812 [632] = 1'h0;
+ \8812 [633] = 1'h0;
+ \8812 [634] = 1'h0;
+ \8812 [635] = 1'h0;
+ \8812 [636] = 1'h0;
+ \8812 [637] = 1'h0;
+ \8812 [638] = 1'h0;
+ \8812 [639] = 1'h0;
+ \8812 [640] = 1'h0;
+ \8812 [641] = 1'h0;
+ \8812 [642] = 1'h0;
+ \8812 [643] = 1'h0;
+ \8812 [644] = 1'h0;
+ \8812 [645] = 1'h0;
+ \8812 [646] = 1'h0;
+ \8812 [647] = 1'h0;
+ \8812 [648] = 1'h0;
+ \8812 [649] = 1'h0;
+ \8812 [650] = 1'h0;
+ \8812 [651] = 1'h0;
+ \8812 [652] = 1'h0;
+ \8812 [653] = 1'h0;
+ \8812 [654] = 1'h0;
+ \8812 [655] = 1'h0;
+ \8812 [656] = 1'h0;
+ \8812 [657] = 1'h0;
+ \8812 [658] = 1'h0;
+ \8812 [659] = 1'h0;
+ \8812 [660] = 1'h0;
+ \8812 [661] = 1'h0;
+ \8812 [662] = 1'h0;
+ \8812 [663] = 1'h0;
+ \8812 [664] = 1'h0;
+ \8812 [665] = 1'h0;
+ \8812 [666] = 1'h0;
+ \8812 [667] = 1'h0;
+ \8812 [668] = 1'h0;
+ \8812 [669] = 1'h0;
+ \8812 [670] = 1'h0;
+ \8812 [671] = 1'h0;
+ \8812 [672] = 1'h0;
+ \8812 [673] = 1'h0;
+ \8812 [674] = 1'h0;
+ \8812 [675] = 1'h0;
+ \8812 [676] = 1'h0;
+ \8812 [677] = 1'h0;
+ \8812 [678] = 1'h0;
+ \8812 [679] = 1'h0;
+ \8812 [680] = 1'h0;
+ \8812 [681] = 1'h0;
+ \8812 [682] = 1'h0;
+ \8812 [683] = 1'h0;
+ \8812 [684] = 1'h0;
+ \8812 [685] = 1'h0;
+ \8812 [686] = 1'h0;
+ \8812 [687] = 1'h0;
+ \8812 [688] = 1'h0;
+ \8812 [689] = 1'h0;
+ \8812 [690] = 1'h0;
+ \8812 [691] = 1'h0;
+ \8812 [692] = 1'h0;
+ \8812 [693] = 1'h0;
+ \8812 [694] = 1'h0;
+ \8812 [695] = 1'h0;
+ \8812 [696] = 1'h0;
+ \8812 [697] = 1'h0;
+ \8812 [698] = 1'h0;
+ \8812 [699] = 1'h0;
+ \8812 [700] = 1'h0;
+ \8812 [701] = 1'h0;
+ \8812 [702] = 1'h0;
+ \8812 [703] = 1'h0;
+ \8812 [704] = 1'h0;
+ \8812 [705] = 1'h0;
+ \8812 [706] = 1'h0;
+ \8812 [707] = 1'h0;
+ \8812 [708] = 1'h0;
+ \8812 [709] = 1'h0;
+ \8812 [710] = 1'h0;
+ \8812 [711] = 1'h0;
+ \8812 [712] = 1'h0;
+ \8812 [713] = 1'h0;
+ \8812 [714] = 1'h0;
+ \8812 [715] = 1'h0;
+ \8812 [716] = 1'h0;
+ \8812 [717] = 1'h0;
+ \8812 [718] = 1'h0;
+ \8812 [719] = 1'h0;
+ \8812 [720] = 1'h0;
+ \8812 [721] = 1'h0;
+ \8812 [722] = 1'h0;
+ \8812 [723] = 1'h0;
+ \8812 [724] = 1'h0;
+ \8812 [725] = 1'h0;
+ \8812 [726] = 1'h0;
+ \8812 [727] = 1'h0;
+ \8812 [728] = 1'h0;
+ \8812 [729] = 1'h0;
+ \8812 [730] = 1'h0;
+ \8812 [731] = 1'h0;
+ \8812 [732] = 1'h0;
+ \8812 [733] = 1'h0;
+ \8812 [734] = 1'h0;
+ \8812 [735] = 1'h0;
+ \8812 [736] = 1'h0;
+ \8812 [737] = 1'h0;
+ \8812 [738] = 1'h0;
+ \8812 [739] = 1'h0;
+ \8812 [740] = 1'h0;
+ \8812 [741] = 1'h0;
+ \8812 [742] = 1'h0;
+ \8812 [743] = 1'h0;
+ \8812 [744] = 1'h0;
+ \8812 [745] = 1'h0;
+ \8812 [746] = 1'h0;
+ \8812 [747] = 1'h0;
+ \8812 [748] = 1'h0;
+ \8812 [749] = 1'h0;
+ \8812 [750] = 1'h0;
+ \8812 [751] = 1'h0;
+ \8812 [752] = 1'h0;
+ \8812 [753] = 1'h0;
+ \8812 [754] = 1'h0;
+ \8812 [755] = 1'h0;
+ \8812 [756] = 1'h0;
+ \8812 [757] = 1'h0;
+ \8812 [758] = 1'h0;
+ \8812 [759] = 1'h0;
+ \8812 [760] = 1'h0;
+ \8812 [761] = 1'h0;
+ \8812 [762] = 1'h0;
+ \8812 [763] = 1'h0;
+ \8812 [764] = 1'h0;
+ \8812 [765] = 1'h0;
+ \8812 [766] = 1'h0;
+ \8812 [767] = 1'h0;
+ \8812 [768] = 1'h0;
+ \8812 [769] = 1'h0;
+ \8812 [770] = 1'h0;
+ \8812 [771] = 1'h0;
+ \8812 [772] = 1'h0;
+ \8812 [773] = 1'h0;
+ \8812 [774] = 1'h0;
+ \8812 [775] = 1'h0;
+ \8812 [776] = 1'h0;
+ \8812 [777] = 1'h0;
+ \8812 [778] = 1'h0;
+ \8812 [779] = 1'h0;
+ \8812 [780] = 1'h0;
+ \8812 [781] = 1'h0;
+ \8812 [782] = 1'h0;
+ \8812 [783] = 1'h0;
+ \8812 [784] = 1'h0;
+ \8812 [785] = 1'h0;
+ \8812 [786] = 1'h0;
+ \8812 [787] = 1'h0;
+ \8812 [788] = 1'h0;
+ \8812 [789] = 1'h0;
+ \8812 [790] = 1'h0;
+ \8812 [791] = 1'h0;
+ \8812 [792] = 1'h0;
+ \8812 [793] = 1'h0;
+ \8812 [794] = 1'h0;
+ \8812 [795] = 1'h0;
+ \8812 [796] = 1'h0;
+ \8812 [797] = 1'h0;
+ \8812 [798] = 1'h0;
+ \8812 [799] = 1'h0;
+ \8812 [800] = 1'h0;
+ \8812 [801] = 1'h0;
+ \8812 [802] = 1'h0;
+ \8812 [803] = 1'h0;
+ \8812 [804] = 1'h0;
+ \8812 [805] = 1'h0;
+ \8812 [806] = 1'h0;
+ \8812 [807] = 1'h0;
+ \8812 [808] = 1'h0;
+ \8812 [809] = 1'h0;
+ \8812 [810] = 1'h0;
+ \8812 [811] = 1'h0;
+ \8812 [812] = 1'h0;
+ \8812 [813] = 1'h0;
+ \8812 [814] = 1'h0;
+ \8812 [815] = 1'h0;
+ \8812 [816] = 1'h0;
+ \8812 [817] = 1'h0;
+ \8812 [818] = 1'h0;
+ \8812 [819] = 1'h0;
+ \8812 [820] = 1'h0;
+ \8812 [821] = 1'h0;
+ \8812 [822] = 1'h0;
+ \8812 [823] = 1'h0;
+ \8812 [824] = 1'h0;
+ \8812 [825] = 1'h0;
+ \8812 [826] = 1'h0;
+ \8812 [827] = 1'h0;
+ \8812 [828] = 1'h0;
+ \8812 [829] = 1'h0;
+ \8812 [830] = 1'h0;
+ \8812 [831] = 1'h0;
+ \8812 [832] = 1'h0;
+ \8812 [833] = 1'h0;
+ \8812 [834] = 1'h0;
+ \8812 [835] = 1'h0;
+ \8812 [836] = 1'h0;
+ \8812 [837] = 1'h0;
+ \8812 [838] = 1'h0;
+ \8812 [839] = 1'h0;
+ \8812 [840] = 1'h0;
+ \8812 [841] = 1'h0;
+ \8812 [842] = 1'h0;
+ \8812 [843] = 1'h0;
+ \8812 [844] = 1'h0;
+ \8812 [845] = 1'h0;
+ \8812 [846] = 1'h0;
+ \8812 [847] = 1'h0;
+ \8812 [848] = 1'h0;
+ \8812 [849] = 1'h0;
+ \8812 [850] = 1'h0;
+ \8812 [851] = 1'h0;
+ \8812 [852] = 1'h0;
+ \8812 [853] = 1'h0;
+ \8812 [854] = 1'h0;
+ \8812 [855] = 1'h0;
+ \8812 [856] = 1'h0;
+ \8812 [857] = 1'h0;
+ \8812 [858] = 1'h0;
+ \8812 [859] = 1'h0;
+ \8812 [860] = 1'h0;
+ \8812 [861] = 1'h0;
+ \8812 [862] = 1'h0;
+ \8812 [863] = 1'h0;
+ \8812 [864] = 1'h0;
+ \8812 [865] = 1'h0;
+ \8812 [866] = 1'h0;
+ \8812 [867] = 1'h0;
+ \8812 [868] = 1'h0;
+ \8812 [869] = 1'h0;
+ \8812 [870] = 1'h0;
+ \8812 [871] = 1'h0;
+ \8812 [872] = 1'h0;
+ \8812 [873] = 1'h0;
+ \8812 [874] = 1'h0;
+ \8812 [875] = 1'h0;
+ \8812 [876] = 1'h0;
+ \8812 [877] = 1'h0;
+ \8812 [878] = 1'h0;
+ \8812 [879] = 1'h0;
+ \8812 [880] = 1'h0;
+ \8812 [881] = 1'h0;
+ \8812 [882] = 1'h0;
+ \8812 [883] = 1'h0;
+ \8812 [884] = 1'h0;
+ \8812 [885] = 1'h0;
+ \8812 [886] = 1'h0;
+ \8812 [887] = 1'h0;
+ \8812 [888] = 1'h0;
+ \8812 [889] = 1'h0;
+ \8812 [890] = 1'h0;
+ \8812 [891] = 1'h0;
+ \8812 [892] = 1'h0;
+ \8812 [893] = 1'h0;
+ \8812 [894] = 1'h0;
+ \8812 [895] = 1'h0;
+ \8812 [896] = 1'h0;
+ \8812 [897] = 1'h0;
+ \8812 [898] = 1'h0;
+ \8812 [899] = 1'h0;
+ \8812 [900] = 1'h0;
+ \8812 [901] = 1'h0;
+ \8812 [902] = 1'h0;
+ \8812 [903] = 1'h0;
+ \8812 [904] = 1'h0;
+ \8812 [905] = 1'h0;
+ \8812 [906] = 1'h0;
+ \8812 [907] = 1'h0;
+ \8812 [908] = 1'h0;
+ \8812 [909] = 1'h0;
+ \8812 [910] = 1'h0;
+ \8812 [911] = 1'h0;
+ \8812 [912] = 1'h0;
+ \8812 [913] = 1'h0;
+ \8812 [914] = 1'h0;
+ \8812 [915] = 1'h0;
+ \8812 [916] = 1'h0;
+ \8812 [917] = 1'h0;
+ \8812 [918] = 1'h0;
+ \8812 [919] = 1'h0;
+ \8812 [920] = 1'h0;
+ \8812 [921] = 1'h0;
+ \8812 [922] = 1'h0;
+ \8812 [923] = 1'h0;
+ \8812 [924] = 1'h0;
+ \8812 [925] = 1'h0;
+ \8812 [926] = 1'h0;
+ \8812 [927] = 1'h0;
+ \8812 [928] = 1'h0;
+ \8812 [929] = 1'h0;
+ \8812 [930] = 1'h0;
+ \8812 [931] = 1'h0;
+ \8812 [932] = 1'h0;
+ \8812 [933] = 1'h0;
+ \8812 [934] = 1'h0;
+ \8812 [935] = 1'h0;
+ \8812 [936] = 1'h0;
+ \8812 [937] = 1'h0;
+ \8812 [938] = 1'h0;
+ \8812 [939] = 1'h0;
+ \8812 [940] = 1'h0;
+ \8812 [941] = 1'h0;
+ \8812 [942] = 1'h0;
+ \8812 [943] = 1'h0;
+ \8812 [944] = 1'h0;
+ \8812 [945] = 1'h0;
+ \8812 [946] = 1'h0;
+ \8812 [947] = 1'h0;
+ \8812 [948] = 1'h0;
+ \8812 [949] = 1'h0;
+ \8812 [950] = 1'h0;
+ \8812 [951] = 1'h0;
+ \8812 [952] = 1'h0;
+ \8812 [953] = 1'h0;
+ \8812 [954] = 1'h0;
+ \8812 [955] = 1'h0;
+ \8812 [956] = 1'h0;
+ \8812 [957] = 1'h0;
+ \8812 [958] = 1'h0;
+ \8812 [959] = 1'h0;
+ \8812 [960] = 1'h0;
+ \8812 [961] = 1'h0;
+ \8812 [962] = 1'h0;
+ \8812 [963] = 1'h0;
+ \8812 [964] = 1'h0;
+ \8812 [965] = 1'h0;
+ \8812 [966] = 1'h0;
+ \8812 [967] = 1'h0;
+ \8812 [968] = 1'h0;
+ \8812 [969] = 1'h0;
+ \8812 [970] = 1'h0;
+ \8812 [971] = 1'h0;
+ \8812 [972] = 1'h0;
+ \8812 [973] = 1'h0;
+ \8812 [974] = 1'h0;
+ \8812 [975] = 1'h0;
+ \8812 [976] = 1'h0;
+ \8812 [977] = 1'h0;
+ \8812 [978] = 1'h0;
+ \8812 [979] = 1'h0;
+ \8812 [980] = 1'h0;
+ \8812 [981] = 1'h0;
+ \8812 [982] = 1'h0;
+ \8812 [983] = 1'h0;
+ \8812 [984] = 1'h0;
+ \8812 [985] = 1'h0;
+ \8812 [986] = 1'h0;
+ \8812 [987] = 1'h0;
+ \8812 [988] = 1'h0;
+ \8812 [989] = 1'h0;
+ \8812 [990] = 1'h0;
+ \8812 [991] = 1'h0;
+ \8812 [992] = 1'h0;
+ \8812 [993] = 1'h0;
+ \8812 [994] = 1'h0;
+ \8812 [995] = 1'h0;
+ \8812 [996] = 1'h0;
+ \8812 [997] = 1'h0;
+ \8812 [998] = 1'h0;
+ \8812 [999] = 1'h0;
+ \8812 [1000] = 1'h0;
+ \8812 [1001] = 1'h0;
+ \8812 [1002] = 1'h0;
+ \8812 [1003] = 1'h0;
+ \8812 [1004] = 1'h0;
+ \8812 [1005] = 1'h0;
+ \8812 [1006] = 1'h0;
+ \8812 [1007] = 1'h0;
+ \8812 [1008] = 1'h0;
+ \8812 [1009] = 1'h0;
+ \8812 [1010] = 1'h0;
+ \8812 [1011] = 1'h0;
+ \8812 [1012] = 1'h0;
+ \8812 [1013] = 1'h0;
+ \8812 [1014] = 1'h0;
+ \8812 [1015] = 1'h0;
+ \8812 [1016] = 1'h0;
+ \8812 [1017] = 1'h0;
+ \8812 [1018] = 1'h0;
+ \8812 [1019] = 1'h0;
+ \8812 [1020] = 1'h0;
+ \8812 [1021] = 1'h0;
+ \8812 [1022] = 1'h0;
+ \8812 [1023] = 1'h0;
+ \8812 [1024] = 1'h0;
+ \8812 [1025] = 1'h0;
+ \8812 [1026] = 1'h0;
+ \8812 [1027] = 1'h0;
+ \8812 [1028] = 1'h0;
+ \8812 [1029] = 1'h0;
+ \8812 [1030] = 1'h0;
+ \8812 [1031] = 1'h0;
+ \8812 [1032] = 1'h0;
+ \8812 [1033] = 1'h0;
+ \8812 [1034] = 1'h0;
+ \8812 [1035] = 1'h0;
+ \8812 [1036] = 1'h0;
+ \8812 [1037] = 1'h0;
+ \8812 [1038] = 1'h0;
+ \8812 [1039] = 1'h0;
+ \8812 [1040] = 1'h0;
+ \8812 [1041] = 1'h0;
+ \8812 [1042] = 1'h0;
+ \8812 [1043] = 1'h0;
+ \8812 [1044] = 1'h0;
+ \8812 [1045] = 1'h0;
+ \8812 [1046] = 1'h0;
+ \8812 [1047] = 1'h0;
+ \8812 [1048] = 1'h0;
+ \8812 [1049] = 1'h0;
+ \8812 [1050] = 1'h0;
+ \8812 [1051] = 1'h0;
+ \8812 [1052] = 1'h0;
+ \8812 [1053] = 1'h0;
+ \8812 [1054] = 1'h0;
+ \8812 [1055] = 1'h0;
+ \8812 [1056] = 1'h0;
+ \8812 [1057] = 1'h0;
+ \8812 [1058] = 1'h0;
+ \8812 [1059] = 1'h0;
+ \8812 [1060] = 1'h0;
+ \8812 [1061] = 1'h0;
+ \8812 [1062] = 1'h0;
+ \8812 [1063] = 1'h0;
+ \8812 [1064] = 1'h0;
+ \8812 [1065] = 1'h0;
+ \8812 [1066] = 1'h0;
+ \8812 [1067] = 1'h0;
+ \8812 [1068] = 1'h0;
+ \8812 [1069] = 1'h0;
+ \8812 [1070] = 1'h0;
+ \8812 [1071] = 1'h0;
+ \8812 [1072] = 1'h0;
+ \8812 [1073] = 1'h0;
+ \8812 [1074] = 1'h0;
+ \8812 [1075] = 1'h0;
+ \8812 [1076] = 1'h0;
+ \8812 [1077] = 1'h0;
+ \8812 [1078] = 1'h0;
+ \8812 [1079] = 1'h0;
+ \8812 [1080] = 1'h0;
+ \8812 [1081] = 1'h0;
+ \8812 [1082] = 1'h0;
+ \8812 [1083] = 1'h0;
+ \8812 [1084] = 1'h0;
+ \8812 [1085] = 1'h0;
+ \8812 [1086] = 1'h0;
+ \8812 [1087] = 1'h0;
+ \8812 [1088] = 1'h0;
+ \8812 [1089] = 1'h0;
+ \8812 [1090] = 1'h0;
+ \8812 [1091] = 1'h0;
+ \8812 [1092] = 1'h0;
+ \8812 [1093] = 1'h0;
+ \8812 [1094] = 1'h0;
+ \8812 [1095] = 1'h0;
+ \8812 [1096] = 1'h0;
+ \8812 [1097] = 1'h0;
+ \8812 [1098] = 1'h0;
+ \8812 [1099] = 1'h0;
+ \8812 [1100] = 1'h0;
+ \8812 [1101] = 1'h0;
+ \8812 [1102] = 1'h0;
+ \8812 [1103] = 1'h0;
+ \8812 [1104] = 1'h0;
+ \8812 [1105] = 1'h0;
+ \8812 [1106] = 1'h0;
+ \8812 [1107] = 1'h0;
+ \8812 [1108] = 1'h0;
+ \8812 [1109] = 1'h0;
+ \8812 [1110] = 1'h0;
+ \8812 [1111] = 1'h0;
+ \8812 [1112] = 1'h0;
+ \8812 [1113] = 1'h0;
+ \8812 [1114] = 1'h0;
+ \8812 [1115] = 1'h0;
+ \8812 [1116] = 1'h0;
+ \8812 [1117] = 1'h0;
+ \8812 [1118] = 1'h0;
+ \8812 [1119] = 1'h0;
+ \8812 [1120] = 1'h0;
+ \8812 [1121] = 1'h0;
+ \8812 [1122] = 1'h0;
+ \8812 [1123] = 1'h0;
+ \8812 [1124] = 1'h0;
+ \8812 [1125] = 1'h0;
+ \8812 [1126] = 1'h0;
+ \8812 [1127] = 1'h0;
+ \8812 [1128] = 1'h0;
+ \8812 [1129] = 1'h0;
+ \8812 [1130] = 1'h0;
+ \8812 [1131] = 1'h0;
+ \8812 [1132] = 1'h0;
+ \8812 [1133] = 1'h0;
+ \8812 [1134] = 1'h0;
+ \8812 [1135] = 1'h0;
+ \8812 [1136] = 1'h0;
+ \8812 [1137] = 1'h0;
+ \8812 [1138] = 1'h0;
+ \8812 [1139] = 1'h0;
+ \8812 [1140] = 1'h0;
+ \8812 [1141] = 1'h0;
+ \8812 [1142] = 1'h0;
+ \8812 [1143] = 1'h0;
+ \8812 [1144] = 1'h0;
+ \8812 [1145] = 1'h0;
+ \8812 [1146] = 1'h0;
+ \8812 [1147] = 1'h0;
+ \8812 [1148] = 1'h0;
+ \8812 [1149] = 1'h0;
+ \8812 [1150] = 1'h0;
+ \8812 [1151] = 1'h0;
+ \8812 [1152] = 1'h0;
+ \8812 [1153] = 1'h0;
+ \8812 [1154] = 1'h0;
+ \8812 [1155] = 1'h0;
+ \8812 [1156] = 1'h0;
+ \8812 [1157] = 1'h0;
+ \8812 [1158] = 1'h0;
+ \8812 [1159] = 1'h0;
+ \8812 [1160] = 1'h0;
+ \8812 [1161] = 1'h0;
+ \8812 [1162] = 1'h0;
+ \8812 [1163] = 1'h0;
+ \8812 [1164] = 1'h0;
+ \8812 [1165] = 1'h0;
+ \8812 [1166] = 1'h0;
+ \8812 [1167] = 1'h0;
+ \8812 [1168] = 1'h0;
+ \8812 [1169] = 1'h0;
+ \8812 [1170] = 1'h0;
+ \8812 [1171] = 1'h0;
+ \8812 [1172] = 1'h0;
+ \8812 [1173] = 1'h0;
+ \8812 [1174] = 1'h0;
+ \8812 [1175] = 1'h0;
+ \8812 [1176] = 1'h0;
+ \8812 [1177] = 1'h0;
+ \8812 [1178] = 1'h0;
+ \8812 [1179] = 1'h0;
+ \8812 [1180] = 1'h0;
+ \8812 [1181] = 1'h0;
+ \8812 [1182] = 1'h0;
+ \8812 [1183] = 1'h0;
+ \8812 [1184] = 1'h0;
+ \8812 [1185] = 1'h0;
+ \8812 [1186] = 1'h0;
+ \8812 [1187] = 1'h0;
+ \8812 [1188] = 1'h0;
+ \8812 [1189] = 1'h0;
+ \8812 [1190] = 1'h0;
+ \8812 [1191] = 1'h0;
+ \8812 [1192] = 1'h0;
+ \8812 [1193] = 1'h0;
+ \8812 [1194] = 1'h0;
+ \8812 [1195] = 1'h0;
+ \8812 [1196] = 1'h0;
+ \8812 [1197] = 1'h0;
+ \8812 [1198] = 1'h0;
+ \8812 [1199] = 1'h0;
+ \8812 [1200] = 1'h0;
+ \8812 [1201] = 1'h0;
+ \8812 [1202] = 1'h0;
+ \8812 [1203] = 1'h0;
+ \8812 [1204] = 1'h0;
+ \8812 [1205] = 1'h0;
+ \8812 [1206] = 1'h0;
+ \8812 [1207] = 1'h0;
+ \8812 [1208] = 1'h0;
+ \8812 [1209] = 1'h0;
+ \8812 [1210] = 1'h0;
+ \8812 [1211] = 1'h0;
+ \8812 [1212] = 1'h0;
+ \8812 [1213] = 1'h0;
+ \8812 [1214] = 1'h0;
+ \8812 [1215] = 1'h0;
+ \8812 [1216] = 1'h0;
+ \8812 [1217] = 1'h0;
+ \8812 [1218] = 1'h0;
+ \8812 [1219] = 1'h0;
+ \8812 [1220] = 1'h0;
+ \8812 [1221] = 1'h0;
+ \8812 [1222] = 1'h0;
+ \8812 [1223] = 1'h0;
+ \8812 [1224] = 1'h0;
+ \8812 [1225] = 1'h0;
+ \8812 [1226] = 1'h0;
+ \8812 [1227] = 1'h0;
+ \8812 [1228] = 1'h0;
+ \8812 [1229] = 1'h0;
+ \8812 [1230] = 1'h0;
+ \8812 [1231] = 1'h0;
+ \8812 [1232] = 1'h0;
+ \8812 [1233] = 1'h0;
+ \8812 [1234] = 1'h0;
+ \8812 [1235] = 1'h0;
+ \8812 [1236] = 1'h0;
+ \8812 [1237] = 1'h0;
+ \8812 [1238] = 1'h0;
+ \8812 [1239] = 1'h0;
+ \8812 [1240] = 1'h0;
+ \8812 [1241] = 1'h0;
+ \8812 [1242] = 1'h0;
+ \8812 [1243] = 1'h0;
+ \8812 [1244] = 1'h0;
+ \8812 [1245] = 1'h0;
+ \8812 [1246] = 1'h0;
+ \8812 [1247] = 1'h0;
+ \8812 [1248] = 1'h0;
+ \8812 [1249] = 1'h0;
+ \8812 [1250] = 1'h0;
+ \8812 [1251] = 1'h0;
+ \8812 [1252] = 1'h0;
+ \8812 [1253] = 1'h0;
+ \8812 [1254] = 1'h0;
+ \8812 [1255] = 1'h0;
+ \8812 [1256] = 1'h0;
+ \8812 [1257] = 1'h0;
+ \8812 [1258] = 1'h0;
+ \8812 [1259] = 1'h0;
+ \8812 [1260] = 1'h0;
+ \8812 [1261] = 1'h0;
+ \8812 [1262] = 1'h0;
+ \8812 [1263] = 1'h0;
+ \8812 [1264] = 1'h0;
+ \8812 [1265] = 1'h0;
+ \8812 [1266] = 1'h0;
+ \8812 [1267] = 1'h0;
+ \8812 [1268] = 1'h0;
+ \8812 [1269] = 1'h0;
+ \8812 [1270] = 1'h0;
+ \8812 [1271] = 1'h0;
+ \8812 [1272] = 1'h0;
+ \8812 [1273] = 1'h0;
+ \8812 [1274] = 1'h0;
+ \8812 [1275] = 1'h0;
+ \8812 [1276] = 1'h0;
+ \8812 [1277] = 1'h0;
+ \8812 [1278] = 1'h0;
+ \8812 [1279] = 1'h0;
+ \8812 [1280] = 1'h0;
+ \8812 [1281] = 1'h0;
+ \8812 [1282] = 1'h0;
+ \8812 [1283] = 1'h0;
+ \8812 [1284] = 1'h0;
+ \8812 [1285] = 1'h0;
+ \8812 [1286] = 1'h0;
+ \8812 [1287] = 1'h0;
+ \8812 [1288] = 1'h0;
+ \8812 [1289] = 1'h0;
+ \8812 [1290] = 1'h0;
+ \8812 [1291] = 1'h0;
+ \8812 [1292] = 1'h0;
+ \8812 [1293] = 1'h0;
+ \8812 [1294] = 1'h0;
+ \8812 [1295] = 1'h0;
+ \8812 [1296] = 1'h0;
+ \8812 [1297] = 1'h0;
+ \8812 [1298] = 1'h0;
+ \8812 [1299] = 1'h0;
+ \8812 [1300] = 1'h0;
+ \8812 [1301] = 1'h0;
+ \8812 [1302] = 1'h0;
+ \8812 [1303] = 1'h0;
+ \8812 [1304] = 1'h0;
+ \8812 [1305] = 1'h0;
+ \8812 [1306] = 1'h0;
+ \8812 [1307] = 1'h0;
+ \8812 [1308] = 1'h0;
+ \8812 [1309] = 1'h0;
+ \8812 [1310] = 1'h0;
+ \8812 [1311] = 1'h0;
+ \8812 [1312] = 1'h0;
+ \8812 [1313] = 1'h0;
+ \8812 [1314] = 1'h0;
+ \8812 [1315] = 1'h0;
+ \8812 [1316] = 1'h0;
+ \8812 [1317] = 1'h0;
+ \8812 [1318] = 1'h0;
+ \8812 [1319] = 1'h0;
+ \8812 [1320] = 1'h0;
+ \8812 [1321] = 1'h0;
+ \8812 [1322] = 1'h0;
+ \8812 [1323] = 1'h0;
+ \8812 [1324] = 1'h0;
+ \8812 [1325] = 1'h0;
+ \8812 [1326] = 1'h0;
+ \8812 [1327] = 1'h0;
+ \8812 [1328] = 1'h0;
+ \8812 [1329] = 1'h0;
+ \8812 [1330] = 1'h0;
+ \8812 [1331] = 1'h0;
+ \8812 [1332] = 1'h0;
+ \8812 [1333] = 1'h0;
+ \8812 [1334] = 1'h0;
+ \8812 [1335] = 1'h0;
+ \8812 [1336] = 1'h0;
+ \8812 [1337] = 1'h0;
+ \8812 [1338] = 1'h0;
+ \8812 [1339] = 1'h0;
+ \8812 [1340] = 1'h0;
+ \8812 [1341] = 1'h0;
+ \8812 [1342] = 1'h0;
+ \8812 [1343] = 1'h0;
+ \8812 [1344] = 1'h0;
+ \8812 [1345] = 1'h0;
+ \8812 [1346] = 1'h0;
+ \8812 [1347] = 1'h0;
+ \8812 [1348] = 1'h0;
+ \8812 [1349] = 1'h0;
+ \8812 [1350] = 1'h0;
+ \8812 [1351] = 1'h0;
+ \8812 [1352] = 1'h0;
+ \8812 [1353] = 1'h0;
+ \8812 [1354] = 1'h0;
+ \8812 [1355] = 1'h0;
+ \8812 [1356] = 1'h0;
+ \8812 [1357] = 1'h0;
+ \8812 [1358] = 1'h0;
+ \8812 [1359] = 1'h0;
+ \8812 [1360] = 1'h0;
+ \8812 [1361] = 1'h0;
+ \8812 [1362] = 1'h0;
+ \8812 [1363] = 1'h0;
+ \8812 [1364] = 1'h0;
+ \8812 [1365] = 1'h0;
+ \8812 [1366] = 1'h0;
+ \8812 [1367] = 1'h0;
+ \8812 [1368] = 1'h0;
+ \8812 [1369] = 1'h0;
+ \8812 [1370] = 1'h0;
+ \8812 [1371] = 1'h0;
+ \8812 [1372] = 1'h0;
+ \8812 [1373] = 1'h0;
+ \8812 [1374] = 1'h0;
+ \8812 [1375] = 1'h0;
+ \8812 [1376] = 1'h0;
+ \8812 [1377] = 1'h0;
+ \8812 [1378] = 1'h0;
+ \8812 [1379] = 1'h0;
+ \8812 [1380] = 1'h0;
+ \8812 [1381] = 1'h0;
+ \8812 [1382] = 1'h0;
+ \8812 [1383] = 1'h0;
+ \8812 [1384] = 1'h0;
+ \8812 [1385] = 1'h0;
+ \8812 [1386] = 1'h0;
+ \8812 [1387] = 1'h0;
+ \8812 [1388] = 1'h0;
+ \8812 [1389] = 1'h0;
+ \8812 [1390] = 1'h0;
+ \8812 [1391] = 1'h0;
+ \8812 [1392] = 1'h0;
+ \8812 [1393] = 1'h0;
+ \8812 [1394] = 1'h0;
+ \8812 [1395] = 1'h0;
+ \8812 [1396] = 1'h0;
+ \8812 [1397] = 1'h0;
+ \8812 [1398] = 1'h0;
+ \8812 [1399] = 1'h0;
+ \8812 [1400] = 1'h0;
+ \8812 [1401] = 1'h0;
+ \8812 [1402] = 1'h0;
+ \8812 [1403] = 1'h0;
+ \8812 [1404] = 1'h0;
+ \8812 [1405] = 1'h0;
+ \8812 [1406] = 1'h0;
+ \8812 [1407] = 1'h0;
+ \8812 [1408] = 1'h0;
+ \8812 [1409] = 1'h0;
+ \8812 [1410] = 1'h0;
+ \8812 [1411] = 1'h0;
+ \8812 [1412] = 1'h0;
+ \8812 [1413] = 1'h0;
+ \8812 [1414] = 1'h0;
+ \8812 [1415] = 1'h0;
+ \8812 [1416] = 1'h0;
+ \8812 [1417] = 1'h0;
+ \8812 [1418] = 1'h0;
+ \8812 [1419] = 1'h0;
+ \8812 [1420] = 1'h0;
+ \8812 [1421] = 1'h0;
+ \8812 [1422] = 1'h0;
+ \8812 [1423] = 1'h0;
+ \8812 [1424] = 1'h0;
+ \8812 [1425] = 1'h0;
+ \8812 [1426] = 1'h0;
+ \8812 [1427] = 1'h0;
+ \8812 [1428] = 1'h0;
+ \8812 [1429] = 1'h0;
+ \8812 [1430] = 1'h0;
+ \8812 [1431] = 1'h0;
+ \8812 [1432] = 1'h0;
+ \8812 [1433] = 1'h0;
+ \8812 [1434] = 1'h0;
+ \8812 [1435] = 1'h0;
+ \8812 [1436] = 1'h0;
+ \8812 [1437] = 1'h0;
+ \8812 [1438] = 1'h0;
+ \8812 [1439] = 1'h0;
+ \8812 [1440] = 1'h0;
+ \8812 [1441] = 1'h0;
+ \8812 [1442] = 1'h0;
+ \8812 [1443] = 1'h0;
+ \8812 [1444] = 1'h0;
+ \8812 [1445] = 1'h0;
+ \8812 [1446] = 1'h0;
+ \8812 [1447] = 1'h0;
+ \8812 [1448] = 1'h0;
+ \8812 [1449] = 1'h0;
+ \8812 [1450] = 1'h0;
+ \8812 [1451] = 1'h0;
+ \8812 [1452] = 1'h0;
+ \8812 [1453] = 1'h0;
+ \8812 [1454] = 1'h0;
+ \8812 [1455] = 1'h0;
+ \8812 [1456] = 1'h0;
+ \8812 [1457] = 1'h0;
+ \8812 [1458] = 1'h0;
+ \8812 [1459] = 1'h0;
+ \8812 [1460] = 1'h0;
+ \8812 [1461] = 1'h0;
+ \8812 [1462] = 1'h0;
+ \8812 [1463] = 1'h0;
+ \8812 [1464] = 1'h0;
+ \8812 [1465] = 1'h0;
+ \8812 [1466] = 1'h0;
+ \8812 [1467] = 1'h0;
+ \8812 [1468] = 1'h0;
+ \8812 [1469] = 1'h0;
+ \8812 [1470] = 1'h0;
+ \8812 [1471] = 1'h0;
+ \8812 [1472] = 1'h0;
+ \8812 [1473] = 1'h0;
+ \8812 [1474] = 1'h0;
+ \8812 [1475] = 1'h0;
+ \8812 [1476] = 1'h0;
+ \8812 [1477] = 1'h0;
+ \8812 [1478] = 1'h0;
+ \8812 [1479] = 1'h0;
+ \8812 [1480] = 1'h0;
+ \8812 [1481] = 1'h0;
+ \8812 [1482] = 1'h0;
+ \8812 [1483] = 1'h0;
+ \8812 [1484] = 1'h0;
+ \8812 [1485] = 1'h0;
+ \8812 [1486] = 1'h0;
+ \8812 [1487] = 1'h0;
+ \8812 [1488] = 1'h0;
+ \8812 [1489] = 1'h0;
+ \8812 [1490] = 1'h0;
+ \8812 [1491] = 1'h0;
+ \8812 [1492] = 1'h0;
+ \8812 [1493] = 1'h0;
+ \8812 [1494] = 1'h0;
+ \8812 [1495] = 1'h0;
+ \8812 [1496] = 1'h0;
+ \8812 [1497] = 1'h0;
+ \8812 [1498] = 1'h0;
+ \8812 [1499] = 1'h0;
+ \8812 [1500] = 1'h0;
+ \8812 [1501] = 1'h0;
+ \8812 [1502] = 1'h0;
+ \8812 [1503] = 1'h0;
+ \8812 [1504] = 1'h0;
+ \8812 [1505] = 1'h0;
+ \8812 [1506] = 1'h0;
+ \8812 [1507] = 1'h0;
+ \8812 [1508] = 1'h0;
+ \8812 [1509] = 1'h0;
+ \8812 [1510] = 1'h0;
+ \8812 [1511] = 1'h0;
+ \8812 [1512] = 1'h0;
+ \8812 [1513] = 1'h0;
+ \8812 [1514] = 1'h0;
+ \8812 [1515] = 1'h0;
+ \8812 [1516] = 1'h0;
+ \8812 [1517] = 1'h0;
+ \8812 [1518] = 1'h0;
+ \8812 [1519] = 1'h0;
+ \8812 [1520] = 1'h0;
+ \8812 [1521] = 1'h0;
+ \8812 [1522] = 1'h0;
+ \8812 [1523] = 1'h0;
+ \8812 [1524] = 1'h0;
+ \8812 [1525] = 1'h0;
+ \8812 [1526] = 1'h0;
+ \8812 [1527] = 1'h0;
+ \8812 [1528] = 1'h0;
+ \8812 [1529] = 1'h0;
+ \8812 [1530] = 1'h0;
+ \8812 [1531] = 1'h0;
+ \8812 [1532] = 1'h0;
+ \8812 [1533] = 1'h0;
+ \8812 [1534] = 1'h0;
+ \8812 [1535] = 1'h0;
+ \8812 [1536] = 1'h0;
+ \8812 [1537] = 1'h0;
+ \8812 [1538] = 1'h0;
+ \8812 [1539] = 1'h0;
+ \8812 [1540] = 1'h0;
+ \8812 [1541] = 1'h0;
+ \8812 [1542] = 1'h0;
+ \8812 [1543] = 1'h0;
+ \8812 [1544] = 1'h0;
+ \8812 [1545] = 1'h0;
+ \8812 [1546] = 1'h0;
+ \8812 [1547] = 1'h0;
+ \8812 [1548] = 1'h0;
+ \8812 [1549] = 1'h0;
+ \8812 [1550] = 1'h0;
+ \8812 [1551] = 1'h0;
+ \8812 [1552] = 1'h0;
+ \8812 [1553] = 1'h0;
+ \8812 [1554] = 1'h0;
+ \8812 [1555] = 1'h0;
+ \8812 [1556] = 1'h0;
+ \8812 [1557] = 1'h0;
+ \8812 [1558] = 1'h0;
+ \8812 [1559] = 1'h0;
+ \8812 [1560] = 1'h0;
+ \8812 [1561] = 1'h0;
+ \8812 [1562] = 1'h0;
+ \8812 [1563] = 1'h0;
+ \8812 [1564] = 1'h0;
+ \8812 [1565] = 1'h0;
+ \8812 [1566] = 1'h0;
+ \8812 [1567] = 1'h0;
+ \8812 [1568] = 1'h0;
+ \8812 [1569] = 1'h0;
+ \8812 [1570] = 1'h0;
+ \8812 [1571] = 1'h0;
+ \8812 [1572] = 1'h0;
+ \8812 [1573] = 1'h0;
+ \8812 [1574] = 1'h0;
+ \8812 [1575] = 1'h0;
+ \8812 [1576] = 1'h0;
+ \8812 [1577] = 1'h0;
+ \8812 [1578] = 1'h0;
+ \8812 [1579] = 1'h0;
+ \8812 [1580] = 1'h0;
+ \8812 [1581] = 1'h0;
+ \8812 [1582] = 1'h0;
+ \8812 [1583] = 1'h0;
+ \8812 [1584] = 1'h0;
+ \8812 [1585] = 1'h0;
+ \8812 [1586] = 1'h0;
+ \8812 [1587] = 1'h0;
+ \8812 [1588] = 1'h0;
+ \8812 [1589] = 1'h0;
+ \8812 [1590] = 1'h0;
+ \8812 [1591] = 1'h0;
+ \8812 [1592] = 1'h0;
+ \8812 [1593] = 1'h0;
+ \8812 [1594] = 1'h0;
+ \8812 [1595] = 1'h0;
+ \8812 [1596] = 1'h0;
+ \8812 [1597] = 1'h0;
+ \8812 [1598] = 1'h0;
+ \8812 [1599] = 1'h0;
+ \8812 [1600] = 1'h0;
+ \8812 [1601] = 1'h0;
+ \8812 [1602] = 1'h0;
+ \8812 [1603] = 1'h0;
+ \8812 [1604] = 1'h0;
+ \8812 [1605] = 1'h0;
+ \8812 [1606] = 1'h0;
+ \8812 [1607] = 1'h0;
+ \8812 [1608] = 1'h0;
+ \8812 [1609] = 1'h0;
+ \8812 [1610] = 1'h0;
+ \8812 [1611] = 1'h0;
+ \8812 [1612] = 1'h0;
+ \8812 [1613] = 1'h0;
+ \8812 [1614] = 1'h0;
+ \8812 [1615] = 1'h0;
+ \8812 [1616] = 1'h0;
+ \8812 [1617] = 1'h0;
+ \8812 [1618] = 1'h0;
+ \8812 [1619] = 1'h0;
+ \8812 [1620] = 1'h0;
+ \8812 [1621] = 1'h0;
+ \8812 [1622] = 1'h0;
+ \8812 [1623] = 1'h0;
+ \8812 [1624] = 1'h0;
+ \8812 [1625] = 1'h0;
+ \8812 [1626] = 1'h0;
+ \8812 [1627] = 1'h0;
+ \8812 [1628] = 1'h0;
+ \8812 [1629] = 1'h0;
+ \8812 [1630] = 1'h0;
+ \8812 [1631] = 1'h0;
+ \8812 [1632] = 1'h0;
+ \8812 [1633] = 1'h0;
+ \8812 [1634] = 1'h0;
+ \8812 [1635] = 1'h0;
+ \8812 [1636] = 1'h0;
+ \8812 [1637] = 1'h0;
+ \8812 [1638] = 1'h0;
+ \8812 [1639] = 1'h0;
+ \8812 [1640] = 1'h0;
+ \8812 [1641] = 1'h0;
+ \8812 [1642] = 1'h0;
+ \8812 [1643] = 1'h0;
+ \8812 [1644] = 1'h0;
+ \8812 [1645] = 1'h0;
+ \8812 [1646] = 1'h0;
+ \8812 [1647] = 1'h0;
+ \8812 [1648] = 1'h0;
+ \8812 [1649] = 1'h0;
+ \8812 [1650] = 1'h0;
+ \8812 [1651] = 1'h0;
+ \8812 [1652] = 1'h0;
+ \8812 [1653] = 1'h0;
+ \8812 [1654] = 1'h0;
+ \8812 [1655] = 1'h0;
+ \8812 [1656] = 1'h0;
+ \8812 [1657] = 1'h0;
+ \8812 [1658] = 1'h0;
+ \8812 [1659] = 1'h0;
+ \8812 [1660] = 1'h0;
+ \8812 [1661] = 1'h0;
+ \8812 [1662] = 1'h0;
+ \8812 [1663] = 1'h0;
+ \8812 [1664] = 1'h0;
+ \8812 [1665] = 1'h0;
+ \8812 [1666] = 1'h0;
+ \8812 [1667] = 1'h0;
+ \8812 [1668] = 1'h0;
+ \8812 [1669] = 1'h0;
+ \8812 [1670] = 1'h0;
+ \8812 [1671] = 1'h0;
+ \8812 [1672] = 1'h0;
+ \8812 [1673] = 1'h0;
+ \8812 [1674] = 1'h0;
+ \8812 [1675] = 1'h0;
+ \8812 [1676] = 1'h0;
+ \8812 [1677] = 1'h0;
+ \8812 [1678] = 1'h0;
+ \8812 [1679] = 1'h0;
+ \8812 [1680] = 1'h0;
+ \8812 [1681] = 1'h0;
+ \8812 [1682] = 1'h0;
+ \8812 [1683] = 1'h0;
+ \8812 [1684] = 1'h0;
+ \8812 [1685] = 1'h0;
+ \8812 [1686] = 1'h0;
+ \8812 [1687] = 1'h0;
+ \8812 [1688] = 1'h0;
+ \8812 [1689] = 1'h0;
+ \8812 [1690] = 1'h0;
+ \8812 [1691] = 1'h0;
+ \8812 [1692] = 1'h0;
+ \8812 [1693] = 1'h0;
+ \8812 [1694] = 1'h0;
+ \8812 [1695] = 1'h0;
+ \8812 [1696] = 1'h0;
+ \8812 [1697] = 1'h0;
+ \8812 [1698] = 1'h0;
+ \8812 [1699] = 1'h0;
+ \8812 [1700] = 1'h0;
+ \8812 [1701] = 1'h0;
+ \8812 [1702] = 1'h0;
+ \8812 [1703] = 1'h0;
+ \8812 [1704] = 1'h0;
+ \8812 [1705] = 1'h0;
+ \8812 [1706] = 1'h0;
+ \8812 [1707] = 1'h0;
+ \8812 [1708] = 1'h0;
+ \8812 [1709] = 1'h0;
+ \8812 [1710] = 1'h0;
+ \8812 [1711] = 1'h0;
+ \8812 [1712] = 1'h0;
+ \8812 [1713] = 1'h0;
+ \8812 [1714] = 1'h0;
+ \8812 [1715] = 1'h0;
+ \8812 [1716] = 1'h0;
+ \8812 [1717] = 1'h0;
+ \8812 [1718] = 1'h0;
+ \8812 [1719] = 1'h0;
+ \8812 [1720] = 1'h0;
+ \8812 [1721] = 1'h0;
+ \8812 [1722] = 1'h0;
+ \8812 [1723] = 1'h0;
+ \8812 [1724] = 1'h0;
+ \8812 [1725] = 1'h0;
+ \8812 [1726] = 1'h0;
+ \8812 [1727] = 1'h0;
+ \8812 [1728] = 1'h0;
+ \8812 [1729] = 1'h0;
+ \8812 [1730] = 1'h0;
+ \8812 [1731] = 1'h0;
+ \8812 [1732] = 1'h0;
+ \8812 [1733] = 1'h0;
+ \8812 [1734] = 1'h0;
+ \8812 [1735] = 1'h0;
+ \8812 [1736] = 1'h0;
+ \8812 [1737] = 1'h0;
+ \8812 [1738] = 1'h0;
+ \8812 [1739] = 1'h0;
+ \8812 [1740] = 1'h0;
+ \8812 [1741] = 1'h0;
+ \8812 [1742] = 1'h0;
+ \8812 [1743] = 1'h0;
+ \8812 [1744] = 1'h0;
+ \8812 [1745] = 1'h0;
+ \8812 [1746] = 1'h0;
+ \8812 [1747] = 1'h0;
+ \8812 [1748] = 1'h0;
+ \8812 [1749] = 1'h0;
+ \8812 [1750] = 1'h0;
+ \8812 [1751] = 1'h0;
+ \8812 [1752] = 1'h0;
+ \8812 [1753] = 1'h0;
+ \8812 [1754] = 1'h0;
+ \8812 [1755] = 1'h0;
+ \8812 [1756] = 1'h0;
+ \8812 [1757] = 1'h0;
+ \8812 [1758] = 1'h0;
+ \8812 [1759] = 1'h0;
+ \8812 [1760] = 1'h0;
+ \8812 [1761] = 1'h0;
+ \8812 [1762] = 1'h0;
+ \8812 [1763] = 1'h0;
+ \8812 [1764] = 1'h0;
+ \8812 [1765] = 1'h0;
+ \8812 [1766] = 1'h0;
+ \8812 [1767] = 1'h0;
+ \8812 [1768] = 1'h0;
+ \8812 [1769] = 1'h0;
+ \8812 [1770] = 1'h0;
+ \8812 [1771] = 1'h0;
+ \8812 [1772] = 1'h0;
+ \8812 [1773] = 1'h0;
+ \8812 [1774] = 1'h0;
+ \8812 [1775] = 1'h0;
+ \8812 [1776] = 1'h0;
+ \8812 [1777] = 1'h0;
+ \8812 [1778] = 1'h0;
+ \8812 [1779] = 1'h0;
+ \8812 [1780] = 1'h0;
+ \8812 [1781] = 1'h0;
+ \8812 [1782] = 1'h0;
+ \8812 [1783] = 1'h0;
+ \8812 [1784] = 1'h0;
+ \8812 [1785] = 1'h0;
+ \8812 [1786] = 1'h0;
+ \8812 [1787] = 1'h0;
+ \8812 [1788] = 1'h0;
+ \8812 [1789] = 1'h0;
+ \8812 [1790] = 1'h0;
+ \8812 [1791] = 1'h0;
+ \8812 [1792] = 1'h0;
+ \8812 [1793] = 1'h0;
+ \8812 [1794] = 1'h0;
+ \8812 [1795] = 1'h0;
+ \8812 [1796] = 1'h0;
+ \8812 [1797] = 1'h0;
+ \8812 [1798] = 1'h0;
+ \8812 [1799] = 1'h0;
+ \8812 [1800] = 1'h0;
+ \8812 [1801] = 1'h0;
+ \8812 [1802] = 1'h0;
+ \8812 [1803] = 1'h0;
+ \8812 [1804] = 1'h0;
+ \8812 [1805] = 1'h0;
+ \8812 [1806] = 1'h0;
+ \8812 [1807] = 1'h0;
+ \8812 [1808] = 1'h0;
+ \8812 [1809] = 1'h0;
+ \8812 [1810] = 1'h0;
+ \8812 [1811] = 1'h0;
+ \8812 [1812] = 1'h0;
+ \8812 [1813] = 1'h0;
+ \8812 [1814] = 1'h0;
+ \8812 [1815] = 1'h0;
+ \8812 [1816] = 1'h0;
+ \8812 [1817] = 1'h0;
+ \8812 [1818] = 1'h0;
+ \8812 [1819] = 1'h0;
+ \8812 [1820] = 1'h0;
+ \8812 [1821] = 1'h0;
+ \8812 [1822] = 1'h0;
+ \8812 [1823] = 1'h0;
+ \8812 [1824] = 1'h0;
+ \8812 [1825] = 1'h0;
+ \8812 [1826] = 1'h0;
+ \8812 [1827] = 1'h0;
+ \8812 [1828] = 1'h0;
+ \8812 [1829] = 1'h0;
+ \8812 [1830] = 1'h0;
+ \8812 [1831] = 1'h0;
+ \8812 [1832] = 1'h0;
+ \8812 [1833] = 1'h0;
+ \8812 [1834] = 1'h0;
+ \8812 [1835] = 1'h0;
+ \8812 [1836] = 1'h0;
+ \8812 [1837] = 1'h0;
+ \8812 [1838] = 1'h0;
+ \8812 [1839] = 1'h0;
+ \8812 [1840] = 1'h0;
+ \8812 [1841] = 1'h0;
+ \8812 [1842] = 1'h0;
+ \8812 [1843] = 1'h0;
+ \8812 [1844] = 1'h0;
+ \8812 [1845] = 1'h0;
+ \8812 [1846] = 1'h0;
+ \8812 [1847] = 1'h0;
+ \8812 [1848] = 1'h0;
+ \8812 [1849] = 1'h0;
+ \8812 [1850] = 1'h0;
+ \8812 [1851] = 1'h0;
+ \8812 [1852] = 1'h0;
+ \8812 [1853] = 1'h0;
+ \8812 [1854] = 1'h0;
+ \8812 [1855] = 1'h0;
+ \8812 [1856] = 1'h0;
+ \8812 [1857] = 1'h0;
+ \8812 [1858] = 1'h0;
+ \8812 [1859] = 1'h0;
+ \8812 [1860] = 1'h0;
+ \8812 [1861] = 1'h0;
+ \8812 [1862] = 1'h0;
+ \8812 [1863] = 1'h0;
+ \8812 [1864] = 1'h0;
+ \8812 [1865] = 1'h0;
+ \8812 [1866] = 1'h0;
+ \8812 [1867] = 1'h0;
+ \8812 [1868] = 1'h0;
+ \8812 [1869] = 1'h0;
+ \8812 [1870] = 1'h0;
+ \8812 [1871] = 1'h0;
+ \8812 [1872] = 1'h0;
+ \8812 [1873] = 1'h0;
+ \8812 [1874] = 1'h0;
+ \8812 [1875] = 1'h0;
+ \8812 [1876] = 1'h0;
+ \8812 [1877] = 1'h0;
+ \8812 [1878] = 1'h0;
+ \8812 [1879] = 1'h0;
+ \8812 [1880] = 1'h0;
+ \8812 [1881] = 1'h0;
+ \8812 [1882] = 1'h0;
+ \8812 [1883] = 1'h0;
+ \8812 [1884] = 1'h0;
+ \8812 [1885] = 1'h0;
+ \8812 [1886] = 1'h0;
+ \8812 [1887] = 1'h0;
+ \8812 [1888] = 1'h0;
+ \8812 [1889] = 1'h0;
+ \8812 [1890] = 1'h0;
+ \8812 [1891] = 1'h0;
+ \8812 [1892] = 1'h0;
+ \8812 [1893] = 1'h0;
+ \8812 [1894] = 1'h0;
+ \8812 [1895] = 1'h0;
+ \8812 [1896] = 1'h0;
+ \8812 [1897] = 1'h0;
+ \8812 [1898] = 1'h0;
+ \8812 [1899] = 1'h0;
+ \8812 [1900] = 1'h0;
+ \8812 [1901] = 1'h0;
+ \8812 [1902] = 1'h0;
+ \8812 [1903] = 1'h0;
+ \8812 [1904] = 1'h0;
+ \8812 [1905] = 1'h0;
+ \8812 [1906] = 1'h0;
+ \8812 [1907] = 1'h0;
+ \8812 [1908] = 1'h0;
+ \8812 [1909] = 1'h0;
+ \8812 [1910] = 1'h0;
+ \8812 [1911] = 1'h0;
+ \8812 [1912] = 1'h0;
+ \8812 [1913] = 1'h0;
+ \8812 [1914] = 1'h0;
+ \8812 [1915] = 1'h0;
+ \8812 [1916] = 1'h0;
+ \8812 [1917] = 1'h0;
+ \8812 [1918] = 1'h0;
+ \8812 [1919] = 1'h0;
+ \8812 [1920] = 1'h0;
+ \8812 [1921] = 1'h0;
+ \8812 [1922] = 1'h0;
+ \8812 [1923] = 1'h0;
+ \8812 [1924] = 1'h0;
+ \8812 [1925] = 1'h0;
+ \8812 [1926] = 1'h0;
+ \8812 [1927] = 1'h0;
+ \8812 [1928] = 1'h0;
+ \8812 [1929] = 1'h0;
+ \8812 [1930] = 1'h0;
+ \8812 [1931] = 1'h0;
+ \8812 [1932] = 1'h0;
+ \8812 [1933] = 1'h0;
+ \8812 [1934] = 1'h0;
+ \8812 [1935] = 1'h0;
+ \8812 [1936] = 1'h0;
+ \8812 [1937] = 1'h0;
+ \8812 [1938] = 1'h0;
+ \8812 [1939] = 1'h0;
+ \8812 [1940] = 1'h0;
+ \8812 [1941] = 1'h0;
+ \8812 [1942] = 1'h0;
+ \8812 [1943] = 1'h0;
+ \8812 [1944] = 1'h0;
+ \8812 [1945] = 1'h0;
+ \8812 [1946] = 1'h0;
+ \8812 [1947] = 1'h0;
+ \8812 [1948] = 1'h0;
+ \8812 [1949] = 1'h0;
+ \8812 [1950] = 1'h0;
+ \8812 [1951] = 1'h0;
+ \8812 [1952] = 1'h0;
+ \8812 [1953] = 1'h0;
+ \8812 [1954] = 1'h0;
+ \8812 [1955] = 1'h0;
+ \8812 [1956] = 1'h0;
+ \8812 [1957] = 1'h0;
+ \8812 [1958] = 1'h0;
+ \8812 [1959] = 1'h0;
+ \8812 [1960] = 1'h0;
+ \8812 [1961] = 1'h0;
+ \8812 [1962] = 1'h0;
+ \8812 [1963] = 1'h0;
+ \8812 [1964] = 1'h0;
+ \8812 [1965] = 1'h0;
+ \8812 [1966] = 1'h0;
+ \8812 [1967] = 1'h0;
+ \8812 [1968] = 1'h0;
+ \8812 [1969] = 1'h0;
+ \8812 [1970] = 1'h0;
+ \8812 [1971] = 1'h0;
+ \8812 [1972] = 1'h0;
+ \8812 [1973] = 1'h0;
+ \8812 [1974] = 1'h0;
+ \8812 [1975] = 1'h0;
+ \8812 [1976] = 1'h0;
+ \8812 [1977] = 1'h0;
+ \8812 [1978] = 1'h0;
+ \8812 [1979] = 1'h0;
+ \8812 [1980] = 1'h0;
+ \8812 [1981] = 1'h0;
+ \8812 [1982] = 1'h0;
+ \8812 [1983] = 1'h0;
+ \8812 [1984] = 1'h0;
+ \8812 [1985] = 1'h0;
+ \8812 [1986] = 1'h0;
+ \8812 [1987] = 1'h0;
+ \8812 [1988] = 1'h0;
+ \8812 [1989] = 1'h0;
+ \8812 [1990] = 1'h0;
+ \8812 [1991] = 1'h0;
+ \8812 [1992] = 1'h0;
+ \8812 [1993] = 1'h0;
+ \8812 [1994] = 1'h0;
+ \8812 [1995] = 1'h0;
+ \8812 [1996] = 1'h0;
+ \8812 [1997] = 1'h0;
+ \8812 [1998] = 1'h0;
+ \8812 [1999] = 1'h0;
+ \8812 [2000] = 1'h0;
+ \8812 [2001] = 1'h0;
+ \8812 [2002] = 1'h0;
+ \8812 [2003] = 1'h0;
+ \8812 [2004] = 1'h0;
+ \8812 [2005] = 1'h0;
+ \8812 [2006] = 1'h0;
+ \8812 [2007] = 1'h0;
+ \8812 [2008] = 1'h0;
+ \8812 [2009] = 1'h0;
+ \8812 [2010] = 1'h0;
+ \8812 [2011] = 1'h0;
+ \8812 [2012] = 1'h0;
+ \8812 [2013] = 1'h0;
+ \8812 [2014] = 1'h0;
+ \8812 [2015] = 1'h0;
+ \8812 [2016] = 1'h0;
+ \8812 [2017] = 1'h0;
+ \8812 [2018] = 1'h0;
+ \8812 [2019] = 1'h0;
+ \8812 [2020] = 1'h0;
+ \8812 [2021] = 1'h0;
+ \8812 [2022] = 1'h0;
+ \8812 [2023] = 1'h0;
+ \8812 [2024] = 1'h0;
+ \8812 [2025] = 1'h0;
+ \8812 [2026] = 1'h0;
+ \8812 [2027] = 1'h0;
+ \8812 [2028] = 1'h0;
+ \8812 [2029] = 1'h0;
+ \8812 [2030] = 1'h0;
+ \8812 [2031] = 1'h0;
+ \8812 [2032] = 1'h0;
+ \8812 [2033] = 1'h0;
+ \8812 [2034] = 1'h0;
+ \8812 [2035] = 1'h0;
+ \8812 [2036] = 1'h0;
+ \8812 [2037] = 1'h0;
+ \8812 [2038] = 1'h0;
+ \8812 [2039] = 1'h0;
+ \8812 [2040] = 1'h0;
+ \8812 [2041] = 1'h0;
+ \8812 [2042] = 1'h0;
+ \8812 [2043] = 1'h0;
+ \8812 [2044] = 1'h0;
+ \8812 [2045] = 1'h0;
+ \8812 [2046] = 1'h0;
+ \8812 [2047] = 1'h0;
+ end
+ assign _127_ = \8812 [_027_];
+ reg [40:0] \8814 [63:0];
+ initial begin
+ \8814 [0] = 41'h00000000000;
+ \8814 [1] = 41'h00000000000;
+ \8814 [2] = 41'h00000000000;
+ \8814 [3] = 41'h00000000000;
+ \8814 [4] = 41'h00000000000;
+ \8814 [5] = 41'h00000000000;
+ \8814 [6] = 41'h00000000000;
+ \8814 [7] = 41'h00000000000;
+ \8814 [8] = 41'h00000000000;
+ \8814 [9] = 41'h00000000000;
+ \8814 [10] = 41'h00000000000;
+ \8814 [11] = 41'h00000000000;
+ \8814 [12] = 41'h050000509ad;
+ \8814 [13] = 41'h00000000000;
+ \8814 [14] = 41'h040000509b1;
+ \8814 [15] = 41'h050000509b1;
+ \8814 [16] = 41'h00000000000;
+ \8814 [17] = 41'h00000000000;
+ \8814 [18] = 41'h00000000000;
+ \8814 [19] = 41'h00000000000;
+ \8814 [20] = 41'h00000000000;
+ \8814 [21] = 41'h00000000000;
+ \8814 [22] = 41'h00000000000;
+ \8814 [23] = 41'h00000000000;
+ \8814 [24] = 41'h00000000000;
+ \8814 [25] = 41'h00000000000;
+ \8814 [26] = 41'h00000000000;
+ \8814 [27] = 41'h00000000000;
+ \8814 [28] = 41'h00000000000;
+ \8814 [29] = 41'h00000000000;
+ \8814 [30] = 41'h00000000000;
+ \8814 [31] = 41'h00000000000;
+ \8814 [32] = 41'h00000000000;
+ \8814 [33] = 41'h00000000000;
+ \8814 [34] = 41'h00000000000;
+ \8814 [35] = 41'h00000000000;
+ \8814 [36] = 41'h00000000000;
+ \8814 [37] = 41'h00000000000;
+ \8814 [38] = 41'h00000000000;
+ \8814 [39] = 41'h00000000000;
+ \8814 [40] = 41'h00000000000;
+ \8814 [41] = 41'h00000000000;
+ \8814 [42] = 41'h00000000000;
+ \8814 [43] = 41'h00000000000;
+ \8814 [44] = 41'h00000000000;
+ \8814 [45] = 41'h00000000000;
+ \8814 [46] = 41'h00000000000;
+ \8814 [47] = 41'h00000000000;
+ \8814 [48] = 41'h00000000000;
+ \8814 [49] = 41'h00000000000;
+ \8814 [50] = 41'h00000000000;
+ \8814 [51] = 41'h00000000000;
+ \8814 [52] = 41'h00000000000;
+ \8814 [53] = 41'h00000000000;
+ \8814 [54] = 41'h00000000000;
+ \8814 [55] = 41'h00000000000;
+ \8814 [56] = 41'h00000000000;
+ \8814 [57] = 41'h00000000000;
+ \8814 [58] = 41'h00000000000;
+ \8814 [59] = 41'h00000000000;
+ \8814 [60] = 41'h00000000000;
+ \8814 [61] = 41'h00000000000;
+ \8814 [62] = 41'h00000000000;
+ \8814 [63] = 41'h00000000000;
+ end
+ assign _129_ = \8814 [_029_];
+ reg [40:0] \8816 [1023:0];
+ initial begin
+ \8816 [0] = 41'h00000000000;
+ \8816 [1] = 41'h00000000000;
+ \8816 [2] = 41'h00000000000;
+ \8816 [3] = 41'h00000000000;
+ \8816 [4] = 41'h00000000000;
+ \8816 [5] = 41'h00000000000;
+ \8816 [6] = 41'h00000000000;
+ \8816 [7] = 41'h00000000000;
+ \8816 [8] = 41'h00000000000;
+ \8816 [9] = 41'h00000000a52;
+ \8816 [10] = 41'h00040008a82;
+ \8816 [11] = 41'h00000000000;
+ \8816 [12] = 41'h00000000000;
+ \8816 [13] = 41'h00000000000;
+ \8816 [14] = 41'h00000000000;
+ \8816 [15] = 41'h00000000000;
+ \8816 [16] = 41'h00000240a75;
+ \8816 [17] = 41'h00000000000;
+ \8816 [18] = 41'h00000000000;
+ \8816 [19] = 41'h00000000000;
+ \8816 [20] = 41'h05800040955;
+ \8816 [21] = 41'h00000000000;
+ \8816 [22] = 41'h05000040955;
+ \8816 [23] = 41'h00000000000;
+ \8816 [24] = 41'h00000000000;
+ \8816 [25] = 41'h00000000000;
+ \8816 [26] = 41'h00000000000;
+ \8816 [27] = 41'h00000000000;
+ \8816 [28] = 41'h00000000000;
+ \8816 [29] = 41'h00000000000;
+ \8816 [30] = 41'h00000000000;
+ \8816 [31] = 41'h00000000000;
+ \8816 [32] = 41'h00000000000;
+ \8816 [33] = 41'h00000000000;
+ \8816 [34] = 41'h00000000000;
+ \8816 [35] = 41'h00000000000;
+ \8816 [36] = 41'h00000000000;
+ \8816 [37] = 41'h0403008805d;
+ \8816 [38] = 41'h00000000000;
+ \8816 [39] = 41'h00000000000;
+ \8816 [40] = 41'h00030020a8a;
+ \8816 [41] = 41'h1000000006d;
+ \8816 [42] = 41'h00010008a82;
+ \8816 [43] = 41'h00000000000;
+ \8816 [44] = 41'h00000000000;
+ \8816 [45] = 41'h00000000000;
+ \8816 [46] = 41'h00000000000;
+ \8816 [47] = 41'h00000000000;
+ \8816 [48] = 41'h00000240a75;
+ \8816 [49] = 41'h00000000000;
+ \8816 [50] = 41'h00000000000;
+ \8816 [51] = 41'h00000000000;
+ \8816 [52] = 41'h04800040955;
+ \8816 [53] = 41'h00000000000;
+ \8816 [54] = 41'h04000040955;
+ \8816 [55] = 41'h00000000000;
+ \8816 [56] = 41'h00000000000;
+ \8816 [57] = 41'h00000000000;
+ \8816 [58] = 41'h00000000000;
+ \8816 [59] = 41'h00000000000;
+ \8816 [60] = 41'h00000000000;
+ \8816 [61] = 41'h00000000000;
+ \8816 [62] = 41'h00000000000;
+ \8816 [63] = 41'h00000000000;
+ \8816 [64] = 41'h00000000000;
+ \8816 [65] = 41'h00000000000;
+ \8816 [66] = 41'h00000000000;
+ \8816 [67] = 41'h00000000000;
+ \8816 [68] = 41'h00000000000;
+ \8816 [69] = 41'h0401008805d;
+ \8816 [70] = 41'h00000000000;
+ \8816 [71] = 41'h00000000000;
+ \8816 [72] = 41'h00000000000;
+ \8816 [73] = 41'h00000000000;
+ \8816 [74] = 41'h00020008a82;
+ \8816 [75] = 41'h00000000000;
+ \8816 [76] = 41'h00000000000;
+ \8816 [77] = 41'h00000000000;
+ \8816 [78] = 41'h00000000000;
+ \8816 [79] = 41'h00000000000;
+ \8816 [80] = 41'h00000240a75;
+ \8816 [81] = 41'h00000000000;
+ \8816 [82] = 41'h00000000000;
+ \8816 [83] = 41'h00000000000;
+ \8816 [84] = 41'h05800040959;
+ \8816 [85] = 41'h00000000000;
+ \8816 [86] = 41'h05000040959;
+ \8816 [87] = 41'h00000000000;
+ \8816 [88] = 41'h00000000000;
+ \8816 [89] = 41'h00000000000;
+ \8816 [90] = 41'h00000000000;
+ \8816 [91] = 41'h00000000000;
+ \8816 [92] = 41'h00000000000;
+ \8816 [93] = 41'h00000000000;
+ \8816 [94] = 41'h00000000000;
+ \8816 [95] = 41'h00000000000;
+ \8816 [96] = 41'h00000000000;
+ \8816 [97] = 41'h00000000000;
+ \8816 [98] = 41'h00000000000;
+ \8816 [99] = 41'h00000000000;
+ \8816 [100] = 41'h00000000000;
+ \8816 [101] = 41'h0402008805d;
+ \8816 [102] = 41'h00000000000;
+ \8816 [103] = 41'h00000000000;
+ \8816 [104] = 41'h00000000000;
+ \8816 [105] = 41'h000a0008a82;
+ \8816 [106] = 41'h00030008a82;
+ \8816 [107] = 41'h00000000000;
+ \8816 [108] = 41'h00000000000;
+ \8816 [109] = 41'h00000000000;
+ \8816 [110] = 41'h00000000000;
+ \8816 [111] = 41'h00000000000;
+ \8816 [112] = 41'h00000240a75;
+ \8816 [113] = 41'h00000000000;
+ \8816 [114] = 41'h00000000000;
+ \8816 [115] = 41'h00000000000;
+ \8816 [116] = 41'h04800040959;
+ \8816 [117] = 41'h00000000000;
+ \8816 [118] = 41'h04000040959;
+ \8816 [119] = 41'h00000000000;
+ \8816 [120] = 41'h00000000000;
+ \8816 [121] = 41'h00000000000;
+ \8816 [122] = 41'h00000000000;
+ \8816 [123] = 41'h00000000000;
+ \8816 [124] = 41'h00000000000;
+ \8816 [125] = 41'h00000000000;
+ \8816 [126] = 41'h00000000000;
+ \8816 [127] = 41'h00000000000;
+ \8816 [128] = 41'h00000000000;
+ \8816 [129] = 41'h00000000000;
+ \8816 [130] = 41'h00000000000;
+ \8816 [131] = 41'h00000000000;
+ \8816 [132] = 41'h0400008d861;
+ \8816 [133] = 41'h0400008d861;
+ \8816 [134] = 41'h00000000000;
+ \8816 [135] = 41'h00000000000;
+ \8816 [136] = 41'h00030100a86;
+ \8816 [137] = 41'h00000000000;
+ \8816 [138] = 41'h00040040a7e;
+ \8816 [139] = 41'h00000000000;
+ \8816 [140] = 41'h00000000000;
+ \8816 [141] = 41'h00000000000;
+ \8816 [142] = 41'h00000000000;
+ \8816 [143] = 41'h00000000000;
+ \8816 [144] = 41'h00000240a75;
+ \8816 [145] = 41'h00000000000;
+ \8816 [146] = 41'h00000000000;
+ \8816 [147] = 41'h00000000000;
+ \8816 [148] = 41'h00000000000;
+ \8816 [149] = 41'h00000000000;
+ \8816 [150] = 41'h00000000000;
+ \8816 [151] = 41'h00000000000;
+ \8816 [152] = 41'h00000000000;
+ \8816 [153] = 41'h00000000000;
+ \8816 [154] = 41'h00000000000;
+ \8816 [155] = 41'h00000000000;
+ \8816 [156] = 41'h00000000000;
+ \8816 [157] = 41'h00000000000;
+ \8816 [158] = 41'h00000000000;
+ \8816 [159] = 41'h00000000000;
+ \8816 [160] = 41'h00000000000;
+ \8816 [161] = 41'h00000000000;
+ \8816 [162] = 41'h00000000000;
+ \8816 [163] = 41'h00000000000;
+ \8816 [164] = 41'h00000000000;
+ \8816 [165] = 41'h00000000000;
+ \8816 [166] = 41'h00000000000;
+ \8816 [167] = 41'h00000000000;
+ \8816 [168] = 41'h00130100a86;
+ \8816 [169] = 41'h10000000005;
+ \8816 [170] = 41'h00010040a7e;
+ \8816 [171] = 41'h00000000000;
+ \8816 [172] = 41'h00000000000;
+ \8816 [173] = 41'h00000000000;
+ \8816 [174] = 41'h00000000000;
+ \8816 [175] = 41'h00000000000;
+ \8816 [176] = 41'h00000240a75;
+ \8816 [177] = 41'h00000000000;
+ \8816 [178] = 41'h00000000000;
+ \8816 [179] = 41'h00000000000;
+ \8816 [180] = 41'h00000000000;
+ \8816 [181] = 41'h00000000000;
+ \8816 [182] = 41'h00000000000;
+ \8816 [183] = 41'h00000000000;
+ \8816 [184] = 41'h00000000000;
+ \8816 [185] = 41'h00000000000;
+ \8816 [186] = 41'h00000000000;
+ \8816 [187] = 41'h00000000000;
+ \8816 [188] = 41'h00000000000;
+ \8816 [189] = 41'h00000000000;
+ \8816 [190] = 41'h00000000000;
+ \8816 [191] = 41'h00000000000;
+ \8816 [192] = 41'h00000000000;
+ \8816 [193] = 41'h00000000000;
+ \8816 [194] = 41'h00000000000;
+ \8816 [195] = 41'h00000000000;
+ \8816 [196] = 41'h0500808d8e1;
+ \8816 [197] = 41'h0500808d8e1;
+ \8816 [198] = 41'h00000000000;
+ \8816 [199] = 41'h0580808e0e1;
+ \8816 [200] = 41'h00000000000;
+ \8816 [201] = 41'h00000000000;
+ \8816 [202] = 41'h00020040a7e;
+ \8816 [203] = 41'h00000000000;
+ \8816 [204] = 41'h00000000000;
+ \8816 [205] = 41'h00000000000;
+ \8816 [206] = 41'h00000000000;
+ \8816 [207] = 41'h00000000000;
+ \8816 [208] = 41'h00000240a75;
+ \8816 [209] = 41'h00000000000;
+ \8816 [210] = 41'h00000000000;
+ \8816 [211] = 41'h00000000000;
+ \8816 [212] = 41'h00000000000;
+ \8816 [213] = 41'h00000000000;
+ \8816 [214] = 41'h00000000000;
+ \8816 [215] = 41'h00000000000;
+ \8816 [216] = 41'h00000000000;
+ \8816 [217] = 41'h00000000000;
+ \8816 [218] = 41'h00000000000;
+ \8816 [219] = 41'h00000000000;
+ \8816 [220] = 41'h00000000000;
+ \8816 [221] = 41'h00000000000;
+ \8816 [222] = 41'h00000000000;
+ \8816 [223] = 41'h00000000000;
+ \8816 [224] = 41'h00000000000;
+ \8816 [225] = 41'h00000000000;
+ \8816 [226] = 41'h00000000000;
+ \8816 [227] = 41'h00000000000;
+ \8816 [228] = 41'h00000000000;
+ \8816 [229] = 41'h050080888e1;
+ \8816 [230] = 41'h00000000000;
+ \8816 [231] = 41'h058080888e1;
+ \8816 [232] = 41'h00000000000;
+ \8816 [233] = 41'h000a0040a7e;
+ \8816 [234] = 41'h00030040a7e;
+ \8816 [235] = 41'h00000000000;
+ \8816 [236] = 41'h00000000000;
+ \8816 [237] = 41'h00000000000;
+ \8816 [238] = 41'h00000000000;
+ \8816 [239] = 41'h00000000000;
+ \8816 [240] = 41'h00000240a75;
+ \8816 [241] = 41'h00000000000;
+ \8816 [242] = 41'h00000000000;
+ \8816 [243] = 41'h00000000000;
+ \8816 [244] = 41'h0180004099d;
+ \8816 [245] = 41'h04000040909;
+ \8816 [246] = 41'h0100004099d;
+ \8816 [247] = 41'h00000000000;
+ \8816 [248] = 41'h00000000000;
+ \8816 [249] = 41'h00000000000;
+ \8816 [250] = 41'h00000000000;
+ \8816 [251] = 41'h00000000000;
+ \8816 [252] = 41'h00000000000;
+ \8816 [253] = 41'h00000000000;
+ \8816 [254] = 41'h00000000000;
+ \8816 [255] = 41'h00000000000;
+ \8816 [256] = 41'h00000000000;
+ \8816 [257] = 41'h00000000000;
+ \8816 [258] = 41'h00000000000;
+ \8816 [259] = 41'h00000000000;
+ \8816 [260] = 41'h00000000000;
+ \8816 [261] = 41'h00000000000;
+ \8816 [262] = 41'h00000000000;
+ \8816 [263] = 41'h00000000000;
+ \8816 [264] = 41'h00240020a8a;
+ \8816 [265] = 41'h00000000000;
+ \8816 [266] = 41'h00000000000;
+ \8816 [267] = 41'h00000000000;
+ \8816 [268] = 41'h0000004003d;
+ \8816 [269] = 41'h00000000005;
+ \8816 [270] = 41'h00000000000;
+ \8816 [271] = 41'h00000000000;
+ \8816 [272] = 41'h00000240a75;
+ \8816 [273] = 41'h00000000000;
+ \8816 [274] = 41'h00000000000;
+ \8816 [275] = 41'h00000000000;
+ \8816 [276] = 41'h058000409ad;
+ \8816 [277] = 41'h0400a045109;
+ \8816 [278] = 41'h050000409ad;
+ \8816 [279] = 41'h0400a845109;
+ \8816 [280] = 41'h00000000000;
+ \8816 [281] = 41'h00000000000;
+ \8816 [282] = 41'h00000000000;
+ \8816 [283] = 41'h00000000000;
+ \8816 [284] = 41'h00000000000;
+ \8816 [285] = 41'h00000000000;
+ \8816 [286] = 41'h00000000000;
+ \8816 [287] = 41'h00000000000;
+ \8816 [288] = 41'h00000000000;
+ \8816 [289] = 41'h00000000000;
+ \8816 [290] = 41'h00000000000;
+ \8816 [291] = 41'h00000000000;
+ \8816 [292] = 41'h00000000000;
+ \8816 [293] = 41'h00000000000;
+ \8816 [294] = 41'h00000000000;
+ \8816 [295] = 41'h00000000000;
+ \8816 [296] = 41'h00040020a8a;
+ \8816 [297] = 41'h02420008a82;
+ \8816 [298] = 41'h00000000000;
+ \8816 [299] = 41'h00000000000;
+ \8816 [300] = 41'h00000000000;
+ \8816 [301] = 41'h00000000005;
+ \8816 [302] = 41'h00000000000;
+ \8816 [303] = 41'h00000000000;
+ \8816 [304] = 41'h00000240a75;
+ \8816 [305] = 41'h00000000000;
+ \8816 [306] = 41'h00000000000;
+ \8816 [307] = 41'h00000000000;
+ \8816 [308] = 41'h00000000000;
+ \8816 [309] = 41'h0400a040109;
+ \8816 [310] = 41'h00000000000;
+ \8816 [311] = 41'h0400a840109;
+ \8816 [312] = 41'h00000000000;
+ \8816 [313] = 41'h00000000000;
+ \8816 [314] = 41'h00000000000;
+ \8816 [315] = 41'h00000000000;
+ \8816 [316] = 41'h00000000000;
+ \8816 [317] = 41'h00000000000;
+ \8816 [318] = 41'h00000000000;
+ \8816 [319] = 41'h00000000000;
+ \8816 [320] = 41'h00000000000;
+ \8816 [321] = 41'h00000000000;
+ \8816 [322] = 41'h00000000000;
+ \8816 [323] = 41'h00000000000;
+ \8816 [324] = 41'h00000000000;
+ \8816 [325] = 41'h00000000000;
+ \8816 [326] = 41'h00000000000;
+ \8816 [327] = 41'h00000000000;
+ \8816 [328] = 41'h00a30020a8a;
+ \8816 [329] = 41'h02410008a82;
+ \8816 [330] = 41'h00000000000;
+ \8816 [331] = 41'h00000000000;
+ \8816 [332] = 41'h00000000000;
+ \8816 [333] = 41'h00000000005;
+ \8816 [334] = 41'h00000000000;
+ \8816 [335] = 41'h00000000000;
+ \8816 [336] = 41'h00000240a75;
+ \8816 [337] = 41'h00000000000;
+ \8816 [338] = 41'h00000000000;
+ \8816 [339] = 41'h00000000000;
+ \8816 [340] = 41'h00000000000;
+ \8816 [341] = 41'h00000000000;
+ \8816 [342] = 41'h00000000000;
+ \8816 [343] = 41'h00000000000;
+ \8816 [344] = 41'h00000000000;
+ \8816 [345] = 41'h00000000000;
+ \8816 [346] = 41'h00000000000;
+ \8816 [347] = 41'h00000000000;
+ \8816 [348] = 41'h00000000000;
+ \8816 [349] = 41'h00000000000;
+ \8816 [350] = 41'h00000000000;
+ \8816 [351] = 41'h00000000000;
+ \8816 [352] = 41'h00000000000;
+ \8816 [353] = 41'h00000000000;
+ \8816 [354] = 41'h00000000000;
+ \8816 [355] = 41'h00000000000;
+ \8816 [356] = 41'h00000000000;
+ \8816 [357] = 41'h00000000000;
+ \8816 [358] = 41'h00000000000;
+ \8816 [359] = 41'h00000000000;
+ \8816 [360] = 41'h00830020a8a;
+ \8816 [361] = 41'h000b0008a82;
+ \8816 [362] = 41'h00000000000;
+ \8816 [363] = 41'h000c0008a82;
+ \8816 [364] = 41'h00000000000;
+ \8816 [365] = 41'h00000000005;
+ \8816 [366] = 41'h00000000000;
+ \8816 [367] = 41'h00000000000;
+ \8816 [368] = 41'h00000240a75;
+ \8816 [369] = 41'h00000000000;
+ \8816 [370] = 41'h00000000000;
+ \8816 [371] = 41'h00000000000;
+ \8816 [372] = 41'h00000000000;
+ \8816 [373] = 41'h0400a040909;
+ \8816 [374] = 41'h00000000000;
+ \8816 [375] = 41'h0400a840909;
+ \8816 [376] = 41'h00000000000;
+ \8816 [377] = 41'h00000000000;
+ \8816 [378] = 41'h00000000000;
+ \8816 [379] = 41'h00000000000;
+ \8816 [380] = 41'h00000000000;
+ \8816 [381] = 41'h00000000000;
+ \8816 [382] = 41'h00000000000;
+ \8816 [383] = 41'h00000000000;
+ \8816 [384] = 41'h00000000000;
+ \8816 [385] = 41'h00000000000;
+ \8816 [386] = 41'h00000000000;
+ \8816 [387] = 41'h00000000000;
+ \8816 [388] = 41'h00000000000;
+ \8816 [389] = 41'h00000000000;
+ \8816 [390] = 41'h00000000000;
+ \8816 [391] = 41'h00000000000;
+ \8816 [392] = 41'h00240100a86;
+ \8816 [393] = 41'h00000000000;
+ \8816 [394] = 41'h00000000000;
+ \8816 [395] = 41'h00000000000;
+ \8816 [396] = 41'h00000000000;
+ \8816 [397] = 41'h00000000005;
+ \8816 [398] = 41'h00000000000;
+ \8816 [399] = 41'h00000000000;
+ \8816 [400] = 41'h00000240a75;
+ \8816 [401] = 41'h00000000000;
+ \8816 [402] = 41'h00000000000;
+ \8816 [403] = 41'h00000000000;
+ \8816 [404] = 41'h00000000000;
+ \8816 [405] = 41'h00000000000;
+ \8816 [406] = 41'h00000000000;
+ \8816 [407] = 41'h04006840109;
+ \8816 [408] = 41'h00000000000;
+ \8816 [409] = 41'h00000000000;
+ \8816 [410] = 41'h00000000000;
+ \8816 [411] = 41'h00000000000;
+ \8816 [412] = 41'h00000000000;
+ \8816 [413] = 41'h00000000000;
+ \8816 [414] = 41'h00000000000;
+ \8816 [415] = 41'h00000000000;
+ \8816 [416] = 41'h00000000000;
+ \8816 [417] = 41'h00000000000;
+ \8816 [418] = 41'h00000000000;
+ \8816 [419] = 41'h00000000000;
+ \8816 [420] = 41'h00000000000;
+ \8816 [421] = 41'h00000000000;
+ \8816 [422] = 41'h00000000000;
+ \8816 [423] = 41'h00000000000;
+ \8816 [424] = 41'h00040100a86;
+ \8816 [425] = 41'h10000000005;
+ \8816 [426] = 41'h00000000000;
+ \8816 [427] = 41'h00000000000;
+ \8816 [428] = 41'h00000000000;
+ \8816 [429] = 41'h00000000005;
+ \8816 [430] = 41'h00000000000;
+ \8816 [431] = 41'h00000000000;
+ \8816 [432] = 41'h00000240a75;
+ \8816 [433] = 41'h00000000000;
+ \8816 [434] = 41'h00000000000;
+ \8816 [435] = 41'h00000000000;
+ \8816 [436] = 41'h058000409b5;
+ \8816 [437] = 41'h00000000000;
+ \8816 [438] = 41'h050000409b1;
+ \8816 [439] = 41'h00000000000;
+ \8816 [440] = 41'h00000000000;
+ \8816 [441] = 41'h00000000000;
+ \8816 [442] = 41'h00000000000;
+ \8816 [443] = 41'h00000000000;
+ \8816 [444] = 41'h00000000000;
+ \8816 [445] = 41'h00000000000;
+ \8816 [446] = 41'h00000000000;
+ \8816 [447] = 41'h0000040008d;
+ \8816 [448] = 41'h00000000000;
+ \8816 [449] = 41'h00000000000;
+ \8816 [450] = 41'h00000000000;
+ \8816 [451] = 41'h00000000000;
+ \8816 [452] = 41'h00000000000;
+ \8816 [453] = 41'h04000088035;
+ \8816 [454] = 41'h00000000000;
+ \8816 [455] = 41'h00000000000;
+ \8816 [456] = 41'h00a30100a86;
+ \8816 [457] = 41'h00000000000;
+ \8816 [458] = 41'h00000000000;
+ \8816 [459] = 41'h00000000000;
+ \8816 [460] = 41'h00000000000;
+ \8816 [461] = 41'h00000000005;
+ \8816 [462] = 41'h00000000000;
+ \8816 [463] = 41'h00000000000;
+ \8816 [464] = 41'h00000240a75;
+ \8816 [465] = 41'h00000000000;
+ \8816 [466] = 41'h00000000000;
+ \8816 [467] = 41'h00000000000;
+ \8816 [468] = 41'h00000000000;
+ \8816 [469] = 41'h00000000000;
+ \8816 [470] = 41'h00000000000;
+ \8816 [471] = 41'h04006840909;
+ \8816 [472] = 41'h00000000000;
+ \8816 [473] = 41'h00000000000;
+ \8816 [474] = 41'h00000000000;
+ \8816 [475] = 41'h00000000000;
+ \8816 [476] = 41'h00000000000;
+ \8816 [477] = 41'h00000000000;
+ \8816 [478] = 41'h00000000000;
+ \8816 [479] = 41'h00000000000;
+ \8816 [480] = 41'h00000000000;
+ \8816 [481] = 41'h00000000000;
+ \8816 [482] = 41'h00000000000;
+ \8816 [483] = 41'h00000000000;
+ \8816 [484] = 41'h040000888e1;
+ \8816 [485] = 41'h04800088035;
+ \8816 [486] = 41'h00000000000;
+ \8816 [487] = 41'h048000888e1;
+ \8816 [488] = 41'h00830100a86;
+ \8816 [489] = 41'h000b0040a7e;
+ \8816 [490] = 41'h00000000000;
+ \8816 [491] = 41'h000c0040a7e;
+ \8816 [492] = 41'h00000000000;
+ \8816 [493] = 41'h00000000005;
+ \8816 [494] = 41'h00000000000;
+ \8816 [495] = 41'h00000000000;
+ \8816 [496] = 41'h00000240a75;
+ \8816 [497] = 41'h00000000000;
+ \8816 [498] = 41'h00000000000;
+ \8816 [499] = 41'h00000000000;
+ \8816 [500] = 41'h048000409b5;
+ \8816 [501] = 41'h04008040909;
+ \8816 [502] = 41'h040000409b1;
+ \8816 [503] = 41'h0400e840909;
+ \8816 [504] = 41'h00000000000;
+ \8816 [505] = 41'h00000000000;
+ \8816 [506] = 41'h00000000000;
+ \8816 [507] = 41'h00000000000;
+ \8816 [508] = 41'h00000000000;
+ \8816 [509] = 41'h00000000000;
+ \8816 [510] = 41'h00000000000;
+ \8816 [511] = 41'h00000000000;
+ \8816 [512] = 41'h00000000000;
+ \8816 [513] = 41'h00000000000;
+ \8816 [514] = 41'h00000000000;
+ \8816 [515] = 41'h00000488829;
+ \8816 [516] = 41'h00000000000;
+ \8816 [517] = 41'h000400880bd;
+ \8816 [518] = 41'h00000000000;
+ \8816 [519] = 41'h00000000000;
+ \8816 [520] = 41'h00000000000;
+ \8816 [521] = 41'h00000000000;
+ \8816 [522] = 41'h00000000000;
+ \8816 [523] = 41'h00000000000;
+ \8816 [524] = 41'h00000000000;
+ \8816 [525] = 41'h000000000ea;
+ \8816 [526] = 41'h00000000000;
+ \8816 [527] = 41'h00000000000;
+ \8816 [528] = 41'h00000240a75;
+ \8816 [529] = 41'h00000000000;
+ \8816 [530] = 41'h00000000000;
+ \8816 [531] = 41'h00000000000;
+ \8816 [532] = 41'h05800040955;
+ \8816 [533] = 41'h00000000000;
+ \8816 [534] = 41'h05000040955;
+ \8816 [535] = 41'h00000000000;
+ \8816 [536] = 41'h00000000000;
+ \8816 [537] = 41'h00000000000;
+ \8816 [538] = 41'h00000000000;
+ \8816 [539] = 41'h00000000000;
+ \8816 [540] = 41'h00000000000;
+ \8816 [541] = 41'h00000000000;
+ \8816 [542] = 41'h00000000000;
+ \8816 [543] = 41'h00000000000;
+ \8816 [544] = 41'h00000000000;
+ \8816 [545] = 41'h00000000000;
+ \8816 [546] = 41'h00000000000;
+ \8816 [547] = 41'h0400108880d;
+ \8816 [548] = 41'h00000000000;
+ \8816 [549] = 41'h00000000000;
+ \8816 [550] = 41'h00000000000;
+ \8816 [551] = 41'h00000000000;
+ \8816 [552] = 41'h00000000000;
+ \8816 [553] = 41'h00000000000;
+ \8816 [554] = 41'h00000000000;
+ \8816 [555] = 41'h00000000000;
+ \8816 [556] = 41'h000000c80a9;
+ \8816 [557] = 41'h00000000000;
+ \8816 [558] = 41'h00000000000;
+ \8816 [559] = 41'h00000000000;
+ \8816 [560] = 41'h00000240a75;
+ \8816 [561] = 41'h00000000000;
+ \8816 [562] = 41'h00000000000;
+ \8816 [563] = 41'h00000000000;
+ \8816 [564] = 41'h04800040955;
+ \8816 [565] = 41'h00000000000;
+ \8816 [566] = 41'h04000040955;
+ \8816 [567] = 41'h00000000000;
+ \8816 [568] = 41'h00000000000;
+ \8816 [569] = 41'h00000000000;
+ \8816 [570] = 41'h00000000000;
+ \8816 [571] = 41'h00000000000;
+ \8816 [572] = 41'h00000000000;
+ \8816 [573] = 41'h00000000000;
+ \8816 [574] = 41'h00000000000;
+ \8816 [575] = 41'h00000000000;
+ \8816 [576] = 41'h00000000000;
+ \8816 [577] = 41'h00000000000;
+ \8816 [578] = 41'h00000000000;
+ \8816 [579] = 41'h040000888b9;
+ \8816 [580] = 41'h00000000000;
+ \8816 [581] = 41'h00000000000;
+ \8816 [582] = 41'h00000000000;
+ \8816 [583] = 41'h00000000000;
+ \8816 [584] = 41'h00220008a82;
+ \8816 [585] = 41'h00000000000;
+ \8816 [586] = 41'h00000000000;
+ \8816 [587] = 41'h00000000000;
+ \8816 [588] = 41'h00000000000;
+ \8816 [589] = 41'h00000000000;
+ \8816 [590] = 41'h00000000000;
+ \8816 [591] = 41'h00000000000;
+ \8816 [592] = 41'h00000240a75;
+ \8816 [593] = 41'h00000000000;
+ \8816 [594] = 41'h00000000000;
+ \8816 [595] = 41'h00000000000;
+ \8816 [596] = 41'h05800040959;
+ \8816 [597] = 41'h00000000000;
+ \8816 [598] = 41'h05000040959;
+ \8816 [599] = 41'h00000000000;
+ \8816 [600] = 41'h00000000000;
+ \8816 [601] = 41'h00000000000;
+ \8816 [602] = 41'h00000000000;
+ \8816 [603] = 41'h00000000000;
+ \8816 [604] = 41'h00000000000;
+ \8816 [605] = 41'h00000000000;
+ \8816 [606] = 41'h00000000000;
+ \8816 [607] = 41'h00000000000;
+ \8816 [608] = 41'h00000000000;
+ \8816 [609] = 41'h00000000000;
+ \8816 [610] = 41'h00000000000;
+ \8816 [611] = 41'h040008888b9;
+ \8816 [612] = 41'h00000000000;
+ \8816 [613] = 41'h00000000000;
+ \8816 [614] = 41'h00000000000;
+ \8816 [615] = 41'h00000000000;
+ \8816 [616] = 41'h00020008a82;
+ \8816 [617] = 41'h00000000000;
+ \8816 [618] = 41'h00000000000;
+ \8816 [619] = 41'h00000000000;
+ \8816 [620] = 41'h00000000000;
+ \8816 [621] = 41'h00000000000;
+ \8816 [622] = 41'h00000000000;
+ \8816 [623] = 41'h00000000000;
+ \8816 [624] = 41'h00000240a75;
+ \8816 [625] = 41'h00000000000;
+ \8816 [626] = 41'h00000000000;
+ \8816 [627] = 41'h00000000000;
+ \8816 [628] = 41'h04800040959;
+ \8816 [629] = 41'h00000000000;
+ \8816 [630] = 41'h04000040959;
+ \8816 [631] = 41'h00000000000;
+ \8816 [632] = 41'h00000000000;
+ \8816 [633] = 41'h00000000000;
+ \8816 [634] = 41'h00000000000;
+ \8816 [635] = 41'h00000000000;
+ \8816 [636] = 41'h00000000000;
+ \8816 [637] = 41'h00000000000;
+ \8816 [638] = 41'h00000000000;
+ \8816 [639] = 41'h00000000000;
+ \8816 [640] = 41'h00000000000;
+ \8816 [641] = 41'h00000000000;
+ \8816 [642] = 41'h00000000000;
+ \8816 [643] = 41'h00000000000;
+ \8816 [644] = 41'h00000000000;
+ \8816 [645] = 41'h000300880bd;
+ \8816 [646] = 41'h00000000000;
+ \8816 [647] = 41'h00000000000;
+ \8816 [648] = 41'h00320040a7e;
+ \8816 [649] = 41'h00000000000;
+ \8816 [650] = 41'h00330040a7e;
+ \8816 [651] = 41'h00000000000;
+ \8816 [652] = 41'h00000000000;
+ \8816 [653] = 41'h00000000000;
+ \8816 [654] = 41'h00000000000;
+ \8816 [655] = 41'h00000000000;
+ \8816 [656] = 41'h00000240a75;
+ \8816 [657] = 41'h00000000000;
+ \8816 [658] = 41'h00000000000;
+ \8816 [659] = 41'h00000000000;
+ \8816 [660] = 41'h00000000000;
+ \8816 [661] = 41'h00000000000;
+ \8816 [662] = 41'h00000000000;
+ \8816 [663] = 41'h00000000000;
+ \8816 [664] = 41'h00000000000;
+ \8816 [665] = 41'h00000000000;
+ \8816 [666] = 41'h00000000000;
+ \8816 [667] = 41'h00000000000;
+ \8816 [668] = 41'h00000000000;
+ \8816 [669] = 41'h00000000000;
+ \8816 [670] = 41'h00000000000;
+ \8816 [671] = 41'h00000000000;
+ \8816 [672] = 41'h00000000000;
+ \8816 [673] = 41'h00000000000;
+ \8816 [674] = 41'h00000000000;
+ \8816 [675] = 41'h00000000000;
+ \8816 [676] = 41'h00000000000;
+ \8816 [677] = 41'h00000000000;
+ \8816 [678] = 41'h00000000000;
+ \8816 [679] = 41'h00000000000;
+ \8816 [680] = 41'h00120040a7e;
+ \8816 [681] = 41'h00000000000;
+ \8816 [682] = 41'h00130040a7e;
+ \8816 [683] = 41'h00000000000;
+ \8816 [684] = 41'h00000048399;
+ \8816 [685] = 41'h00000000000;
+ \8816 [686] = 41'h00000000000;
+ \8816 [687] = 41'h00000000000;
+ \8816 [688] = 41'h00000240a75;
+ \8816 [689] = 41'h00000000000;
+ \8816 [690] = 41'h00000000000;
+ \8816 [691] = 41'h00000000000;
+ \8816 [692] = 41'h00000000000;
+ \8816 [693] = 41'h00000000000;
+ \8816 [694] = 41'h00000000000;
+ \8816 [695] = 41'h00000000000;
+ \8816 [696] = 41'h00000000000;
+ \8816 [697] = 41'h00000000000;
+ \8816 [698] = 41'h00000000000;
+ \8816 [699] = 41'h00000000000;
+ \8816 [700] = 41'h00000000000;
+ \8816 [701] = 41'h00000000000;
+ \8816 [702] = 41'h00000000000;
+ \8816 [703] = 41'h00000000000;
+ \8816 [704] = 41'h00000000000;
+ \8816 [705] = 41'h00000000000;
+ \8816 [706] = 41'h00000000000;
+ \8816 [707] = 41'h040000888f1;
+ \8816 [708] = 41'h00000000000;
+ \8816 [709] = 41'h000000880f5;
+ \8816 [710] = 41'h00000000000;
+ \8816 [711] = 41'h00000000000;
+ \8816 [712] = 41'h00220040a7e;
+ \8816 [713] = 41'h00000000000;
+ \8816 [714] = 41'h00000000000;
+ \8816 [715] = 41'h00000000000;
+ \8816 [716] = 41'h00000000000;
+ \8816 [717] = 41'h000000088ea;
+ \8816 [718] = 41'h00000000000;
+ \8816 [719] = 41'h00000000000;
+ \8816 [720] = 41'h00000240a75;
+ \8816 [721] = 41'h00000000000;
+ \8816 [722] = 41'h00000000000;
+ \8816 [723] = 41'h00000000000;
+ \8816 [724] = 41'h00000000000;
+ \8816 [725] = 41'h00000000000;
+ \8816 [726] = 41'h00000000000;
+ \8816 [727] = 41'h00000000000;
+ \8816 [728] = 41'h00000000000;
+ \8816 [729] = 41'h00000000000;
+ \8816 [730] = 41'h00000000000;
+ \8816 [731] = 41'h00000000000;
+ \8816 [732] = 41'h00000000000;
+ \8816 [733] = 41'h00000000000;
+ \8816 [734] = 41'h00000000000;
+ \8816 [735] = 41'h00000000000;
+ \8816 [736] = 41'h00000000000;
+ \8816 [737] = 41'h00000000000;
+ \8816 [738] = 41'h00000000000;
+ \8816 [739] = 41'h040010888f1;
+ \8816 [740] = 41'h00000000000;
+ \8816 [741] = 41'h000008880f5;
+ \8816 [742] = 41'h00000000000;
+ \8816 [743] = 41'h00000000000;
+ \8816 [744] = 41'h00020040a7e;
+ \8816 [745] = 41'h10000000049;
+ \8816 [746] = 41'h00000000000;
+ \8816 [747] = 41'h00000000000;
+ \8816 [748] = 41'h00000000000;
+ \8816 [749] = 41'h000000088ea;
+ \8816 [750] = 41'h00000000000;
+ \8816 [751] = 41'h00000000000;
+ \8816 [752] = 41'h00000240a75;
+ \8816 [753] = 41'h00000000000;
+ \8816 [754] = 41'h00000000000;
+ \8816 [755] = 41'h00000000000;
+ \8816 [756] = 41'h0080004099d;
+ \8816 [757] = 41'h04000040909;
+ \8816 [758] = 41'h0000004099d;
+ \8816 [759] = 41'h00000000000;
+ \8816 [760] = 41'h00000000000;
+ \8816 [761] = 41'h00000000000;
+ \8816 [762] = 41'h00000000000;
+ \8816 [763] = 41'h00000000000;
+ \8816 [764] = 41'h00000000000;
+ \8816 [765] = 41'h00000000000;
+ \8816 [766] = 41'h00000000000;
+ \8816 [767] = 41'h00000000000;
+ \8816 [768] = 41'h00000000000;
+ \8816 [769] = 41'h00000000000;
+ \8816 [770] = 41'h00000000000;
+ \8816 [771] = 41'h00000088021;
+ \8816 [772] = 41'h00000000000;
+ \8816 [773] = 41'h00000000000;
+ \8816 [774] = 41'h00000000000;
+ \8816 [775] = 41'h00000000000;
+ \8816 [776] = 41'h00210008a82;
+ \8816 [777] = 41'h1000000004d;
+ \8816 [778] = 41'h00000000000;
+ \8816 [779] = 41'h00000000000;
+ \8816 [780] = 41'h00000000000;
+ \8816 [781] = 41'h00000000000;
+ \8816 [782] = 41'h00000000000;
+ \8816 [783] = 41'h00000000000;
+ \8816 [784] = 41'h00000240a75;
+ \8816 [785] = 41'h00000000000;
+ \8816 [786] = 41'h00000000000;
+ \8816 [787] = 41'h00000000000;
+ \8816 [788] = 41'h058000409ad;
+ \8816 [789] = 41'h0400a045109;
+ \8816 [790] = 41'h050000409ad;
+ \8816 [791] = 41'h0400a845109;
+ \8816 [792] = 41'h00000000000;
+ \8816 [793] = 41'h00000000000;
+ \8816 [794] = 41'h00000000000;
+ \8816 [795] = 41'h00000000000;
+ \8816 [796] = 41'h00000000000;
+ \8816 [797] = 41'h00000000000;
+ \8816 [798] = 41'h00000000000;
+ \8816 [799] = 41'h0000040092d;
+ \8816 [800] = 41'h00000000000;
+ \8816 [801] = 41'h00000000000;
+ \8816 [802] = 41'h00000000000;
+ \8816 [803] = 41'h00000000000;
+ \8816 [804] = 41'h00000000000;
+ \8816 [805] = 41'h00000000000;
+ \8816 [806] = 41'h00000000000;
+ \8816 [807] = 41'h00000000000;
+ \8816 [808] = 41'h00010008a82;
+ \8816 [809] = 41'h02440008a82;
+ \8816 [810] = 41'h00000000000;
+ \8816 [811] = 41'h00000000000;
+ \8816 [812] = 41'h00000000000;
+ \8816 [813] = 41'h00000000000;
+ \8816 [814] = 41'h00000000000;
+ \8816 [815] = 41'h00000000000;
+ \8816 [816] = 41'h00000240a75;
+ \8816 [817] = 41'h00000000000;
+ \8816 [818] = 41'h00000000000;
+ \8816 [819] = 41'h00000000000;
+ \8816 [820] = 41'h00000000000;
+ \8816 [821] = 41'h0400a040109;
+ \8816 [822] = 41'h00000000000;
+ \8816 [823] = 41'h0400a840109;
+ \8816 [824] = 41'h00000000000;
+ \8816 [825] = 41'h00000000000;
+ \8816 [826] = 41'h00000000000;
+ \8816 [827] = 41'h00000000000;
+ \8816 [828] = 41'h00000000000;
+ \8816 [829] = 41'h00000000000;
+ \8816 [830] = 41'h00000000000;
+ \8816 [831] = 41'h00000400931;
+ \8816 [832] = 41'h00000000000;
+ \8816 [833] = 41'h00000000000;
+ \8816 [834] = 41'h00000000000;
+ \8816 [835] = 41'h00000000000;
+ \8816 [836] = 41'h00000000000;
+ \8816 [837] = 41'h000400880c1;
+ \8816 [838] = 41'h00000000000;
+ \8816 [839] = 41'h00000000000;
+ \8816 [840] = 41'h00230008a82;
+ \8816 [841] = 41'h00000000000;
+ \8816 [842] = 41'h00240008a82;
+ \8816 [843] = 41'h00000000000;
+ \8816 [844] = 41'h00000000000;
+ \8816 [845] = 41'h100000080a5;
+ \8816 [846] = 41'h00000000000;
+ \8816 [847] = 41'h00000000000;
+ \8816 [848] = 41'h00000240a75;
+ \8816 [849] = 41'h00000000000;
+ \8816 [850] = 41'h00000000000;
+ \8816 [851] = 41'h00000000000;
+ \8816 [852] = 41'h00000000000;
+ \8816 [853] = 41'h0400c040909;
+ \8816 [854] = 41'h00000000000;
+ \8816 [855] = 41'h00000000000;
+ \8816 [856] = 41'h00000000000;
+ \8816 [857] = 41'h00000000000;
+ \8816 [858] = 41'h00000000000;
+ \8816 [859] = 41'h00000000000;
+ \8816 [860] = 41'h00000000000;
+ \8816 [861] = 41'h00000000000;
+ \8816 [862] = 41'h00000000000;
+ \8816 [863] = 41'h00000000000;
+ \8816 [864] = 41'h00000000000;
+ \8816 [865] = 41'h00000000000;
+ \8816 [866] = 41'h00000000000;
+ \8816 [867] = 41'h00000000000;
+ \8816 [868] = 41'h00000000000;
+ \8816 [869] = 41'h000300880c1;
+ \8816 [870] = 41'h00000000000;
+ \8816 [871] = 41'h00000000000;
+ \8816 [872] = 41'h00030008a82;
+ \8816 [873] = 41'h02430008a82;
+ \8816 [874] = 41'h00040008a82;
+ \8816 [875] = 41'h00000000000;
+ \8816 [876] = 41'h00000000000;
+ \8816 [877] = 41'h108000080a5;
+ \8816 [878] = 41'h00000000000;
+ \8816 [879] = 41'h000004080a1;
+ \8816 [880] = 41'h00000240a75;
+ \8816 [881] = 41'h00000000000;
+ \8816 [882] = 41'h00000000000;
+ \8816 [883] = 41'h00000000000;
+ \8816 [884] = 41'h00000000000;
+ \8816 [885] = 41'h0400a040909;
+ \8816 [886] = 41'h00000000000;
+ \8816 [887] = 41'h0400a840909;
+ \8816 [888] = 41'h00000000000;
+ \8816 [889] = 41'h00000000000;
+ \8816 [890] = 41'h00000000000;
+ \8816 [891] = 41'h00000000000;
+ \8816 [892] = 41'h00000000000;
+ \8816 [893] = 41'h00000000000;
+ \8816 [894] = 41'h00000000000;
+ \8816 [895] = 41'h000002400d9;
+ \8816 [896] = 41'h00000000000;
+ \8816 [897] = 41'h00000000000;
+ \8816 [898] = 41'h00000000000;
+ \8816 [899] = 41'h040010888b9;
+ \8816 [900] = 41'h00000000000;
+ \8816 [901] = 41'h000100880bd;
+ \8816 [902] = 41'h00000000000;
+ \8816 [903] = 41'h00000000000;
+ \8816 [904] = 41'h00210040a7e;
+ \8816 [905] = 41'h00000000000;
+ \8816 [906] = 41'h00000000000;
+ \8816 [907] = 41'h00420040a7e;
+ \8816 [908] = 41'h00000000000;
+ \8816 [909] = 41'h00000000000;
+ \8816 [910] = 41'h00000000000;
+ \8816 [911] = 41'h00000000000;
+ \8816 [912] = 41'h00000240a75;
+ \8816 [913] = 41'h00000000000;
+ \8816 [914] = 41'h00000000000;
+ \8816 [915] = 41'h00000000000;
+ \8816 [916] = 41'h00000000000;
+ \8816 [917] = 41'h00000000000;
+ \8816 [918] = 41'h00000000000;
+ \8816 [919] = 41'h04006840109;
+ \8816 [920] = 41'h00000000000;
+ \8816 [921] = 41'h00000000000;
+ \8816 [922] = 41'h00000000000;
+ \8816 [923] = 41'h00000000000;
+ \8816 [924] = 41'h00000000000;
+ \8816 [925] = 41'h00000000000;
+ \8816 [926] = 41'h00000000000;
+ \8816 [927] = 41'h00000000000;
+ \8816 [928] = 41'h00000000000;
+ \8816 [929] = 41'h00000000000;
+ \8816 [930] = 41'h00000000000;
+ \8816 [931] = 41'h00000000000;
+ \8816 [932] = 41'h00000000000;
+ \8816 [933] = 41'h00000000000;
+ \8816 [934] = 41'h00000000000;
+ \8816 [935] = 41'h00000000000;
+ \8816 [936] = 41'h00010040a7e;
+ \8816 [937] = 41'h10000000041;
+ \8816 [938] = 41'h00000000000;
+ \8816 [939] = 41'h00440040a7e;
+ \8816 [940] = 41'h10000040095;
+ \8816 [941] = 41'h00000000000;
+ \8816 [942] = 41'h00000000000;
+ \8816 [943] = 41'h00000000000;
+ \8816 [944] = 41'h00000240a75;
+ \8816 [945] = 41'h00000000000;
+ \8816 [946] = 41'h00000000000;
+ \8816 [947] = 41'h00000000000;
+ \8816 [948] = 41'h058000409b5;
+ \8816 [949] = 41'h000000409f9;
+ \8816 [950] = 41'h050000409b1;
+ \8816 [951] = 41'h00000000000;
+ \8816 [952] = 41'h00000000000;
+ \8816 [953] = 41'h00000000000;
+ \8816 [954] = 41'h00000000000;
+ \8816 [955] = 41'h100000009ed;
+ \8816 [956] = 41'h00000000000;
+ \8816 [957] = 41'h00000000000;
+ \8816 [958] = 41'h00000000000;
+ \8816 [959] = 41'h00000000000;
+ \8816 [960] = 41'h00000000000;
+ \8816 [961] = 41'h00000000000;
+ \8816 [962] = 41'h00000000000;
+ \8816 [963] = 41'h0400088880d;
+ \8816 [964] = 41'h00000000000;
+ \8816 [965] = 41'h04000088035;
+ \8816 [966] = 41'h00000000000;
+ \8816 [967] = 41'h00000000000;
+ \8816 [968] = 41'h00230040a7e;
+ \8816 [969] = 41'h10000000045;
+ \8816 [970] = 41'h00240040a7e;
+ \8816 [971] = 41'h00410040a7e;
+ \8816 [972] = 41'h00000000000;
+ \8816 [973] = 41'h00000000000;
+ \8816 [974] = 41'h00000000000;
+ \8816 [975] = 41'h00000000000;
+ \8816 [976] = 41'h00000240a75;
+ \8816 [977] = 41'h00000000000;
+ \8816 [978] = 41'h00000000000;
+ \8816 [979] = 41'h00000000000;
+ \8816 [980] = 41'h00000000000;
+ \8816 [981] = 41'h00000000000;
+ \8816 [982] = 41'h00000000000;
+ \8816 [983] = 41'h04006840909;
+ \8816 [984] = 41'h00000000000;
+ \8816 [985] = 41'h00000000000;
+ \8816 [986] = 41'h00000000000;
+ \8816 [987] = 41'h00000000000;
+ \8816 [988] = 41'h00000000000;
+ \8816 [989] = 41'h00000000000;
+ \8816 [990] = 41'h00000000000;
+ \8816 [991] = 41'h00006c00925;
+ \8816 [992] = 41'h00000000000;
+ \8816 [993] = 41'h10000000005;
+ \8816 [994] = 41'h00000000000;
+ \8816 [995] = 41'h0400008880d;
+ \8816 [996] = 41'h040000888dd;
+ \8816 [997] = 41'h04800088035;
+ \8816 [998] = 41'h00000000000;
+ \8816 [999] = 41'h048000888dd;
+ \8816 [1000] = 41'h00030040a7e;
+ \8816 [1001] = 41'h10000000071;
+ \8816 [1002] = 41'h00040040a7e;
+ \8816 [1003] = 41'h00430040a7e;
+ \8816 [1004] = 41'h00000240091;
+ \8816 [1005] = 41'h00000000000;
+ \8816 [1006] = 41'h00000000000;
+ \8816 [1007] = 41'h00000000000;
+ \8816 [1008] = 41'h10000240a75;
+ \8816 [1009] = 41'h00000000000;
+ \8816 [1010] = 41'h00000000000;
+ \8816 [1011] = 41'h00000000000;
+ \8816 [1012] = 41'h048000409b5;
+ \8816 [1013] = 41'h04008040909;
+ \8816 [1014] = 41'h040000409b1;
+ \8816 [1015] = 41'h0400e840909;
+ \8816 [1016] = 41'h00000000000;
+ \8816 [1017] = 41'h00000000000;
+ \8816 [1018] = 41'h00000000000;
+ \8816 [1019] = 41'h108000009ed;
+ \8816 [1020] = 41'h00000000000;
+ \8816 [1021] = 41'h00000000000;
+ \8816 [1022] = 41'h00000000000;
+ \8816 [1023] = 41'h01006c00925;
+ end
+ assign _131_ = \8816 [_031_];
+ reg [0:0] \8818 [1023:0];
+ initial begin
+ \8818 [0] = 1'h0;
+ \8818 [1] = 1'h0;
+ \8818 [2] = 1'h0;
+ \8818 [3] = 1'h0;
+ \8818 [4] = 1'h0;
+ \8818 [5] = 1'h0;
+ \8818 [6] = 1'h0;
+ \8818 [7] = 1'h0;
+ \8818 [8] = 1'h0;
+ \8818 [9] = 1'h0;
+ \8818 [10] = 1'h0;
+ \8818 [11] = 1'h0;
+ \8818 [12] = 1'h0;
+ \8818 [13] = 1'h0;
+ \8818 [14] = 1'h0;
+ \8818 [15] = 1'h0;
+ \8818 [16] = 1'h0;
+ \8818 [17] = 1'h0;
+ \8818 [18] = 1'h0;
+ \8818 [19] = 1'h0;
+ \8818 [20] = 1'h0;
+ \8818 [21] = 1'h0;
+ \8818 [22] = 1'h0;
+ \8818 [23] = 1'h0;
+ \8818 [24] = 1'h0;
+ \8818 [25] = 1'h0;
+ \8818 [26] = 1'h0;
+ \8818 [27] = 1'h0;
+ \8818 [28] = 1'h0;
+ \8818 [29] = 1'h0;
+ \8818 [30] = 1'h0;
+ \8818 [31] = 1'h0;
+ \8818 [32] = 1'h0;
+ \8818 [33] = 1'h0;
+ \8818 [34] = 1'h0;
+ \8818 [35] = 1'h0;
+ \8818 [36] = 1'h0;
+ \8818 [37] = 1'h0;
+ \8818 [38] = 1'h0;
+ \8818 [39] = 1'h0;
+ \8818 [40] = 1'h0;
+ \8818 [41] = 1'h0;
+ \8818 [42] = 1'h0;
+ \8818 [43] = 1'h0;
+ \8818 [44] = 1'h0;
+ \8818 [45] = 1'h0;
+ \8818 [46] = 1'h0;
+ \8818 [47] = 1'h0;
+ \8818 [48] = 1'h0;
+ \8818 [49] = 1'h0;
+ \8818 [50] = 1'h0;
+ \8818 [51] = 1'h0;
+ \8818 [52] = 1'h0;
+ \8818 [53] = 1'h0;
+ \8818 [54] = 1'h0;
+ \8818 [55] = 1'h0;
+ \8818 [56] = 1'h0;
+ \8818 [57] = 1'h0;
+ \8818 [58] = 1'h0;
+ \8818 [59] = 1'h0;
+ \8818 [60] = 1'h0;
+ \8818 [61] = 1'h0;
+ \8818 [62] = 1'h0;
+ \8818 [63] = 1'h0;
+ \8818 [64] = 1'h0;
+ \8818 [65] = 1'h0;
+ \8818 [66] = 1'h0;
+ \8818 [67] = 1'h0;
+ \8818 [68] = 1'h0;
+ \8818 [69] = 1'h0;
+ \8818 [70] = 1'h0;
+ \8818 [71] = 1'h0;
+ \8818 [72] = 1'h0;
+ \8818 [73] = 1'h0;
+ \8818 [74] = 1'h0;
+ \8818 [75] = 1'h0;
+ \8818 [76] = 1'h0;
+ \8818 [77] = 1'h0;
+ \8818 [78] = 1'h0;
+ \8818 [79] = 1'h0;
+ \8818 [80] = 1'h0;
+ \8818 [81] = 1'h0;
+ \8818 [82] = 1'h0;
+ \8818 [83] = 1'h0;
+ \8818 [84] = 1'h0;
+ \8818 [85] = 1'h0;
+ \8818 [86] = 1'h0;
+ \8818 [87] = 1'h0;
+ \8818 [88] = 1'h0;
+ \8818 [89] = 1'h0;
+ \8818 [90] = 1'h0;
+ \8818 [91] = 1'h0;
+ \8818 [92] = 1'h0;
+ \8818 [93] = 1'h0;
+ \8818 [94] = 1'h0;
+ \8818 [95] = 1'h0;
+ \8818 [96] = 1'h0;
+ \8818 [97] = 1'h0;
+ \8818 [98] = 1'h0;
+ \8818 [99] = 1'h0;
+ \8818 [100] = 1'h0;
+ \8818 [101] = 1'h0;
+ \8818 [102] = 1'h0;
+ \8818 [103] = 1'h0;
+ \8818 [104] = 1'h0;
+ \8818 [105] = 1'h0;
+ \8818 [106] = 1'h0;
+ \8818 [107] = 1'h0;
+ \8818 [108] = 1'h0;
+ \8818 [109] = 1'h0;
+ \8818 [110] = 1'h0;
+ \8818 [111] = 1'h0;
+ \8818 [112] = 1'h0;
+ \8818 [113] = 1'h0;
+ \8818 [114] = 1'h0;
+ \8818 [115] = 1'h0;
+ \8818 [116] = 1'h0;
+ \8818 [117] = 1'h0;
+ \8818 [118] = 1'h0;
+ \8818 [119] = 1'h0;
+ \8818 [120] = 1'h0;
+ \8818 [121] = 1'h0;
+ \8818 [122] = 1'h0;
+ \8818 [123] = 1'h0;
+ \8818 [124] = 1'h0;
+ \8818 [125] = 1'h0;
+ \8818 [126] = 1'h0;
+ \8818 [127] = 1'h0;
+ \8818 [128] = 1'h0;
+ \8818 [129] = 1'h0;
+ \8818 [130] = 1'h0;
+ \8818 [131] = 1'h0;
+ \8818 [132] = 1'h0;
+ \8818 [133] = 1'h0;
+ \8818 [134] = 1'h0;
+ \8818 [135] = 1'h0;
+ \8818 [136] = 1'h0;
+ \8818 [137] = 1'h0;
+ \8818 [138] = 1'h0;
+ \8818 [139] = 1'h0;
+ \8818 [140] = 1'h0;
+ \8818 [141] = 1'h0;
+ \8818 [142] = 1'h0;
+ \8818 [143] = 1'h0;
+ \8818 [144] = 1'h0;
+ \8818 [145] = 1'h0;
+ \8818 [146] = 1'h0;
+ \8818 [147] = 1'h0;
+ \8818 [148] = 1'h0;
+ \8818 [149] = 1'h0;
+ \8818 [150] = 1'h0;
+ \8818 [151] = 1'h0;
+ \8818 [152] = 1'h0;
+ \8818 [153] = 1'h0;
+ \8818 [154] = 1'h0;
+ \8818 [155] = 1'h0;
+ \8818 [156] = 1'h0;
+ \8818 [157] = 1'h0;
+ \8818 [158] = 1'h0;
+ \8818 [159] = 1'h0;
+ \8818 [160] = 1'h0;
+ \8818 [161] = 1'h0;
+ \8818 [162] = 1'h0;
+ \8818 [163] = 1'h0;
+ \8818 [164] = 1'h0;
+ \8818 [165] = 1'h0;
+ \8818 [166] = 1'h0;
+ \8818 [167] = 1'h0;
+ \8818 [168] = 1'h0;
+ \8818 [169] = 1'h0;
+ \8818 [170] = 1'h0;
+ \8818 [171] = 1'h0;
+ \8818 [172] = 1'h0;
+ \8818 [173] = 1'h0;
+ \8818 [174] = 1'h0;
+ \8818 [175] = 1'h0;
+ \8818 [176] = 1'h0;
+ \8818 [177] = 1'h0;
+ \8818 [178] = 1'h0;
+ \8818 [179] = 1'h0;
+ \8818 [180] = 1'h0;
+ \8818 [181] = 1'h0;
+ \8818 [182] = 1'h0;
+ \8818 [183] = 1'h0;
+ \8818 [184] = 1'h0;
+ \8818 [185] = 1'h0;
+ \8818 [186] = 1'h0;
+ \8818 [187] = 1'h0;
+ \8818 [188] = 1'h0;
+ \8818 [189] = 1'h0;
+ \8818 [190] = 1'h0;
+ \8818 [191] = 1'h0;
+ \8818 [192] = 1'h0;
+ \8818 [193] = 1'h0;
+ \8818 [194] = 1'h0;
+ \8818 [195] = 1'h0;
+ \8818 [196] = 1'h0;
+ \8818 [197] = 1'h0;
+ \8818 [198] = 1'h0;
+ \8818 [199] = 1'h0;
+ \8818 [200] = 1'h0;
+ \8818 [201] = 1'h0;
+ \8818 [202] = 1'h0;
+ \8818 [203] = 1'h0;
+ \8818 [204] = 1'h0;
+ \8818 [205] = 1'h0;
+ \8818 [206] = 1'h0;
+ \8818 [207] = 1'h0;
+ \8818 [208] = 1'h0;
+ \8818 [209] = 1'h0;
+ \8818 [210] = 1'h0;
+ \8818 [211] = 1'h0;
+ \8818 [212] = 1'h0;
+ \8818 [213] = 1'h0;
+ \8818 [214] = 1'h0;
+ \8818 [215] = 1'h0;
+ \8818 [216] = 1'h0;
+ \8818 [217] = 1'h0;
+ \8818 [218] = 1'h0;
+ \8818 [219] = 1'h0;
+ \8818 [220] = 1'h0;
+ \8818 [221] = 1'h0;
+ \8818 [222] = 1'h0;
+ \8818 [223] = 1'h0;
+ \8818 [224] = 1'h0;
+ \8818 [225] = 1'h0;
+ \8818 [226] = 1'h0;
+ \8818 [227] = 1'h0;
+ \8818 [228] = 1'h0;
+ \8818 [229] = 1'h0;
+ \8818 [230] = 1'h0;
+ \8818 [231] = 1'h0;
+ \8818 [232] = 1'h0;
+ \8818 [233] = 1'h0;
+ \8818 [234] = 1'h0;
+ \8818 [235] = 1'h0;
+ \8818 [236] = 1'h0;
+ \8818 [237] = 1'h0;
+ \8818 [238] = 1'h0;
+ \8818 [239] = 1'h0;
+ \8818 [240] = 1'h0;
+ \8818 [241] = 1'h0;
+ \8818 [242] = 1'h0;
+ \8818 [243] = 1'h0;
+ \8818 [244] = 1'h0;
+ \8818 [245] = 1'h0;
+ \8818 [246] = 1'h0;
+ \8818 [247] = 1'h0;
+ \8818 [248] = 1'h0;
+ \8818 [249] = 1'h0;
+ \8818 [250] = 1'h0;
+ \8818 [251] = 1'h0;
+ \8818 [252] = 1'h0;
+ \8818 [253] = 1'h0;
+ \8818 [254] = 1'h0;
+ \8818 [255] = 1'h0;
+ \8818 [256] = 1'h0;
+ \8818 [257] = 1'h0;
+ \8818 [258] = 1'h0;
+ \8818 [259] = 1'h0;
+ \8818 [260] = 1'h0;
+ \8818 [261] = 1'h0;
+ \8818 [262] = 1'h0;
+ \8818 [263] = 1'h0;
+ \8818 [264] = 1'h0;
+ \8818 [265] = 1'h0;
+ \8818 [266] = 1'h0;
+ \8818 [267] = 1'h0;
+ \8818 [268] = 1'h0;
+ \8818 [269] = 1'h0;
+ \8818 [270] = 1'h0;
+ \8818 [271] = 1'h0;
+ \8818 [272] = 1'h0;
+ \8818 [273] = 1'h0;
+ \8818 [274] = 1'h0;
+ \8818 [275] = 1'h0;
+ \8818 [276] = 1'h0;
+ \8818 [277] = 1'h0;
+ \8818 [278] = 1'h0;
+ \8818 [279] = 1'h0;
+ \8818 [280] = 1'h0;
+ \8818 [281] = 1'h0;
+ \8818 [282] = 1'h0;
+ \8818 [283] = 1'h0;
+ \8818 [284] = 1'h0;
+ \8818 [285] = 1'h0;
+ \8818 [286] = 1'h0;
+ \8818 [287] = 1'h0;
+ \8818 [288] = 1'h0;
+ \8818 [289] = 1'h0;
+ \8818 [290] = 1'h0;
+ \8818 [291] = 1'h0;
+ \8818 [292] = 1'h0;
+ \8818 [293] = 1'h0;
+ \8818 [294] = 1'h0;
+ \8818 [295] = 1'h0;
+ \8818 [296] = 1'h0;
+ \8818 [297] = 1'h0;
+ \8818 [298] = 1'h0;
+ \8818 [299] = 1'h0;
+ \8818 [300] = 1'h0;
+ \8818 [301] = 1'h0;
+ \8818 [302] = 1'h0;
+ \8818 [303] = 1'h0;
+ \8818 [304] = 1'h0;
+ \8818 [305] = 1'h0;
+ \8818 [306] = 1'h0;
+ \8818 [307] = 1'h0;
+ \8818 [308] = 1'h0;
+ \8818 [309] = 1'h0;
+ \8818 [310] = 1'h0;
+ \8818 [311] = 1'h0;
+ \8818 [312] = 1'h0;
+ \8818 [313] = 1'h0;
+ \8818 [314] = 1'h0;
+ \8818 [315] = 1'h1;
+ \8818 [316] = 1'h0;
+ \8818 [317] = 1'h0;
+ \8818 [318] = 1'h0;
+ \8818 [319] = 1'h0;
+ \8818 [320] = 1'h0;
+ \8818 [321] = 1'h0;
+ \8818 [322] = 1'h0;
+ \8818 [323] = 1'h0;
+ \8818 [324] = 1'h0;
+ \8818 [325] = 1'h0;
+ \8818 [326] = 1'h0;
+ \8818 [327] = 1'h0;
+ \8818 [328] = 1'h0;
+ \8818 [329] = 1'h0;
+ \8818 [330] = 1'h0;
+ \8818 [331] = 1'h0;
+ \8818 [332] = 1'h0;
+ \8818 [333] = 1'h0;
+ \8818 [334] = 1'h0;
+ \8818 [335] = 1'h0;
+ \8818 [336] = 1'h0;
+ \8818 [337] = 1'h0;
+ \8818 [338] = 1'h0;
+ \8818 [339] = 1'h0;
+ \8818 [340] = 1'h0;
+ \8818 [341] = 1'h0;
+ \8818 [342] = 1'h0;
+ \8818 [343] = 1'h0;
+ \8818 [344] = 1'h0;
+ \8818 [345] = 1'h0;
+ \8818 [346] = 1'h0;
+ \8818 [347] = 1'h0;
+ \8818 [348] = 1'h0;
+ \8818 [349] = 1'h0;
+ \8818 [350] = 1'h0;
+ \8818 [351] = 1'h0;
+ \8818 [352] = 1'h0;
+ \8818 [353] = 1'h0;
+ \8818 [354] = 1'h0;
+ \8818 [355] = 1'h0;
+ \8818 [356] = 1'h0;
+ \8818 [357] = 1'h0;
+ \8818 [358] = 1'h0;
+ \8818 [359] = 1'h0;
+ \8818 [360] = 1'h0;
+ \8818 [361] = 1'h0;
+ \8818 [362] = 1'h0;
+ \8818 [363] = 1'h0;
+ \8818 [364] = 1'h0;
+ \8818 [365] = 1'h0;
+ \8818 [366] = 1'h0;
+ \8818 [367] = 1'h0;
+ \8818 [368] = 1'h0;
+ \8818 [369] = 1'h0;
+ \8818 [370] = 1'h0;
+ \8818 [371] = 1'h0;
+ \8818 [372] = 1'h0;
+ \8818 [373] = 1'h0;
+ \8818 [374] = 1'h0;
+ \8818 [375] = 1'h0;
+ \8818 [376] = 1'h0;
+ \8818 [377] = 1'h0;
+ \8818 [378] = 1'h0;
+ \8818 [379] = 1'h0;
+ \8818 [380] = 1'h0;
+ \8818 [381] = 1'h0;
+ \8818 [382] = 1'h0;
+ \8818 [383] = 1'h0;
+ \8818 [384] = 1'h0;
+ \8818 [385] = 1'h0;
+ \8818 [386] = 1'h0;
+ \8818 [387] = 1'h0;
+ \8818 [388] = 1'h0;
+ \8818 [389] = 1'h0;
+ \8818 [390] = 1'h0;
+ \8818 [391] = 1'h0;
+ \8818 [392] = 1'h0;
+ \8818 [393] = 1'h0;
+ \8818 [394] = 1'h0;
+ \8818 [395] = 1'h0;
+ \8818 [396] = 1'h0;
+ \8818 [397] = 1'h0;
+ \8818 [398] = 1'h0;
+ \8818 [399] = 1'h0;
+ \8818 [400] = 1'h0;
+ \8818 [401] = 1'h0;
+ \8818 [402] = 1'h0;
+ \8818 [403] = 1'h0;
+ \8818 [404] = 1'h0;
+ \8818 [405] = 1'h0;
+ \8818 [406] = 1'h0;
+ \8818 [407] = 1'h0;
+ \8818 [408] = 1'h0;
+ \8818 [409] = 1'h0;
+ \8818 [410] = 1'h0;
+ \8818 [411] = 1'h0;
+ \8818 [412] = 1'h0;
+ \8818 [413] = 1'h0;
+ \8818 [414] = 1'h0;
+ \8818 [415] = 1'h0;
+ \8818 [416] = 1'h0;
+ \8818 [417] = 1'h0;
+ \8818 [418] = 1'h0;
+ \8818 [419] = 1'h0;
+ \8818 [420] = 1'h0;
+ \8818 [421] = 1'h0;
+ \8818 [422] = 1'h0;
+ \8818 [423] = 1'h0;
+ \8818 [424] = 1'h0;
+ \8818 [425] = 1'h0;
+ \8818 [426] = 1'h0;
+ \8818 [427] = 1'h0;
+ \8818 [428] = 1'h0;
+ \8818 [429] = 1'h0;
+ \8818 [430] = 1'h0;
+ \8818 [431] = 1'h0;
+ \8818 [432] = 1'h0;
+ \8818 [433] = 1'h0;
+ \8818 [434] = 1'h0;
+ \8818 [435] = 1'h0;
+ \8818 [436] = 1'h0;
+ \8818 [437] = 1'h0;
+ \8818 [438] = 1'h0;
+ \8818 [439] = 1'h0;
+ \8818 [440] = 1'h0;
+ \8818 [441] = 1'h0;
+ \8818 [442] = 1'h0;
+ \8818 [443] = 1'h0;
+ \8818 [444] = 1'h0;
+ \8818 [445] = 1'h0;
+ \8818 [446] = 1'h0;
+ \8818 [447] = 1'h1;
+ \8818 [448] = 1'h0;
+ \8818 [449] = 1'h0;
+ \8818 [450] = 1'h0;
+ \8818 [451] = 1'h0;
+ \8818 [452] = 1'h0;
+ \8818 [453] = 1'h0;
+ \8818 [454] = 1'h0;
+ \8818 [455] = 1'h0;
+ \8818 [456] = 1'h0;
+ \8818 [457] = 1'h0;
+ \8818 [458] = 1'h0;
+ \8818 [459] = 1'h0;
+ \8818 [460] = 1'h0;
+ \8818 [461] = 1'h0;
+ \8818 [462] = 1'h0;
+ \8818 [463] = 1'h0;
+ \8818 [464] = 1'h0;
+ \8818 [465] = 1'h0;
+ \8818 [466] = 1'h0;
+ \8818 [467] = 1'h0;
+ \8818 [468] = 1'h0;
+ \8818 [469] = 1'h0;
+ \8818 [470] = 1'h0;
+ \8818 [471] = 1'h0;
+ \8818 [472] = 1'h0;
+ \8818 [473] = 1'h0;
+ \8818 [474] = 1'h0;
+ \8818 [475] = 1'h0;
+ \8818 [476] = 1'h0;
+ \8818 [477] = 1'h0;
+ \8818 [478] = 1'h0;
+ \8818 [479] = 1'h0;
+ \8818 [480] = 1'h0;
+ \8818 [481] = 1'h0;
+ \8818 [482] = 1'h0;
+ \8818 [483] = 1'h0;
+ \8818 [484] = 1'h0;
+ \8818 [485] = 1'h0;
+ \8818 [486] = 1'h0;
+ \8818 [487] = 1'h0;
+ \8818 [488] = 1'h0;
+ \8818 [489] = 1'h0;
+ \8818 [490] = 1'h0;
+ \8818 [491] = 1'h0;
+ \8818 [492] = 1'h0;
+ \8818 [493] = 1'h0;
+ \8818 [494] = 1'h1;
+ \8818 [495] = 1'h1;
+ \8818 [496] = 1'h0;
+ \8818 [497] = 1'h0;
+ \8818 [498] = 1'h0;
+ \8818 [499] = 1'h0;
+ \8818 [500] = 1'h0;
+ \8818 [501] = 1'h0;
+ \8818 [502] = 1'h0;
+ \8818 [503] = 1'h0;
+ \8818 [504] = 1'h0;
+ \8818 [505] = 1'h0;
+ \8818 [506] = 1'h0;
+ \8818 [507] = 1'h0;
+ \8818 [508] = 1'h0;
+ \8818 [509] = 1'h0;
+ \8818 [510] = 1'h0;
+ \8818 [511] = 1'h1;
+ \8818 [512] = 1'h0;
+ \8818 [513] = 1'h0;
+ \8818 [514] = 1'h0;
+ \8818 [515] = 1'h0;
+ \8818 [516] = 1'h0;
+ \8818 [517] = 1'h0;
+ \8818 [518] = 1'h0;
+ \8818 [519] = 1'h0;
+ \8818 [520] = 1'h0;
+ \8818 [521] = 1'h0;
+ \8818 [522] = 1'h0;
+ \8818 [523] = 1'h0;
+ \8818 [524] = 1'h0;
+ \8818 [525] = 1'h0;
+ \8818 [526] = 1'h0;
+ \8818 [527] = 1'h0;
+ \8818 [528] = 1'h0;
+ \8818 [529] = 1'h0;
+ \8818 [530] = 1'h0;
+ \8818 [531] = 1'h0;
+ \8818 [532] = 1'h0;
+ \8818 [533] = 1'h0;
+ \8818 [534] = 1'h0;
+ \8818 [535] = 1'h0;
+ \8818 [536] = 1'h0;
+ \8818 [537] = 1'h0;
+ \8818 [538] = 1'h0;
+ \8818 [539] = 1'h0;
+ \8818 [540] = 1'h0;
+ \8818 [541] = 1'h0;
+ \8818 [542] = 1'h0;
+ \8818 [543] = 1'h0;
+ \8818 [544] = 1'h0;
+ \8818 [545] = 1'h0;
+ \8818 [546] = 1'h0;
+ \8818 [547] = 1'h0;
+ \8818 [548] = 1'h0;
+ \8818 [549] = 1'h0;
+ \8818 [550] = 1'h0;
+ \8818 [551] = 1'h0;
+ \8818 [552] = 1'h0;
+ \8818 [553] = 1'h0;
+ \8818 [554] = 1'h0;
+ \8818 [555] = 1'h0;
+ \8818 [556] = 1'h0;
+ \8818 [557] = 1'h0;
+ \8818 [558] = 1'h0;
+ \8818 [559] = 1'h0;
+ \8818 [560] = 1'h0;
+ \8818 [561] = 1'h0;
+ \8818 [562] = 1'h0;
+ \8818 [563] = 1'h0;
+ \8818 [564] = 1'h0;
+ \8818 [565] = 1'h0;
+ \8818 [566] = 1'h0;
+ \8818 [567] = 1'h0;
+ \8818 [568] = 1'h0;
+ \8818 [569] = 1'h0;
+ \8818 [570] = 1'h0;
+ \8818 [571] = 1'h0;
+ \8818 [572] = 1'h0;
+ \8818 [573] = 1'h0;
+ \8818 [574] = 1'h0;
+ \8818 [575] = 1'h0;
+ \8818 [576] = 1'h0;
+ \8818 [577] = 1'h0;
+ \8818 [578] = 1'h0;
+ \8818 [579] = 1'h0;
+ \8818 [580] = 1'h0;
+ \8818 [581] = 1'h0;
+ \8818 [582] = 1'h0;
+ \8818 [583] = 1'h0;
+ \8818 [584] = 1'h0;
+ \8818 [585] = 1'h0;
+ \8818 [586] = 1'h0;
+ \8818 [587] = 1'h0;
+ \8818 [588] = 1'h0;
+ \8818 [589] = 1'h0;
+ \8818 [590] = 1'h0;
+ \8818 [591] = 1'h0;
+ \8818 [592] = 1'h0;
+ \8818 [593] = 1'h0;
+ \8818 [594] = 1'h0;
+ \8818 [595] = 1'h0;
+ \8818 [596] = 1'h0;
+ \8818 [597] = 1'h0;
+ \8818 [598] = 1'h0;
+ \8818 [599] = 1'h0;
+ \8818 [600] = 1'h0;
+ \8818 [601] = 1'h0;
+ \8818 [602] = 1'h0;
+ \8818 [603] = 1'h0;
+ \8818 [604] = 1'h0;
+ \8818 [605] = 1'h0;
+ \8818 [606] = 1'h0;
+ \8818 [607] = 1'h0;
+ \8818 [608] = 1'h0;
+ \8818 [609] = 1'h0;
+ \8818 [610] = 1'h0;
+ \8818 [611] = 1'h0;
+ \8818 [612] = 1'h0;
+ \8818 [613] = 1'h0;
+ \8818 [614] = 1'h0;
+ \8818 [615] = 1'h0;
+ \8818 [616] = 1'h0;
+ \8818 [617] = 1'h0;
+ \8818 [618] = 1'h0;
+ \8818 [619] = 1'h0;
+ \8818 [620] = 1'h0;
+ \8818 [621] = 1'h0;
+ \8818 [622] = 1'h0;
+ \8818 [623] = 1'h0;
+ \8818 [624] = 1'h0;
+ \8818 [625] = 1'h0;
+ \8818 [626] = 1'h0;
+ \8818 [627] = 1'h0;
+ \8818 [628] = 1'h0;
+ \8818 [629] = 1'h0;
+ \8818 [630] = 1'h0;
+ \8818 [631] = 1'h0;
+ \8818 [632] = 1'h0;
+ \8818 [633] = 1'h0;
+ \8818 [634] = 1'h0;
+ \8818 [635] = 1'h0;
+ \8818 [636] = 1'h0;
+ \8818 [637] = 1'h0;
+ \8818 [638] = 1'h0;
+ \8818 [639] = 1'h0;
+ \8818 [640] = 1'h0;
+ \8818 [641] = 1'h0;
+ \8818 [642] = 1'h0;
+ \8818 [643] = 1'h0;
+ \8818 [644] = 1'h0;
+ \8818 [645] = 1'h0;
+ \8818 [646] = 1'h0;
+ \8818 [647] = 1'h0;
+ \8818 [648] = 1'h0;
+ \8818 [649] = 1'h0;
+ \8818 [650] = 1'h0;
+ \8818 [651] = 1'h0;
+ \8818 [652] = 1'h0;
+ \8818 [653] = 1'h0;
+ \8818 [654] = 1'h0;
+ \8818 [655] = 1'h0;
+ \8818 [656] = 1'h0;
+ \8818 [657] = 1'h0;
+ \8818 [658] = 1'h0;
+ \8818 [659] = 1'h0;
+ \8818 [660] = 1'h0;
+ \8818 [661] = 1'h0;
+ \8818 [662] = 1'h0;
+ \8818 [663] = 1'h0;
+ \8818 [664] = 1'h0;
+ \8818 [665] = 1'h0;
+ \8818 [666] = 1'h0;
+ \8818 [667] = 1'h0;
+ \8818 [668] = 1'h0;
+ \8818 [669] = 1'h0;
+ \8818 [670] = 1'h0;
+ \8818 [671] = 1'h0;
+ \8818 [672] = 1'h0;
+ \8818 [673] = 1'h0;
+ \8818 [674] = 1'h0;
+ \8818 [675] = 1'h0;
+ \8818 [676] = 1'h0;
+ \8818 [677] = 1'h0;
+ \8818 [678] = 1'h0;
+ \8818 [679] = 1'h0;
+ \8818 [680] = 1'h0;
+ \8818 [681] = 1'h0;
+ \8818 [682] = 1'h0;
+ \8818 [683] = 1'h0;
+ \8818 [684] = 1'h0;
+ \8818 [685] = 1'h0;
+ \8818 [686] = 1'h0;
+ \8818 [687] = 1'h0;
+ \8818 [688] = 1'h0;
+ \8818 [689] = 1'h0;
+ \8818 [690] = 1'h0;
+ \8818 [691] = 1'h0;
+ \8818 [692] = 1'h0;
+ \8818 [693] = 1'h0;
+ \8818 [694] = 1'h0;
+ \8818 [695] = 1'h0;
+ \8818 [696] = 1'h0;
+ \8818 [697] = 1'h0;
+ \8818 [698] = 1'h0;
+ \8818 [699] = 1'h0;
+ \8818 [700] = 1'h0;
+ \8818 [701] = 1'h0;
+ \8818 [702] = 1'h0;
+ \8818 [703] = 1'h0;
+ \8818 [704] = 1'h0;
+ \8818 [705] = 1'h0;
+ \8818 [706] = 1'h0;
+ \8818 [707] = 1'h0;
+ \8818 [708] = 1'h0;
+ \8818 [709] = 1'h0;
+ \8818 [710] = 1'h0;
+ \8818 [711] = 1'h0;
+ \8818 [712] = 1'h0;
+ \8818 [713] = 1'h0;
+ \8818 [714] = 1'h0;
+ \8818 [715] = 1'h0;
+ \8818 [716] = 1'h0;
+ \8818 [717] = 1'h0;
+ \8818 [718] = 1'h0;
+ \8818 [719] = 1'h0;
+ \8818 [720] = 1'h0;
+ \8818 [721] = 1'h0;
+ \8818 [722] = 1'h0;
+ \8818 [723] = 1'h0;
+ \8818 [724] = 1'h0;
+ \8818 [725] = 1'h0;
+ \8818 [726] = 1'h0;
+ \8818 [727] = 1'h0;
+ \8818 [728] = 1'h0;
+ \8818 [729] = 1'h0;
+ \8818 [730] = 1'h0;
+ \8818 [731] = 1'h0;
+ \8818 [732] = 1'h0;
+ \8818 [733] = 1'h0;
+ \8818 [734] = 1'h0;
+ \8818 [735] = 1'h0;
+ \8818 [736] = 1'h0;
+ \8818 [737] = 1'h0;
+ \8818 [738] = 1'h0;
+ \8818 [739] = 1'h0;
+ \8818 [740] = 1'h0;
+ \8818 [741] = 1'h0;
+ \8818 [742] = 1'h0;
+ \8818 [743] = 1'h0;
+ \8818 [744] = 1'h0;
+ \8818 [745] = 1'h0;
+ \8818 [746] = 1'h0;
+ \8818 [747] = 1'h0;
+ \8818 [748] = 1'h0;
+ \8818 [749] = 1'h0;
+ \8818 [750] = 1'h0;
+ \8818 [751] = 1'h0;
+ \8818 [752] = 1'h0;
+ \8818 [753] = 1'h0;
+ \8818 [754] = 1'h0;
+ \8818 [755] = 1'h0;
+ \8818 [756] = 1'h0;
+ \8818 [757] = 1'h0;
+ \8818 [758] = 1'h0;
+ \8818 [759] = 1'h0;
+ \8818 [760] = 1'h0;
+ \8818 [761] = 1'h0;
+ \8818 [762] = 1'h0;
+ \8818 [763] = 1'h0;
+ \8818 [764] = 1'h0;
+ \8818 [765] = 1'h0;
+ \8818 [766] = 1'h0;
+ \8818 [767] = 1'h0;
+ \8818 [768] = 1'h0;
+ \8818 [769] = 1'h0;
+ \8818 [770] = 1'h0;
+ \8818 [771] = 1'h0;
+ \8818 [772] = 1'h0;
+ \8818 [773] = 1'h0;
+ \8818 [774] = 1'h0;
+ \8818 [775] = 1'h0;
+ \8818 [776] = 1'h0;
+ \8818 [777] = 1'h0;
+ \8818 [778] = 1'h0;
+ \8818 [779] = 1'h0;
+ \8818 [780] = 1'h0;
+ \8818 [781] = 1'h0;
+ \8818 [782] = 1'h0;
+ \8818 [783] = 1'h0;
+ \8818 [784] = 1'h0;
+ \8818 [785] = 1'h0;
+ \8818 [786] = 1'h0;
+ \8818 [787] = 1'h0;
+ \8818 [788] = 1'h0;
+ \8818 [789] = 1'h0;
+ \8818 [790] = 1'h0;
+ \8818 [791] = 1'h0;
+ \8818 [792] = 1'h0;
+ \8818 [793] = 1'h0;
+ \8818 [794] = 1'h0;
+ \8818 [795] = 1'h0;
+ \8818 [796] = 1'h0;
+ \8818 [797] = 1'h0;
+ \8818 [798] = 1'h0;
+ \8818 [799] = 1'h0;
+ \8818 [800] = 1'h0;
+ \8818 [801] = 1'h0;
+ \8818 [802] = 1'h0;
+ \8818 [803] = 1'h0;
+ \8818 [804] = 1'h0;
+ \8818 [805] = 1'h0;
+ \8818 [806] = 1'h0;
+ \8818 [807] = 1'h0;
+ \8818 [808] = 1'h0;
+ \8818 [809] = 1'h0;
+ \8818 [810] = 1'h0;
+ \8818 [811] = 1'h0;
+ \8818 [812] = 1'h0;
+ \8818 [813] = 1'h0;
+ \8818 [814] = 1'h0;
+ \8818 [815] = 1'h0;
+ \8818 [816] = 1'h0;
+ \8818 [817] = 1'h0;
+ \8818 [818] = 1'h0;
+ \8818 [819] = 1'h0;
+ \8818 [820] = 1'h0;
+ \8818 [821] = 1'h0;
+ \8818 [822] = 1'h0;
+ \8818 [823] = 1'h0;
+ \8818 [824] = 1'h0;
+ \8818 [825] = 1'h0;
+ \8818 [826] = 1'h0;
+ \8818 [827] = 1'h0;
+ \8818 [828] = 1'h0;
+ \8818 [829] = 1'h0;
+ \8818 [830] = 1'h0;
+ \8818 [831] = 1'h0;
+ \8818 [832] = 1'h0;
+ \8818 [833] = 1'h0;
+ \8818 [834] = 1'h0;
+ \8818 [835] = 1'h0;
+ \8818 [836] = 1'h0;
+ \8818 [837] = 1'h0;
+ \8818 [838] = 1'h0;
+ \8818 [839] = 1'h0;
+ \8818 [840] = 1'h0;
+ \8818 [841] = 1'h0;
+ \8818 [842] = 1'h0;
+ \8818 [843] = 1'h0;
+ \8818 [844] = 1'h0;
+ \8818 [845] = 1'h0;
+ \8818 [846] = 1'h0;
+ \8818 [847] = 1'h0;
+ \8818 [848] = 1'h0;
+ \8818 [849] = 1'h0;
+ \8818 [850] = 1'h0;
+ \8818 [851] = 1'h0;
+ \8818 [852] = 1'h0;
+ \8818 [853] = 1'h0;
+ \8818 [854] = 1'h0;
+ \8818 [855] = 1'h0;
+ \8818 [856] = 1'h0;
+ \8818 [857] = 1'h0;
+ \8818 [858] = 1'h0;
+ \8818 [859] = 1'h0;
+ \8818 [860] = 1'h0;
+ \8818 [861] = 1'h0;
+ \8818 [862] = 1'h0;
+ \8818 [863] = 1'h0;
+ \8818 [864] = 1'h0;
+ \8818 [865] = 1'h0;
+ \8818 [866] = 1'h0;
+ \8818 [867] = 1'h0;
+ \8818 [868] = 1'h0;
+ \8818 [869] = 1'h0;
+ \8818 [870] = 1'h0;
+ \8818 [871] = 1'h0;
+ \8818 [872] = 1'h0;
+ \8818 [873] = 1'h0;
+ \8818 [874] = 1'h0;
+ \8818 [875] = 1'h0;
+ \8818 [876] = 1'h0;
+ \8818 [877] = 1'h0;
+ \8818 [878] = 1'h0;
+ \8818 [879] = 1'h0;
+ \8818 [880] = 1'h0;
+ \8818 [881] = 1'h0;
+ \8818 [882] = 1'h0;
+ \8818 [883] = 1'h0;
+ \8818 [884] = 1'h0;
+ \8818 [885] = 1'h0;
+ \8818 [886] = 1'h0;
+ \8818 [887] = 1'h0;
+ \8818 [888] = 1'h0;
+ \8818 [889] = 1'h0;
+ \8818 [890] = 1'h0;
+ \8818 [891] = 1'h0;
+ \8818 [892] = 1'h0;
+ \8818 [893] = 1'h0;
+ \8818 [894] = 1'h0;
+ \8818 [895] = 1'h0;
+ \8818 [896] = 1'h0;
+ \8818 [897] = 1'h0;
+ \8818 [898] = 1'h0;
+ \8818 [899] = 1'h0;
+ \8818 [900] = 1'h0;
+ \8818 [901] = 1'h0;
+ \8818 [902] = 1'h0;
+ \8818 [903] = 1'h0;
+ \8818 [904] = 1'h0;
+ \8818 [905] = 1'h0;
+ \8818 [906] = 1'h0;
+ \8818 [907] = 1'h0;
+ \8818 [908] = 1'h0;
+ \8818 [909] = 1'h0;
+ \8818 [910] = 1'h0;
+ \8818 [911] = 1'h0;
+ \8818 [912] = 1'h0;
+ \8818 [913] = 1'h0;
+ \8818 [914] = 1'h0;
+ \8818 [915] = 1'h0;
+ \8818 [916] = 1'h0;
+ \8818 [917] = 1'h0;
+ \8818 [918] = 1'h0;
+ \8818 [919] = 1'h0;
+ \8818 [920] = 1'h0;
+ \8818 [921] = 1'h0;
+ \8818 [922] = 1'h0;
+ \8818 [923] = 1'h0;
+ \8818 [924] = 1'h0;
+ \8818 [925] = 1'h0;
+ \8818 [926] = 1'h0;
+ \8818 [927] = 1'h0;
+ \8818 [928] = 1'h1;
+ \8818 [929] = 1'h1;
+ \8818 [930] = 1'h1;
+ \8818 [931] = 1'h1;
+ \8818 [932] = 1'h1;
+ \8818 [933] = 1'h1;
+ \8818 [934] = 1'h1;
+ \8818 [935] = 1'h1;
+ \8818 [936] = 1'h1;
+ \8818 [937] = 1'h1;
+ \8818 [938] = 1'h1;
+ \8818 [939] = 1'h1;
+ \8818 [940] = 1'h1;
+ \8818 [941] = 1'h1;
+ \8818 [942] = 1'h1;
+ \8818 [943] = 1'h1;
+ \8818 [944] = 1'h1;
+ \8818 [945] = 1'h1;
+ \8818 [946] = 1'h1;
+ \8818 [947] = 1'h1;
+ \8818 [948] = 1'h1;
+ \8818 [949] = 1'h1;
+ \8818 [950] = 1'h1;
+ \8818 [951] = 1'h1;
+ \8818 [952] = 1'h1;
+ \8818 [953] = 1'h1;
+ \8818 [954] = 1'h1;
+ \8818 [955] = 1'h1;
+ \8818 [956] = 1'h1;
+ \8818 [957] = 1'h1;
+ \8818 [958] = 1'h1;
+ \8818 [959] = 1'h1;
+ \8818 [960] = 1'h0;
+ \8818 [961] = 1'h0;
+ \8818 [962] = 1'h0;
+ \8818 [963] = 1'h0;
+ \8818 [964] = 1'h0;
+ \8818 [965] = 1'h0;
+ \8818 [966] = 1'h0;
+ \8818 [967] = 1'h0;
+ \8818 [968] = 1'h0;
+ \8818 [969] = 1'h0;
+ \8818 [970] = 1'h0;
+ \8818 [971] = 1'h0;
+ \8818 [972] = 1'h0;
+ \8818 [973] = 1'h0;
+ \8818 [974] = 1'h0;
+ \8818 [975] = 1'h0;
+ \8818 [976] = 1'h0;
+ \8818 [977] = 1'h1;
+ \8818 [978] = 1'h1;
+ \8818 [979] = 1'h0;
+ \8818 [980] = 1'h0;
+ \8818 [981] = 1'h0;
+ \8818 [982] = 1'h1;
+ \8818 [983] = 1'h1;
+ \8818 [984] = 1'h1;
+ \8818 [985] = 1'h1;
+ \8818 [986] = 1'h0;
+ \8818 [987] = 1'h1;
+ \8818 [988] = 1'h0;
+ \8818 [989] = 1'h0;
+ \8818 [990] = 1'h1;
+ \8818 [991] = 1'h0;
+ \8818 [992] = 1'h0;
+ \8818 [993] = 1'h0;
+ \8818 [994] = 1'h0;
+ \8818 [995] = 1'h0;
+ \8818 [996] = 1'h0;
+ \8818 [997] = 1'h0;
+ \8818 [998] = 1'h0;
+ \8818 [999] = 1'h0;
+ \8818 [1000] = 1'h0;
+ \8818 [1001] = 1'h0;
+ \8818 [1002] = 1'h0;
+ \8818 [1003] = 1'h0;
+ \8818 [1004] = 1'h0;
+ \8818 [1005] = 1'h0;
+ \8818 [1006] = 1'h0;
+ \8818 [1007] = 1'h0;
+ \8818 [1008] = 1'h0;
+ \8818 [1009] = 1'h0;
+ \8818 [1010] = 1'h0;
+ \8818 [1011] = 1'h0;
+ \8818 [1012] = 1'h0;
+ \8818 [1013] = 1'h0;
+ \8818 [1014] = 1'h0;
+ \8818 [1015] = 1'h0;
+ \8818 [1016] = 1'h0;
+ \8818 [1017] = 1'h0;
+ \8818 [1018] = 1'h0;
+ \8818 [1019] = 1'h0;
+ \8818 [1020] = 1'h0;
+ \8818 [1021] = 1'h0;
+ \8818 [1022] = 1'h0;
+ \8818 [1023] = 1'h1;
+ end
+ assign _133_ = \8818 [_074_];
+ reg [40:0] \8820 [7:0];
+ initial begin
+ \8820 [0] = 41'h10000000079;
+ \8820 [1] = 41'h00000000000;
+ \8820 [2] = 41'h00000006bc5;
+ \8820 [3] = 41'h080002c6b1d;
+ \8820 [4] = 41'h00000000000;
+ \8820 [5] = 41'h00000000000;
+ \8820 [6] = 41'h04000044409;
+ \8820 [7] = 41'h00000600039;
+ end
+ assign _135_ = \8820 [_076_];
+ reg [40:0] \8822 [15:0];
+ initial begin
+ \8822 [0] = 41'h00000000000;
+ \8822 [1] = 41'h00000000000;
+ \8822 [2] = 41'h00000000000;
+ \8822 [3] = 41'h00000000000;
+ \8822 [4] = 41'h00000000000;
+ \8822 [5] = 41'h00000000000;
+ \8822 [6] = 41'h040000888d1;
+ \8822 [7] = 41'h040000888cd;
+ \8822 [8] = 41'h0400008d9c9;
+ \8822 [9] = 41'h0400008d9c9;
+ \8822 [10] = 41'h0400008d8c9;
+ \8822 [11] = 41'h0400008d8c9;
+ \8822 [12] = 41'h0400008d8d1;
+ \8822 [13] = 41'h0400008d8d1;
+ \8822 [14] = 41'h0400008d8cd;
+ \8822 [15] = 41'h0400008d8cd;
+ end
+ assign _137_ = \8822 [_086_];
+ reg [40:0] \8824 [3:0];
+ initial begin
+ \8824 [0] = 41'h00000000000;
+ \8824 [1] = 41'h00130044a7e;
+ \8824 [2] = 41'h00240044a7e;
+ \8824 [3] = 41'h00040044a7e;
+ end
+ assign _139_ = \8824 [_092_];
+ reg [40:0] \8826 [3:0];
+ initial begin
+ \8826 [0] = 41'h00000000000;
+ \8826 [1] = 41'h00000000000;
+ \8826 [2] = 41'h0024000ca82;
+ \8826 [3] = 41'h0004000ca82;
+ end
+ assign _141_ = \8826 [_095_];
+ assign _000_ = ~ stall_in;
+ assign _001_ = _000_ ? s : r;
+ assign _002_ = _000_ ? 1'h0 : s[0];
+ assign _003_ = _000_ ? si : ri;
+ assign _004_ = _110_ & r[0];
+ assign _005_ = _004_ & stall_in;
+ assign _006_ = ~ r[0];
+ assign _007_ = ~ stall_in;
+ assign _008_ = _006_ | _007_;
+ assign _009_ = _008_ ? { _101_, _100_, _099_, _098_, f_in[98:3], f_in[1], _110_ } : r;
+ assign _010_ = _008_ ? { _105_, _111_ } : ri;
+ assign _011_ = s[0] ? _001_ : _009_;
+ assign _012_ = s[0] ? _002_ : _005_;
+ assign _013_ = s[0] ? s[153:1] : { _101_, _100_, _099_, _098_, f_in[98:3], f_in[1] };
+ assign _014_ = s[0] ? _003_ : _010_;
+ assign _015_ = s[0] ? si : { _105_, _111_ };
+ assign _016_ = flush_in ? 1'h0 : _011_[0];
+ assign _017_ = flush_in ? r[153:1] : _011_[153:1];
+ assign _018_ = flush_in ? 1'h0 : _012_;
+ assign _019_ = flush_in ? s[153:1] : _013_;
+ assign _020_ = flush_in ? ri : _014_;
+ assign _021_ = flush_in ? si : _015_;
+ assign _022_ = rst ? 154'h000000000000000000000000000000000000000 : { _017_, _016_ };
+ assign _023_ = rst ? 154'h000000000000000000000000000000000000000 : { _019_, _018_ };
+ assign _024_ = rst ? 44'h00000000000 : _020_;
+ assign _025_ = rst ? 44'h00000000000 : _021_;
+ always @(posedge clk)
+ r <= _022_;
+ always @(posedge clk)
+ s <= _023_;
+ always @(posedge clk)
+ ri <= _024_;
+ always @(posedge clk)
+ si <= _025_;
+ assign _026_ = 6'h3f - f_in[98:93];
+ assign _027_ = 11'h7ff - { f_in[72:67], f_in[77:73] };
+ assign _028_ = ~ _127_;
+ assign _029_ = 6'h3f - f_in[72:67];
+ assign _030_ = { 25'h0000000, f_in[98:93] } == 31'h00000004;
+ assign _031_ = 10'h3ff - f_in[77:68];
+ assign _032_ = { f_in[82:78], f_in[87:83] } == 10'h008;
+ assign _033_ = { f_in[82:78], f_in[87:83] } == 10'h009;
+ assign _034_ = { f_in[82:78], f_in[87:83] } == 10'h01a;
+ assign _035_ = { f_in[82:78], f_in[87:83] } == 10'h01b;
+ assign _036_ = { f_in[82:78], f_in[87:83] } == 10'h13a;
+ assign _037_ = { f_in[82:78], f_in[87:83] } == 10'h13b;
+ assign _038_ = { f_in[82:78], f_in[87:83] } == 10'h110;
+ assign _039_ = { f_in[82:78], f_in[87:83] } == 10'h111;
+ assign _040_ = { f_in[82:78], f_in[87:83] } == 10'h112;
+ assign _041_ = { f_in[82:78], f_in[87:83] } == 10'h113;
+ assign _042_ = { f_in[82:78], f_in[87:83] } == 10'h103;
+ assign _043_ = _041_ | _042_;
+ assign _044_ = { f_in[82:78], f_in[87:83] } == 10'h130;
+ assign _045_ = { f_in[82:78], f_in[87:83] } == 10'h131;
+ assign _046_ = { f_in[82:78], f_in[87:83] } == 10'h001;
+ assign _047_ = { f_in[82:78], f_in[87:83] } == 10'h32f;
+ function [0:0] \8524 ;
+ input [0:0] a;
+ input [13:0] b;
+ input [13:0] s;
+ (* parallel_case *)
+ casez (s)
+ 14'b?????????????1:
+ \8524 = b[0:0];
+ 14'b????????????1?:
+ \8524 = b[1:1];
+ 14'b???????????1??:
+ \8524 = b[2:2];
+ 14'b??????????1???:
+ \8524 = b[3:3];
+ 14'b?????????1????:
+ \8524 = b[4:4];
+ 14'b????????1?????:
+ \8524 = b[5:5];
+ 14'b???????1??????:
+ \8524 = b[6:6];
+ 14'b??????1???????:
+ \8524 = b[7:7];
+ 14'b?????1????????:
+ \8524 = b[8:8];
+ 14'b????1?????????:
+ \8524 = b[9:9];
+ 14'b???1??????????:
+ \8524 = b[10:10];
+ 14'b??1???????????:
+ \8524 = b[11:11];
+ 14'b?1????????????:
+ \8524 = b[12:12];
+ 14'b1?????????????:
+ \8524 = b[13:13];
+ default:
+ \8524 = a;
+ endcase
+ endfunction
+ assign _048_ = \8524 (1'h0, 14'h3fff, { _047_, _046_, _045_, _044_, _043_, _040_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _032_ });
+ function [6:0] \8530 ;
+ input [6:0] a;
+ input [97:0] b;
+ input [13:0] s;
+ (* parallel_case *)
+ casez (s)
+ 14'b?????????????1:
+ \8530 = b[6:0];
+ 14'b????????????1?:
+ \8530 = b[13:7];
+ 14'b???????????1??:
+ \8530 = b[20:14];
+ 14'b??????????1???:
+ \8530 = b[27:21];
+ 14'b?????????1????:
+ \8530 = b[34:28];
+ 14'b????????1?????:
+ \8530 = b[41:35];
+ 14'b???????1??????:
+ \8530 = b[48:42];
+ 14'b??????1???????:
+ \8530 = b[55:49];
+ 14'b?????1????????:
+ \8530 = b[62:56];
+ 14'b????1?????????:
+ \8530 = b[69:63];
+ 14'b???1??????????:
+ \8530 = b[76:70];
+ 14'b??1???????????:
+ \8530 = b[83:77];
+ 14'b?1????????????:
+ \8530 = b[90:84];
+ 14'b1?????????????:
+ \8530 = b[97:91];
+ default:
+ \8530 = a;
+ endcase
+ endfunction
+ assign _049_ = \8530 (7'h00, 98'hxxxxxxxxxxxxxxxxxxxxxxxxx, { _047_, _046_, _045_, _044_, _043_, _040_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _032_ });
+ function [4:0] \8546 ;
+ input [4:0] a;
+ input [69:0] b;
+ input [13:0] s;
+ (* parallel_case *)
+ casez (s)
+ 14'b?????????????1:
+ \8546 = b[4:0];
+ 14'b????????????1?:
+ \8546 = b[9:5];
+ 14'b???????????1??:
+ \8546 = b[14:10];
+ 14'b??????????1???:
+ \8546 = b[19:15];
+ 14'b?????????1????:
+ \8546 = b[24:20];
+ 14'b????????1?????:
+ \8546 = b[29:25];
+ 14'b???????1??????:
+ \8546 = b[34:30];
+ 14'b??????1???????:
+ \8546 = b[39:35];
+ 14'b?????1????????:
+ \8546 = b[44:40];
+ 14'b????1?????????:
+ \8546 = b[49:45];
+ 14'b???1??????????:
+ \8546 = b[54:50];
+ 14'b??1???????????:
+ \8546 = b[59:55];
+ 14'b?1????????????:
+ \8546 = b[64:60];
+ 14'b1?????????????:
+ \8546 = b[69:65];
+ default:
+ \8546 = a;
+ endcase
+ endfunction
+ assign _050_ = \8546 (5'h00, 70'h1ac5a928398a418820, { _047_, _046_, _045_, _044_, _043_, _040_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _032_ });
+ assign _051_ = _048_ ? _050_ : 5'hxx;
+ assign _052_ = _048_ ? { 2'h1, _051_ } : _049_;
+ assign _053_ = f_in[77:68] & 10'h37f;
+ assign _054_ = _053_ == 10'h153;
+ assign _055_ = ~ _052_[5];
+ assign _056_ = { f_in[82:78], f_in[87:83] } == 10'h013;
+ assign _057_ = { f_in[82:78], f_in[87:83] } == 10'h012;
+ assign _058_ = _056_ | _057_;
+ assign _059_ = { f_in[82:78], f_in[87:83] } == 10'h030;
+ assign _060_ = _058_ | _059_;
+ assign _061_ = { f_in[82:78], f_in[87:83] } == 10'h2d0;
+ assign _062_ = _060_ | _061_;
+ function [1:0] \8589 ;
+ input [1:0] a;
+ input [1:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \8589 = b[1:0];
+ default:
+ \8589 = a;
+ endcase
+ endfunction
+ assign _063_ = \8589 (2'h0, 2'h2, _062_);
+ function [0:0] \8591 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \8591 = b[0:0];
+ default:
+ \8591 = a;
+ endcase
+ endfunction
+ assign _064_ = \8591 (1'h0, 1'h1, _062_);
+ assign _065_ = _055_ ? _063_ : 2'h0;
+ assign _066_ = _055_ ? { 1'h1, _064_ } : 2'h0;
+ assign _067_ = _054_ ? _065_ : 2'h0;
+ assign _068_ = _054_ ? _066_ : 2'h0;
+ assign _069_ = { 25'h0000000, f_in[98:93] } == 31'h0000001f;
+ assign _070_ = ~ f_in[90];
+ assign _071_ = _070_ ? 7'h21 : 7'h00;
+ assign _072_ = { 25'h0000000, f_in[98:93] } == 31'h00000010;
+ assign _073_ = { 25'h0000000, f_in[98:93] } == 31'h00000012;
+ assign _074_ = 10'h3ff - { f_in[72:68], f_in[77:73] };
+ assign _075_ = ~ _133_;
+ assign _076_ = 3'h7 - { f_in[72], f_in[70:69] };
+ assign _077_ = ~ f_in[69];
+ assign _078_ = ~ f_in[90];
+ assign _079_ = _078_ ? 7'h21 : 7'h00;
+ assign _080_ = ~ f_in[77];
+ assign _081_ = ~ f_in[73];
+ assign _082_ = _081_ ? 7'h21 : 7'h2d;
+ assign _083_ = _080_ ? 7'h20 : _082_;
+ assign _084_ = _077_ ? { _083_, _079_ } : 14'h1123;
+ assign _085_ = { 25'h0000000, f_in[98:93] } == 31'h00000013;
+ assign _086_ = 4'hf - f_in[71:68];
+ assign _087_ = { 25'h0000000, f_in[98:93] } == 31'h0000001e;
+ assign _088_ = f_in[98:67] & 32'd4294967295;
+ assign _089_ = _088_ == 32'd1610612736;
+ assign _090_ = _089_ ? 42'h0000000000b : 42'h00000000000;
+ assign _091_ = { 25'h0000000, f_in[98:93] } == 31'h00000030;
+ assign _092_ = 2'h3 - f_in[68:67];
+ assign _093_ = { 25'h0000000, f_in[98:93] } == 31'h0000003a;
+ assign _094_ = { 25'h0000000, f_in[98:93] } == 31'h0000003b;
+ assign _095_ = 2'h3 - f_in[68:67];
+ assign _096_ = { 25'h0000000, f_in[98:93] } == 31'h0000003e;
+ assign _097_ = { 25'h0000000, f_in[98:93] } == 31'h0000003f;
+ function [6:0] \8714 ;
+ input [6:0] a;
+ input [76:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8714 = b[6:0];
+ 11'b?????????1?:
+ \8714 = b[13:7];
+ 11'b????????1??:
+ \8714 = b[20:14];
+ 11'b???????1???:
+ \8714 = b[27:21];
+ 11'b??????1????:
+ \8714 = b[34:28];
+ 11'b?????1?????:
+ \8714 = b[41:35];
+ 11'b????1??????:
+ \8714 = b[48:42];
+ 11'b???1???????:
+ \8714 = b[55:49];
+ 11'b??1????????:
+ \8714 = b[62:56];
+ 11'b?1?????????:
+ \8714 = b[69:63];
+ 11'b1??????????:
+ \8714 = b[76:70];
+ default:
+ \8714 = a;
+ endcase
+ endfunction
+ assign _098_ = \8714 (7'h00, { 42'h00000000000, _084_[6:0], 7'h00, _071_, _052_, 7'h00 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [6:0] \8717 ;
+ input [6:0] a;
+ input [76:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8717 = b[6:0];
+ 11'b?????????1?:
+ \8717 = b[13:7];
+ 11'b????????1??:
+ \8717 = b[20:14];
+ 11'b???????1???:
+ \8717 = b[27:21];
+ 11'b??????1????:
+ \8717 = b[34:28];
+ 11'b?????1?????:
+ \8717 = b[41:35];
+ 11'b????1??????:
+ \8717 = b[48:42];
+ 11'b???1???????:
+ \8717 = b[55:49];
+ 11'b??1????????:
+ \8717 = b[62:56];
+ 11'b?1?????????:
+ \8717 = b[69:63];
+ 11'b1??????????:
+ \8717 = b[76:70];
+ default:
+ \8717 = a;
+ endcase
+ endfunction
+ assign _099_ = \8717 (7'h00, { 42'h00000000000, _084_[13:7], 28'h0000000 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [40:0] \8718 ;
+ input [40:0] a;
+ input [450:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8718 = b[40:0];
+ 11'b?????????1?:
+ \8718 = b[81:41];
+ 11'b????????1??:
+ \8718 = b[122:82];
+ 11'b???????1???:
+ \8718 = b[163:123];
+ 11'b??????1????:
+ \8718 = b[204:164];
+ 11'b?????1?????:
+ \8718 = b[245:205];
+ 11'b????1??????:
+ \8718 = b[286:246];
+ 11'b???1???????:
+ \8718 = b[327:287];
+ 11'b??1????????:
+ \8718 = b[368:328];
+ 11'b?1?????????:
+ \8718 = b[409:369];
+ 11'b1??????????:
+ \8718 = b[450:410];
+ default:
+ \8718 = a;
+ endcase
+ endfunction
+ assign _100_ = \8718 (_125_, { _125_, _141_, _125_, _139_, _125_, _137_, _135_, _125_, _125_, _131_, _129_ }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [0:0] \8719 ;
+ input [0:0] a;
+ input [10:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8719 = b[0:0];
+ 11'b?????????1?:
+ \8719 = b[1:1];
+ 11'b????????1??:
+ \8719 = b[2:2];
+ 11'b???????1???:
+ \8719 = b[3:3];
+ 11'b??????1????:
+ \8719 = b[4:4];
+ 11'b?????1?????:
+ \8719 = b[5:5];
+ 11'b????1??????:
+ \8719 = b[6:6];
+ 11'b???1???????:
+ \8719 = b[7:7];
+ 11'b??1????????:
+ \8719 = b[8:8];
+ 11'b?1?????????:
+ \8719 = b[9:9];
+ 11'b1??????????:
+ \8719 = b[10:10];
+ default:
+ \8719 = a;
+ endcase
+ endfunction
+ assign _101_ = \8719 (1'h0, { 8'h01, f_in[82], 2'h0 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [0:0] \8723 ;
+ input [0:0] a;
+ input [10:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8723 = b[0:0];
+ 11'b?????????1?:
+ \8723 = b[1:1];
+ 11'b????????1??:
+ \8723 = b[2:2];
+ 11'b???????1???:
+ \8723 = b[3:3];
+ 11'b??????1????:
+ \8723 = b[4:4];
+ 11'b?????1?????:
+ \8723 = b[5:5];
+ 11'b????1??????:
+ \8723 = b[6:6];
+ 11'b???1???????:
+ \8723 = b[7:7];
+ 11'b??1????????:
+ \8723 = b[8:8];
+ 11'b?1?????????:
+ \8723 = b[9:9];
+ 11'b1??????????:
+ \8723 = b[10:10];
+ default:
+ \8723 = a;
+ endcase
+ endfunction
+ assign _102_ = \8723 (1'h0, { 4'h0, _090_[0], 1'h0, _075_, 3'h0, _028_ }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [1:0] \8726 ;
+ input [1:0] a;
+ input [21:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8726 = b[1:0];
+ 11'b?????????1?:
+ \8726 = b[3:2];
+ 11'b????????1??:
+ \8726 = b[5:4];
+ 11'b???????1???:
+ \8726 = b[7:6];
+ 11'b??????1????:
+ \8726 = b[9:8];
+ 11'b?????1?????:
+ \8726 = b[11:10];
+ 11'b????1??????:
+ \8726 = b[13:12];
+ 11'b???1???????:
+ \8726 = b[15:14];
+ 11'b??1????????:
+ \8726 = b[17:16];
+ 11'b?1?????????:
+ \8726 = b[19:18];
+ 11'b1??????????:
+ \8726 = b[21:20];
+ default:
+ \8726 = a;
+ endcase
+ endfunction
+ assign _103_ = \8726 (2'h0, { 8'h00, _090_[2:1], 8'h00, _067_, 2'h0 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [38:0] \8729 ;
+ input [38:0] a;
+ input [428:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8729 = b[38:0];
+ 11'b?????????1?:
+ \8729 = b[77:39];
+ 11'b????????1??:
+ \8729 = b[116:78];
+ 11'b???????1???:
+ \8729 = b[155:117];
+ 11'b??????1????:
+ \8729 = b[194:156];
+ 11'b?????1?????:
+ \8729 = b[233:195];
+ 11'b????1??????:
+ \8729 = b[272:234];
+ 11'b???1???????:
+ \8729 = b[311:273];
+ 11'b??1????????:
+ \8729 = b[350:312];
+ 11'b?1?????????:
+ \8729 = b[389:351];
+ 11'b1??????????:
+ \8729 = b[428:390];
+ default:
+ \8729 = a;
+ endcase
+ endfunction
+ assign _104_ = \8729 (39'h0000000000, { 156'h000000000000000000000000000000000000000, _090_[41:3], 234'h00000000000000000000000000000000000000000000000000000000000 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [1:0] \8731 ;
+ input [1:0] a;
+ input [21:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8731 = b[1:0];
+ 11'b?????????1?:
+ \8731 = b[3:2];
+ 11'b????????1??:
+ \8731 = b[5:4];
+ 11'b???????1???:
+ \8731 = b[7:6];
+ 11'b??????1????:
+ \8731 = b[9:8];
+ 11'b?????1?????:
+ \8731 = b[11:10];
+ 11'b????1??????:
+ \8731 = b[13:12];
+ 11'b???1???????:
+ \8731 = b[15:14];
+ 11'b??1????????:
+ \8731 = b[17:16];
+ 11'b?1?????????:
+ \8731 = b[19:18];
+ 11'b1??????????:
+ \8731 = b[21:20];
+ default:
+ \8731 = a;
+ endcase
+ endfunction
+ assign _105_ = \8731 (2'h0, { 18'h00000, _068_, 2'h0 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ function [23:0] \8740 ;
+ input [23:0] a;
+ input [263:0] b;
+ input [10:0] s;
+ (* parallel_case *)
+ casez (s)
+ 11'b??????????1:
+ \8740 = b[23:0];
+ 11'b?????????1?:
+ \8740 = b[47:24];
+ 11'b????????1??:
+ \8740 = b[71:48];
+ 11'b???????1???:
+ \8740 = b[95:72];
+ 11'b??????1????:
+ \8740 = b[119:96];
+ 11'b?????1?????:
+ \8740 = b[143:120];
+ 11'b????1??????:
+ \8740 = b[167:144];
+ 11'b???1???????:
+ \8740 = b[191:168];
+ 11'b??1????????:
+ \8740 = b[215:192];
+ 11'b?1?????????:
+ \8740 = b[239:216];
+ 11'b1??????????:
+ \8740 = b[263:240];
+ default:
+ \8740 = a;
+ endcase
+ endfunction
+ assign _106_ = \8740 (24'h000000, { 168'h000000000000000000000000000000000000000000, f_in[92:69], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82:69], 48'h000000000000 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+ assign _107_ = ri[8:3] == 6'h3f;
+ assign _108_ = ri[0] & _107_;
+ assign _109_ = _108_ ? 1'h0 : 1'h1;
+ assign _110_ = f_in[2] ? _109_ : f_in[0];
+ assign _111_ = f_in[2] ? 42'h000000001fd : { _104_, _103_, _102_ };
+ assign _112_ = f_in[68] ? 62'h0000000000000000 : f_in[66:5];
+ assign _113_ = _112_ + { _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_ };
+ assign _114_ = _101_ & f_in[0];
+ assign _115_ = ~ flush_in;
+ assign _116_ = _114_ & _115_;
+ assign _117_ = ~ s[0];
+ assign _118_ = _116_ & _117_;
+ assign _119_ = ri[42] ? ri[2:1] : r[113:112];
+ assign _120_ = ri[0] ? ri[2:1] : _119_;
+ assign _121_ = ri[0] ? ri[41] : r[152];
+ assign _122_ = ri[43] ? 1'h1 : _121_;
+ assign _123_ = ri[0] ? ri[40:3] : r[151:114];
+ assign busy_out = s[0];
+ assign flush_out = _118_;
+ assign f_out = { _113_, 2'h0, _118_ };
+ assign d_out = { r[153], _122_, _123_, _120_, r[111:0] };
+ assign log_out = 13'hzzzz;
+endmodule
+
+module decode2_0_0e356ba505631fbf715758bed27d503f8b260e3a(clk, rst, complete_in, busy_in, flush_in, d_in, r_in, c_in, stall_out, stopped_out, e_out, r_out, c_out, log_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire [379:0] _05_;
+ wire _06_;
+ wire [6:0] _07_;
+ wire _08_;
+ wire _09_;
+ wire [6:0] _10_;
+ wire _11_;
+ wire [6:0] _12_;
+ wire _13_;
+ wire _14_;
+ wire [6:0] _15_;
+ wire _16_;
+ wire [6:0] _17_;
+ wire _18_;
+ wire _19_;
+ wire [6:0] _20_;
+ wire _21_;
+ wire _22_;
+ wire [6:0] _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire [71:0] _31_;
+ wire [71:0] _32_;
+ wire [71:0] _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire [71:0] _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire [71:0] _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire [7:0] _61_;
+ wire _62_;
+ wire _63_;
+ wire _64_;
+ wire _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ wire [3:0] _70_;
+ wire _71_;
+ wire _72_;
+ wire _73_;
+ wire _74_;
+ wire _75_;
+ wire _76_;
+ wire _77_;
+ wire _78_;
+ wire _79_;
+ wire _80_;
+ wire _81_;
+ wire _82_;
+ wire _83_;
+ wire _84_;
+ wire _85_;
+ wire _86_;
+ wire _87_;
+ wire _88_;
+ wire _89_;
+ wire _90_;
+ wire _91_;
+ input busy_in;
+ input [36:0] c_in;
+ output c_out;
+ input clk;
+ input complete_in;
+ wire control_valid_out;
+ wire cr_bypass;
+ wire cr_bypass_avail;
+ wire cr_write_valid;
+ input [153:0] d_in;
+ wire deferred;
+ output [379:0] e_out;
+ input flush_in;
+ wire gpr_a_bypass;
+ wire gpr_b_bypass;
+ wire gpr_bypassable;
+ wire gpr_c_bypass;
+ output [9:0] log_out;
+ reg [379:0] r;
+ input [191:0] r_in;
+ output [23:0] r_out;
+ wire [379:0] rin;
+ input rst;
+ output stall_out;
+ output stopped_out;
+ wire [6:0] update_gpr_write_reg;
+ wire update_gpr_write_valid;
+ assign deferred = r[0] & busy_in;
+ assign _02_ = rst | flush_in;
+ assign _03_ = ~ deferred;
+ assign _04_ = _02_ | _03_;
+ assign _05_ = _04_ ? rin : r;
+ always @(posedge clk)
+ r <= _05_;
+ assign _06_ = d_in[122:120] == 3'h3;
+ assign _07_ = _06_ ? d_in[104:98] : _10_;
+ assign _08_ = d_in[122:120] == 3'h5;
+ assign _09_ = _08_ & 1'h0;
+ assign _10_ = _09_ ? { 2'h2, d_in[86:82] } : { 2'h0, d_in[86:82] };
+ assign _11_ = d_in[126:123] == 4'hd;
+ assign _12_ = _11_ ? d_in[111:105] : _15_;
+ assign _13_ = d_in[126:123] == 4'he;
+ assign _14_ = _13_ & 1'h0;
+ assign _15_ = _14_ ? { 2'h2, d_in[81:77] } : { 2'h0, d_in[81:77] };
+ assign _16_ = d_in[129:127] == 3'h2;
+ assign _17_ = _16_ ? { 2'h0, d_in[76:72] } : _20_;
+ assign _18_ = d_in[129:127] == 3'h3;
+ assign _19_ = _18_ & 1'h0;
+ assign _20_ = _19_ ? { 2'h2, d_in[76:72] } : _23_;
+ assign _21_ = d_in[129:127] == 3'h4;
+ assign _22_ = _21_ & 1'h0;
+ assign _23_ = _22_ ? { 2'h2, d_in[91:87] } : { 2'h0, d_in[91:87] };
+ assign _24_ = d_in[122:120] == 3'h1;
+ assign _25_ = d_in[122:120] == 3'h2;
+ assign _26_ = d_in[86:82] != 5'h00;
+ assign _27_ = _25_ & _26_;
+ assign _28_ = _24_ | _27_;
+ assign _29_ = d_in[122:120] == 3'h3;
+ assign _30_ = d_in[122:120] == 3'h4;
+ assign _31_ = _30_ ? { d_in[65:2], 8'h00 } : 72'h000000000000000000;
+ assign _32_ = _29_ ? { r_in[63:0], d_in[104:98], d_in[103] } : _31_;
+ assign _33_ = _28_ ? { r_in[63:0], 2'h0, d_in[86:82], 1'h1 } : _32_;
+ assign _34_ = d_in[126:123] == 4'h1;
+ assign _35_ = d_in[126:123] == 4'he;
+ assign _36_ = d_in[126:123] == 4'h2;
+ assign _37_ = d_in[126:123] == 4'h3;
+ assign _38_ = d_in[126:123] == 4'h4;
+ assign _39_ = d_in[126:123] == 4'h5;
+ assign _40_ = d_in[126:123] == 4'h6;
+ assign _41_ = d_in[126:123] == 4'h7;
+ assign _42_ = d_in[126:123] == 4'h9;
+ assign _43_ = d_in[126:123] == 4'h8;
+ assign _44_ = d_in[126:123] == 4'ha;
+ assign _45_ = d_in[126:123] == 4'hb;
+ assign _46_ = d_in[126:123] == 4'hc;
+ assign _47_ = d_in[126:123] == 4'hd;
+ assign _48_ = d_in[126:123] == 4'h0;
+ function [71:0] \9268 ;
+ input [71:0] a;
+ input [1079:0] b;
+ input [14:0] s;
+ (* parallel_case *)
+ casez (s)
+ 15'b??????????????1:
+ \9268 = b[71:0];
+ 15'b?????????????1?:
+ \9268 = b[143:72];
+ 15'b????????????1??:
+ \9268 = b[215:144];
+ 15'b???????????1???:
+ \9268 = b[287:216];
+ 15'b??????????1????:
+ \9268 = b[359:288];
+ 15'b?????????1?????:
+ \9268 = b[431:360];
+ 15'b????????1??????:
+ \9268 = b[503:432];
+ 15'b???????1???????:
+ \9268 = b[575:504];
+ 15'b??????1????????:
+ \9268 = b[647:576];
+ 15'b?????1?????????:
+ \9268 = b[719:648];
+ 15'b????1??????????:
+ \9268 = b[791:720];
+ 15'b???1???????????:
+ \9268 = b[863:792];
+ 15'b??1????????????:
+ \9268 = b[935:864];
+ 15'b?1?????????????:
+ \9268 = b[1007:936];
+ 15'b1??????????????:
+ \9268 = b[1079:1008];
+ default:
+ \9268 = a;
+ endcase
+ endfunction
+ assign _49_ = \9268 (72'hxxxxxxxxxxxxxxxxxx, { 72'h000000000000000000, r_in[127:64], d_in[111:105], d_in[110], 59'h000000000000000, d_in[81:77], 66'h00000000000000000, d_in[67], d_in[81:77], 80'h00ffffffffffffffff00, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:72], d_in[86:82], d_in[66], 24'h000400, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 10'h000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 10'h000, d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91:68], 42'h00000000000, d_in[81:66], 24'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 24'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 56'h00000000000000, d_in[81:66], 80'h00000000000000000000, r_in[127:64], 2'h0, d_in[81:77], 1'h1 }, { _48_, _47_, _46_, _45_, _44_, _43_, _42_, _41_, _40_, _39_, _38_, _37_, _36_, _35_, _34_ });
+ assign _50_ = d_in[129:127] == 3'h1;
+ assign _51_ = d_in[129:127] == 3'h2;
+ assign _52_ = d_in[129:127] == 3'h4;
+ assign _53_ = d_in[129:127] == 3'h3;
+ assign _54_ = d_in[129:127] == 3'h0;
+ function [71:0] \9324 ;
+ input [71:0] a;
+ input [359:0] b;
+ input [4:0] s;
+ (* parallel_case *)
+ casez (s)
+ 5'b????1:
+ \9324 = b[71:0];
+ 5'b???1?:
+ \9324 = b[143:72];
+ 5'b??1??:
+ \9324 = b[215:144];
+ 5'b?1???:
+ \9324 = b[287:216];
+ 5'b1????:
+ \9324 = b[359:288];
+ default:
+ \9324 = a;
+ endcase
+ endfunction
+ assign _55_ = \9324 (72'hxxxxxxxxxxxxxxxxxx, { 216'h000000000000000000000000000000000000000000000000000000, r_in[191:128], 2'h0, d_in[76:72], 1'h1, r_in[191:128], 2'h0, d_in[91:87], 1'h1 }, { _54_, _53_, _52_, _51_, _50_ });
+ assign _56_ = d_in[132:130] == 3'h1;
+ assign _57_ = d_in[132:130] == 3'h2;
+ assign _58_ = d_in[132:130] == 3'h4;
+ assign _59_ = d_in[132:130] == 3'h3;
+ assign _60_ = d_in[132:130] == 3'h0;
+ function [7:0] \9385 ;
+ input [7:0] a;
+ input [39:0] b;
+ input [4:0] s;
+ (* parallel_case *)
+ casez (s)
+ 5'b????1:
+ \9385 = b[7:0];
+ 5'b???1?:
+ \9385 = b[15:8];
+ 5'b??1??:
+ \9385 = b[23:16];
+ 5'b?1???:
+ \9385 = b[31:24];
+ 5'b1????:
+ \9385 = b[39:32];
+ default:
+ \9385 = a;
+ endcase
+ endfunction
+ assign _61_ = \9385 (8'hxx, { 8'h00, d_in[104:98], d_in[103], 10'h000, d_in[86:82], 3'h4, d_in[91:87], 1'h1 }, { _60_, _59_, _58_, _57_, _56_ });
+ assign _62_ = _33_[0] & d_in[0];
+ assign _63_ = _49_[0] & d_in[0];
+ assign _64_ = _55_[0] & d_in[0];
+ assign _65_ = d_in[142:140] == 3'h1;
+ assign _66_ = d_in[142:140] == 3'h2;
+ assign _67_ = d_in[142:140] == 3'h3;
+ assign _68_ = d_in[142:140] == 3'h4;
+ assign _69_ = d_in[142:140] == 3'h0;
+ function [3:0] \9414 ;
+ input [3:0] a;
+ input [19:0] b;
+ input [4:0] s;
+ (* parallel_case *)
+ casez (s)
+ 5'b????1:
+ \9414 = b[3:0];
+ 5'b???1?:
+ \9414 = b[7:4];
+ 5'b??1??:
+ \9414 = b[11:8];
+ 5'b?1???:
+ \9414 = b[15:12];
+ 5'b1????:
+ \9414 = b[19:16];
+ default:
+ \9414 = a;
+ endcase
+ endfunction
+ assign _70_ = \9414 (4'hx, 20'h08421, { _69_, _68_, _67_, _66_, _65_ });
+ assign _71_ = d_in[150:149] == 2'h2;
+ assign _72_ = d_in[150:149] == 2'h1;
+ assign _73_ = d_in[150:149] == 2'h0;
+ function [0:0] \9463 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \9463 = b[0:0];
+ 3'b?1?:
+ \9463 = b[1:1];
+ 3'b1??:
+ \9463 = b[2:2];
+ default:
+ \9463 = a;
+ endcase
+ endfunction
+ assign _74_ = \9463 (1'hx, { 2'h1, d_in[66] }, { _73_, _72_, _71_ });
+ assign _75_ = d_in[119:114] == 6'h2d;
+ assign _76_ = d_in[119:114] == 6'h2c;
+ assign _77_ = _75_ | _76_;
+ assign _78_ = ~ _77_;
+ assign _79_ = d_in[150:149] == 2'h2;
+ function [0:0] \9493 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \9493 = b[0:0];
+ default:
+ \9493 = a;
+ endcase
+ endfunction
+ assign _80_ = \9493 (1'h0, d_in[76], _79_);
+ assign _81_ = _78_ ? _80_ : 1'h0;
+ assign _82_ = d_in[151] ? d_in[66] : 1'h0;
+ assign _83_ = d_in[113:112] == 2'h1;
+ assign _84_ = 1'h1 & _83_;
+ assign gpr_bypassable = _84_ ? 1'h1 : 1'h0;
+ assign update_gpr_write_valid = _82_ ? 1'h1 : d_in[145];
+ assign update_gpr_write_reg = _82_ ? 7'h20 : _33_[7:1];
+ assign _85_ = d_in[150:149] == 2'h2;
+ assign _86_ = d_in[150:149] == 2'h1;
+ assign _87_ = d_in[150:149] == 2'h0;
+ function [0:0] \9604 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \9604 = b[0:0];
+ 3'b?1?:
+ \9604 = b[1:1];
+ 3'b1??:
+ \9604 = b[2:2];
+ default:
+ \9604 = a;
+ endcase
+ endfunction
+ assign _88_ = \9604 (1'hx, { 2'h1, d_in[66] }, { _87_, _86_, _85_ });
+ assign cr_write_valid = d_in[134] | _88_;
+ assign _89_ = d_in[113:112] == 2'h1;
+ assign _90_ = 1'h1 & _89_;
+ assign cr_bypass_avail = _90_ ? d_in[134] : 1'h0;
+ assign _91_ = rst | flush_in;
+ assign rin = _91_ ? 380'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { d_in[153], d_in[146:143], _70_, d_in[97:66], d_in[148:147], d_in[134], 1'h0, d_in[139:135], _81_, _74_, _82_, c_in[36:32], cr_bypass, c_in[31:0], gpr_c_bypass, gpr_b_bypass, gpr_a_bypass, _55_[71:8], _49_[71:8], _33_[71:8], _49_[7:1], _33_[7:1], _61_[7:1], d_in[65:2], d_in[119:112], control_valid_out };
+ control_1 control_0 (
+ .busy_in(busy_in),
+ .clk(clk),
+ .complete_in(complete_in),
+ .cr_bypass(cr_bypass),
+ .cr_bypassable(cr_bypass_avail),
+ .cr_read_in(d_in[133]),
+ .cr_write_in(cr_write_valid),
+ .deferred(deferred),
+ .flush_in(flush_in),
+ .gpr_a_read_in(_33_[7:1]),
+ .gpr_a_read_valid_in(_33_[0]),
+ .gpr_b_read_in(_49_[7:1]),
+ .gpr_b_read_valid_in(_49_[0]),
+ .gpr_bypass_a(gpr_a_bypass),
+ .gpr_bypass_b(gpr_b_bypass),
+ .gpr_bypass_c(gpr_c_bypass),
+ .gpr_bypassable(gpr_bypassable),
+ .gpr_c_read_in(_55_[7:1]),
+ .gpr_c_read_valid_in(_55_[0]),
+ .gpr_write_in(_61_[7:1]),
+ .gpr_write_valid_in(_61_[0]),
+ .rst(rst),
+ .sgl_pipe_in(d_in[152]),
+ .stall_out(_00_),
+ .stop_mark_in(d_in[1]),
+ .stopped_out(_01_),
+ .update_gpr_write_reg(update_gpr_write_reg),
+ .update_gpr_write_valid(update_gpr_write_valid),
+ .valid_in(d_in[0]),
+ .valid_out(control_valid_out)
+ );
+ assign stall_out = _00_;
+ assign stopped_out = _01_;
+ assign e_out = r;
+ assign r_out = { _17_, _64_, _12_, _63_, _07_, _62_ };
+ assign c_out = d_in[133];
+ assign log_out = 10'hzzz;
+endmodule
+
+module divider(clk, rst, d_in, d_out);
+ wire [128:0] _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [63:0] _06_;
+ wire [6:0] _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [6:0] _12_;
+ wire _13_;
+ wire [6:0] _14_;
+ wire [128:0] _15_;
+ wire [63:0] _16_;
+ wire [6:0] _17_;
+ wire _18_;
+ wire [128:0] _19_;
+ wire [63:0] _20_;
+ wire [6:0] _21_;
+ wire _22_;
+ wire [128:0] _23_;
+ wire [63:0] _24_;
+ wire _25_;
+ wire [6:0] _26_;
+ wire _27_;
+ wire _28_;
+ wire [128:0] _29_;
+ wire [63:0] _30_;
+ wire [63:0] _31_;
+ wire _32_;
+ wire [6:0] _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire [128:0] _40_;
+ wire [63:0] _41_;
+ wire [63:0] _42_;
+ wire _43_;
+ wire [6:0] _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire [64:0] _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire [63:0] _62_;
+ wire _63_;
+ wire _64_;
+ reg [65:0] _65_;
+ input clk;
+ reg [6:0] count;
+ input [133:0] d_in;
+ output [65:0] d_out;
+ reg [128:0] dend;
+ wire did_ovf;
+ reg [63:0] div;
+ reg is_32bit;
+ reg is_modulus;
+ reg is_signed;
+ reg neg_result;
+ wire [63:0] oresult;
+ reg overflow;
+ reg ovf32;
+ reg [63:0] quot;
+ wire [63:0] result;
+ input rst;
+ reg running;
+ wire [64:0] sresult;
+ assign _00_ = d_in[131] ? { 1'h0, d_in[64:1], 64'h0000000000000000 } : { 65'h00000000000000000, d_in[64:1] };
+ assign _01_ = count == 7'h3f;
+ assign _02_ = _25_ ? 1'h0 : running;
+ assign _03_ = dend[127:64] >= div;
+ assign _04_ = dend[128] | _03_;
+ assign _05_ = ovf32 | quot[31];
+ assign _06_ = dend[127:64] - div;
+ assign _07_ = count + 7'h01;
+ assign _08_ = dend[128:57] == 72'h000000000000000000;
+ assign _09_ = count[6:3] != 4'h7;
+ assign _10_ = _08_ & _09_;
+ assign _11_ = | { ovf32, quot[31:24] };
+ assign _12_ = count + 7'h08;
+ assign _13_ = ovf32 | quot[31];
+ assign _14_ = count + 7'h01;
+ assign _15_ = _10_ ? { dend[120:0], 8'h00 } : { dend[127:0], 1'h0 };
+ assign _16_ = _10_ ? { quot[55:0], 8'h00 } : { quot[62:0], 1'h0 };
+ assign _17_ = _10_ ? _12_ : _14_;
+ assign _18_ = _10_ ? _11_ : _13_;
+ assign _19_ = _04_ ? { _06_, dend[63:0], 1'h0 } : _15_;
+ assign _20_ = _04_ ? { quot[62:0], 1'h1 } : _16_;
+ assign _21_ = _04_ ? _07_ : _17_;
+ assign _22_ = _04_ ? _05_ : _18_;
+ assign _23_ = running ? _19_ : dend;
+ assign _24_ = running ? _20_ : quot;
+ assign _25_ = running & _01_;
+ assign _26_ = running ? _21_ : 7'h00;
+ assign _27_ = running ? quot[63] : overflow;
+ assign _28_ = running ? _22_ : ovf32;
+ assign _29_ = d_in[0] ? _00_ : _23_;
+ assign _30_ = d_in[0] ? d_in[128:65] : div;
+ assign _31_ = d_in[0] ? 64'h0000000000000000 : _24_;
+ assign _32_ = d_in[0] ? 1'h1 : _02_;
+ assign _33_ = d_in[0] ? 7'h7f : _26_;
+ assign _34_ = d_in[0] ? d_in[133] : neg_result;
+ assign _35_ = d_in[0] ? d_in[132] : is_modulus;
+ assign _36_ = d_in[0] ? d_in[130] : is_32bit;
+ assign _37_ = d_in[0] ? d_in[129] : is_signed;
+ assign _38_ = d_in[0] ? 1'h0 : _27_;
+ assign _39_ = d_in[0] ? 1'h0 : _28_;
+ assign _40_ = rst ? 129'h000000000000000000000000000000000 : _29_;
+ assign _41_ = rst ? 64'h0000000000000000 : _30_;
+ assign _42_ = rst ? 64'h0000000000000000 : _31_;
+ assign _43_ = rst ? 1'h0 : _32_;
+ assign _44_ = rst ? 7'h00 : _33_;
+ assign _45_ = rst ? neg_result : _34_;
+ assign _46_ = rst ? is_modulus : _35_;
+ assign _47_ = rst ? is_32bit : _36_;
+ assign _48_ = rst ? is_signed : _37_;
+ assign _49_ = rst ? overflow : _38_;
+ assign _50_ = rst ? ovf32 : _39_;
+ always @(posedge clk)
+ dend <= _40_;
+ always @(posedge clk)
+ div <= _41_;
+ always @(posedge clk)
+ quot <= _42_;
+ always @(posedge clk)
+ running <= _43_;
+ always @(posedge clk)
+ count <= _44_;
+ always @(posedge clk)
+ neg_result <= _45_;
+ always @(posedge clk)
+ is_modulus <= _46_;
+ always @(posedge clk)
+ is_32bit <= _47_;
+ always @(posedge clk)
+ is_signed <= _48_;
+ always @(posedge clk)
+ overflow <= _49_;
+ always @(posedge clk)
+ ovf32 <= _50_;
+ assign result = is_modulus ? dend[128:65] : quot;
+ assign _51_ = - $signed({ 1'h0, result });
+ assign sresult = neg_result ? _51_ : { 1'h0, result };
+ assign _52_ = ~ is_32bit;
+ assign _53_ = sresult[64] ^ sresult[63];
+ assign _54_ = is_signed & _53_;
+ assign _55_ = overflow | _54_;
+ assign _56_ = sresult[32] != sresult[31];
+ assign _57_ = ovf32 | _56_;
+ assign _58_ = _57_ ? 1'h1 : 1'h0;
+ assign _59_ = is_signed ? _58_ : ovf32;
+ assign did_ovf = _52_ ? _55_ : _59_;
+ assign _60_ = ~ is_modulus;
+ assign _61_ = is_32bit & _60_;
+ assign _62_ = _61_ ? { 32'h00000000, sresult[31:0] } : sresult[63:0];
+ assign oresult = did_ovf ? 64'h0000000000000000 : _62_;
+ assign _63_ = count == 7'h40;
+ assign _64_ = _63_ ? 1'h1 : 1'h0;
+ always @(posedge clk)
+ _65_ <= { did_ovf, oresult, _64_ };
+ assign d_out = _65_;
+endmodule
+
+module dmi_dtm_jtag_8_64(sys_clk, sys_reset, dmi_din, dmi_ack, jtag_tck, jtag_tdi, jtag_tms, jtag_trst, dmi_addr, dmi_dout, dmi_req, dmi_wr, jtag_tdo);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire [1:0] _16_;
+ wire [1:0] _17_;
+ wire [71:0] _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire [63:0] _23_;
+ wire [63:0] _24_;
+ wire [63:0] _25_;
+ wire [63:0] _26_;
+ wire [7:0] _27_;
+ wire [1:0] _28_;
+ wire _29_;
+ wire [73:0] _30_;
+ wire [73:0] _31_;
+ wire [73:0] _32_;
+ wire _33_;
+ wire capture;
+ input dmi_ack;
+ reg dmi_ack_0;
+ reg dmi_ack_1;
+ output [7:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ output dmi_req;
+ output dmi_wr;
+ wire jtag_bsy;
+ reg jtag_req;
+ reg jtag_req_0;
+ reg jtag_req_1;
+ input jtag_tck;
+ input jtag_tdi;
+ output jtag_tdo;
+ input jtag_tms;
+ input jtag_trst;
+ wire op_valid;
+ reg [73:0] request;
+ wire [1:0] rsp_op;
+ wire sel;
+ wire shift;
+ reg [73:0] shiftr;
+ input sys_clk;
+ input sys_reset;
+ wire tdi;
+ wire update;
+ assign _06_ = sys_reset ? 1'h0 : jtag_req;
+ assign _07_ = sys_reset ? 1'h0 : jtag_req_0;
+ always @(posedge sys_clk)
+ jtag_req_0 <= _06_;
+ always @(posedge sys_clk)
+ jtag_req_1 <= _07_;
+ always @(posedge jtag_tck, posedge jtag_trst)
+ if (jtag_trst) dmi_ack_0 <= 1'h0;
+ else dmi_ack_0 <= dmi_ack;
+ always @(posedge jtag_tck, posedge jtag_trst)
+ if (jtag_trst) dmi_ack_1 <= 1'h0;
+ else dmi_ack_1 <= dmi_ack_0;
+ assign jtag_bsy = jtag_req | dmi_ack_1;
+ assign _08_ = shiftr[1:0] == 2'h1;
+ assign _09_ = shiftr[1:0] == 2'h2;
+ function [0:0] \6934 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \6934 = b[0:0];
+ 2'b1?:
+ \6934 = b[1:1];
+ default:
+ \6934 = a;
+ endcase
+ endfunction
+ assign op_valid = \6934 (1'h0, 2'h3, { _09_, _08_ });
+ assign rsp_op = jtag_bsy ? 2'h3 : 2'h0;
+ assign _10_ = request[1:0] == 2'h2;
+ assign _11_ = _10_ ? 1'h1 : 1'h0;
+ assign _12_ = jtag_trst | sys_reset;
+ assign _13_ = update & op_valid;
+ assign _14_ = ~ jtag_bsy;
+ assign _15_ = _20_ ? 1'h1 : jtag_req;
+ assign _16_ = shift ? shiftr[2:1] : shiftr[1:0];
+ assign _17_ = _13_ ? 2'h3 : _16_;
+ assign _18_ = shift ? { tdi, shiftr[73:3] } : shiftr[73:2];
+ assign _19_ = _13_ & _14_;
+ assign _20_ = _13_ & _14_;
+ assign _21_ = jtag_req & dmi_ack_1;
+ assign _22_ = request[1:0] == 2'h1;
+ assign _23_ = _19_ ? shiftr[65:2] : request[65:2];
+ assign _24_ = _22_ ? dmi_din : _23_;
+ assign _25_ = _19_ ? shiftr[65:2] : request[65:2];
+ assign _26_ = _21_ ? _24_ : _25_;
+ assign _27_ = _19_ ? shiftr[73:66] : request[73:66];
+ assign _28_ = _19_ ? shiftr[1:0] : request[1:0];
+ assign _29_ = _21_ ? 1'h0 : _15_;
+ assign _30_ = capture ? { request[73:2], rsp_op } : { _18_, _17_ };
+ assign _31_ = sel ? _30_ : shiftr;
+ always @(posedge jtag_tck, posedge _12_)
+ if (_12_) shiftr <= 74'h0000000000000000000;
+ else shiftr <= _31_;
+ assign _32_ = sel ? { _27_, _26_, _28_ } : request;
+ always @(posedge jtag_tck, posedge _12_)
+ if (_12_) request <= 74'h0000000000000000000;
+ else request <= _32_;
+ assign _33_ = sel ? _29_ : jtag_req;
+ always @(posedge jtag_tck, posedge _12_)
+ if (_12_) jtag_req <= 1'h0;
+ else jtag_req <= _33_;
+ tap_top tap_top0 (
+ .bs_chain_tdi_i(1'h0),
+ .capture_dr_o(capture),
+ .debug_select_o(sel),
+ .debug_tdi_i(shiftr[0]),
+ .extest_select_o(_03_),
+ .mbist_select_o(_05_),
+ .mbist_tdi_i(1'h0),
+ .pause_dr_o(_02_),
+ .sample_preload_select_o(_04_),
+ .shift_dr_o(shift),
+ .tck_pad_i(jtag_tck),
+ .tdi_pad_i(jtag_tdi),
+ .tdo_o(tdi),
+ .tdo_pad_o(_00_),
+ .tdo_padoe_o(_01_),
+ .tms_pad_i(jtag_tms),
+ .trst_pad_i(jtag_trst),
+ .update_dr_o(update)
+ );
+ assign dmi_addr = request[73:66];
+ assign dmi_dout = request[65:2];
+ assign dmi_req = jtag_req_1;
+ assign dmi_wr = _11_;
+ assign jtag_tdo = _00_;
+endmodule
+
+module execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, rst, e_in, l_in, fp_in, ext_irq_in, log_rd_data, log_wr_addr, flush_out, busy_out, l_out, f_out, fp_out, e_out, dbg_msr_out, icache_inval, terminate_out, log_out, log_rd_addr);
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire [455:0] _0006_;
+ wire [127:0] _0007_;
+ wire [63:0] _0008_;
+ wire [63:0] _0009_;
+ wire _0010_;
+ wire [63:0] _0011_;
+ wire [4:0] _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire [3:0] _0015_;
+ wire [3:0] _0016_;
+ wire [3:0] _0017_;
+ wire [3:0] _0018_;
+ wire [3:0] _0019_;
+ wire [3:0] _0020_;
+ wire [3:0] _0021_;
+ wire [3:0] _0022_;
+ wire _0023_;
+ wire [63:0] _0024_;
+ wire [63:0] _0025_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire [64:0] _0031_;
+ wire [64:0] _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire [63:0] _0038_;
+ wire [63:0] _0039_;
+ wire _0040_;
+ wire [63:0] _0041_;
+ wire [63:0] _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire [63:0] _0046_;
+ wire [127:0] _0047_;
+ wire _0048_;
+ wire [127:0] _0049_;
+ wire [127:0] _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire [63:0] _0059_;
+ wire [127:0] _0060_;
+ wire [127:0] _0061_;
+ wire _0062_;
+ wire [63:0] _0063_;
+ wire [63:0] _0064_;
+ wire [63:0] _0065_;
+ wire _0066_;
+ wire [63:0] _0067_;
+ wire _0068_;
+ wire [63:0] _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire [63:0] _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire [63:0] _0083_;
+ wire [63:0] _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire [5:0] _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire [5:0] _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0126_;
+ wire _0127_;
+ wire [63:0] _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire [115:0] _0152_;
+ wire _0153_;
+ wire [1:0] _0154_;
+ wire [1:0] _0155_;
+ wire [1:0] _0156_;
+ wire _0157_;
+ wire [72:0] _0158_;
+ wire [193:0] _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire [193:0] _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire [31:0] _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire [31:0] _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire [4:0] _0191_;
+ wire [4:0] _0192_;
+ wire _0193_;
+ wire [3:0] _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire [7:0] _0203_;
+ wire [4:0] _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire [40:0] _0208_;
+ wire [63:0] _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire [74:0] _0212_;
+ wire [40:0] _0213_;
+ wire [77:0] _0214_;
+ wire [63:0] _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire [3:0] _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire [3:0] _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire [3:0] _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire [3:0] _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire [3:0] _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire [3:0] _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire [3:0] _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire [3:0] _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire [3:0] _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire [3:0] _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire [3:0] _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire [3:0] _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire [3:0] _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire [3:0] _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire [3:0] _0282_;
+ wire _0283_;
+ wire [3:0] _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire [7:0] _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire [7:0] _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire [63:0] _0351_;
+ wire [6:0] _0352_;
+ wire [63:0] _0353_;
+ wire _0354_;
+ wire [31:0] _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire [63:0] _0369_;
+ wire [6:0] _0370_;
+ wire [63:0] _0371_;
+ wire _0372_;
+ wire [31:0] _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire [1:0] _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire [31:0] _0392_;
+ wire [63:0] _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire [7:0] _0404_;
+ wire _0405_;
+ wire [3:0] _0406_;
+ wire _0407_;
+ wire [3:0] _0408_;
+ wire _0409_;
+ wire [3:0] _0410_;
+ wire _0411_;
+ wire [3:0] _0412_;
+ wire _0413_;
+ wire [3:0] _0414_;
+ wire _0415_;
+ wire [3:0] _0416_;
+ wire _0417_;
+ wire [3:0] _0418_;
+ wire _0419_;
+ wire [3:0] _0420_;
+ wire [31:0] _0421_;
+ wire [31:0] _0422_;
+ wire [31:0] _0423_;
+ wire [31:0] _0424_;
+ wire [31:0] _0425_;
+ wire [31:0] _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire [7:0] _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire [40:0] _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire [7:0] _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire [63:0] _0515_;
+ wire [63:0] _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire [45:0] _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire [31:0] _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire [31:0] _0530_;
+ wire _0531_;
+ wire [31:0] _0532_;
+ wire [31:0] _0533_;
+ wire [31:0] _0534_;
+ wire [63:0] _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire [2:0] _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire [2:0] _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire [2:0] _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire [2:0] _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire [2:0] _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire [2:0] _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire [2:0] _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire [2:0] _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire [2:0] _0602_;
+ wire _0603_;
+ wire [3:0] _0604_;
+ wire _0605_;
+ wire [3:0] _0606_;
+ wire _0607_;
+ wire [3:0] _0608_;
+ wire _0609_;
+ wire [3:0] _0610_;
+ wire _0611_;
+ wire [3:0] _0612_;
+ wire _0613_;
+ wire [3:0] _0614_;
+ wire _0615_;
+ wire [3:0] _0616_;
+ wire _0617_;
+ wire [3:0] _0618_;
+ wire [63:0] _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire [2:0] _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire [2:0] _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire [2:0] _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire [2:0] _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire [2:0] _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire [2:0] _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire [2:0] _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire [2:0] _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire [2:0] _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire [7:0] _0694_;
+ wire [7:0] _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire [27:0] _0698_;
+ wire [2:0] _0699_;
+ wire [1:0] _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire [9:0] _0703_;
+ wire [1:0] _0704_;
+ wire _0705_;
+ wire [43:0] _0706_;
+ wire [2:0] _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire [5:0] _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire [63:0] _0714_;
+ wire [31:0] _0715_;
+ wire _0716_;
+ wire [63:0] _0717_;
+ wire [5:0] _0718_;
+ wire [31:0] _0719_;
+ wire [63:0] _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire [193:0] _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire [31:0] _0736_;
+ wire [31:0] _0737_;
+ wire [31:0] _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire [62:0] _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire [63:0] _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire [1:0] _0759_;
+ wire [1:0] _0760_;
+ wire [5:0] _0761_;
+ wire _0762_;
+ wire [1:0] _0763_;
+ wire _0764_;
+ wire [5:0] _0765_;
+ wire [4:0] _0766_;
+ wire [3:0] _0767_;
+ wire [28:0] _0768_;
+ wire _0769_;
+ wire [2:0] _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire [2:0] _0775_;
+ wire [6:0] _0776_;
+ wire [63:0] _0777_;
+ wire _0778_;
+ wire [7:0] _0779_;
+ wire [31:0] _0780_;
+ wire [5:0] _0781_;
+ wire [71:0] _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire [63:0] _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire [31:0] _0794_;
+ wire _0795_;
+ wire [2:0] _0796_;
+ wire [3:0] _0797_;
+ wire [3:0] _0798_;
+ wire [3:0] _0799_;
+ wire [3:0] _0800_;
+ wire [3:0] _0801_;
+ wire [3:0] _0802_;
+ wire [3:0] _0803_;
+ wire [3:0] _0804_;
+ wire [3:0] _0805_;
+ wire [3:0] _0806_;
+ wire [3:0] _0807_;
+ wire [3:0] _0808_;
+ wire [3:0] _0809_;
+ wire [3:0] _0810_;
+ wire [3:0] _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire [63:0] _0821_;
+ wire _0822_;
+ wire [63:0] _0823_;
+ wire [63:0] _0824_;
+ wire [63:0] _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire [63:0] _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire [71:0] _0833_;
+ wire _0834_;
+ wire [64:0] _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire [64:0] _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire [191:0] _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire [264:0] _0855_;
+ wire [31:0] _0856_;
+ wire [63:0] _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire [191:0] _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire [264:0] _0869_;
+ wire [31:0] _0870_;
+ wire [63:0] _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire [191:0] _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire [198:0] _0884_;
+ wire [63:0] _0885_;
+ wire [1:0] _0886_;
+ wire [31:0] _0887_;
+ wire [63:0] _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire [191:0] _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire [264:0] _0899_;
+ wire [31:0] _0900_;
+ wire [63:0] _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0908_;
+ wire [191:0] _0909_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire [198:0] _0913_;
+ wire [63:0] _0914_;
+ wire [1:0] _0915_;
+ wire [31:0] _0916_;
+ wire [63:0] _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire [63:0] _0925_;
+ wire [1:0] _0926_;
+ wire [1:0] _0927_;
+ wire [1:0] _0928_;
+ wire [1:0] _0929_;
+ wire [3:0] _0930_;
+ wire _0931_;
+ wire [2:0] _0932_;
+ wire [46:0] _0933_;
+ wire _0934_;
+ wire [63:0] _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire _0938_;
+ wire _0939_;
+ wire [31:0] _0940_;
+ wire [63:0] _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire [63:0] _0955_;
+ wire [63:0] _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire [2:0] _0960_;
+ wire _0961_;
+ wire [1:0] _0962_;
+ wire [6:0] _0963_;
+ wire [6:0] _0964_;
+ wire [5:0] _0965_;
+ wire [5:0] _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire [1:0] _0972_;
+ wire [6:0] _0973_;
+ wire [6:0] _0974_;
+ wire [5:0] _0975_;
+ wire [5:0] _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire [63:0] _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire [1:0] _0997_;
+ wire [6:0] _0998_;
+ wire [6:0] _0999_;
+ wire [5:0] _1000_;
+ wire [5:0] _1001_;
+ wire [63:0] _1002_;
+ wire _1003_;
+ wire [1:0] _1004_;
+ wire [6:0] _1005_;
+ wire [5:0] _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1015_;
+ wire _1016_;
+ wire _1017_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire [2:0] _1021_;
+ wire [63:0] _1022_;
+ wire _1023_;
+ wire [1:0] _1024_;
+ wire [6:0] _1025_;
+ wire _1026_;
+ wire _1027_;
+ wire [4:0] _1028_;
+ wire _1029_;
+ wire _1030_;
+ wire _1031_;
+ wire _1032_;
+ wire _1033_;
+ wire _1034_;
+ wire _1035_;
+ wire _1036_;
+ wire _1037_;
+ wire _1038_;
+ wire _1039_;
+ wire _1040_;
+ wire _1041_;
+ wire _1042_;
+ wire [2:0] _1043_;
+ wire [63:0] _1044_;
+ wire _1045_;
+ wire _1046_;
+ wire _1047_;
+ wire _1048_;
+ wire [6:0] _1049_;
+ wire [6:0] _1050_;
+ wire [5:0] _1051_;
+ wire [5:0] _1052_;
+ wire _1053_;
+ wire _1054_;
+ wire _1055_;
+ wire _1056_;
+ wire _1057_;
+ wire _1058_;
+ wire _1059_;
+ wire _1060_;
+ wire _1061_;
+ wire _1062_;
+ wire _1063_;
+ wire _1064_;
+ wire _1065_;
+ wire _1066_;
+ wire [2:0] _1067_;
+ wire _1068_;
+ wire [64:0] _1069_;
+ wire [64:0] _1070_;
+ wire [64:0] _1071_;
+ wire [64:0] _1072_;
+ wire [64:0] _1073_;
+ wire [64:0] _1074_;
+ wire [18:0] _1075_;
+ wire [18:0] _1076_;
+ wire [18:0] _1077_;
+ wire [18:0] _1078_;
+ wire [18:0] _1079_;
+ wire [18:0] _1080_;
+ wire [63:0] _1081_;
+ wire _1082_;
+ wire _1083_;
+ wire _1084_;
+ wire [63:0] _1085_;
+ wire [63:0] _1086_;
+ wire [4:0] _1087_;
+ wire _1088_;
+ wire [63:0] _1089_;
+ wire [63:0] _1090_;
+ wire [63:0] _1091_;
+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire [63:0] _1095_;
+ wire [63:0] _1096_;
+ wire [63:0] _1097_;
+ wire [6:0] _1098_;
+ wire [6:0] _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire [40:0] _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire [63:0] _1109_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire [1:0] _1114_;
+ wire _1115_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire [63:0] _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire [1:0] _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1126_;
+ wire _1127_;
+ wire [63:0] _1128_;
+ wire _1129_;
+ wire _1130_;
+ wire _1131_;
+ wire [1:0] _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire [63:0] _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1140_;
+ wire [1:0] _1141_;
+ wire _1142_;
+ wire _1143_;
+ wire _1144_;
+ wire _1145_;
+ wire _1146_;
+ wire _1147_;
+ wire _1148_;
+ wire _1149_;
+ wire _1150_;
+ wire [7:0] _1151_;
+ wire [63:0] _1152_;
+ wire _1153_;
+ wire _1154_;
+ wire [4:0] _1155_;
+ wire _1156_;
+ wire _1157_;
+ wire _1158_;
+ wire _1159_;
+ wire _1160_;
+ wire _1161_;
+ wire _1162_;
+ wire _1163_;
+ wire _1164_;
+ wire _1165_;
+ wire _1166_;
+ wire [63:0] _1167_;
+ wire _1168_;
+ wire _1169_;
+ wire _1170_;
+ wire _1171_;
+ wire _1172_;
+ wire _1173_;
+ wire _1174_;
+ wire _1175_;
+ wire _1176_;
+ wire _1177_;
+ wire _1178_;
+ wire _1179_;
+ wire _1180_;
+ wire _1181_;
+ wire _1182_;
+ wire _1183_;
+ wire _1184_;
+ wire _1185_;
+ wire _1186_;
+ wire _1187_;
+ wire _1188_;
+ wire _1189_;
+ wire _1190_;
+ wire _1191_;
+ wire _1192_;
+ wire _1193_;
+ wire _1194_;
+ wire _1195_;
+ wire _1196_;
+ wire _1197_;
+ wire _1198_;
+ wire _1199_;
+ wire _1200_;
+ wire _1201_;
+ wire _1202_;
+ wire _1203_;
+ wire _1204_;
+ wire _1205_;
+ wire _1206_;
+ wire _1207_;
+ wire _1208_;
+ wire _1209_;
+ wire _1210_;
+ wire _1211_;
+ wire _1212_;
+ wire _1213_;
+ wire _1214_;
+ wire _1215_;
+ wire _1216_;
+ wire _1217_;
+ wire _1218_;
+ wire _1219_;
+ wire _1220_;
+ wire _1221_;
+ wire _1222_;
+ wire _1223_;
+ wire _1224_;
+ wire _1225_;
+ wire _1226_;
+ wire _1227_;
+ wire _1228_;
+ wire _1229_;
+ wire _1230_;
+ wire _1231_;
+ wire _1232_;
+ wire _1233_;
+ wire _1234_;
+ wire _1235_;
+ wire _1236_;
+ wire _1237_;
+ wire _1238_;
+ wire _1239_;
+ wire _1240_;
+ wire _1241_;
+ wire _1242_;
+ wire _1243_;
+ wire _1244_;
+ wire _1245_;
+ wire _1246_;
+ wire _1247_;
+ wire _1248_;
+ wire _1249_;
+ wire _1250_;
+ wire _1251_;
+ wire _1252_;
+ wire _1253_;
+ wire _1254_;
+ wire _1255_;
+ wire _1256_;
+ wire _1257_;
+ wire _1258_;
+ wire _1259_;
+ wire _1260_;
+ wire _1261_;
+ wire _1262_;
+ wire _1263_;
+ wire _1264_;
+ wire _1265_;
+ wire _1266_;
+ wire _1267_;
+ wire _1268_;
+ wire _1269_;
+ wire _1270_;
+ wire _1271_;
+ wire _1272_;
+ wire _1273_;
+ wire _1274_;
+ wire _1275_;
+ wire _1276_;
+ wire _1277_;
+ wire _1278_;
+ wire _1279_;
+ wire _1280_;
+ wire _1281_;
+ wire _1282_;
+ wire _1283_;
+ wire _1284_;
+ wire _1285_;
+ wire _1286_;
+ wire _1287_;
+ wire _1288_;
+ wire _1289_;
+ wire _1290_;
+ wire _1291_;
+ wire _1292_;
+ wire _1293_;
+ wire _1294_;
+ wire _1295_;
+ wire _1296_;
+ wire _1297_;
+ wire _1298_;
+ wire _1299_;
+ wire _1300_;
+ wire _1301_;
+ wire _1302_;
+ wire _1303_;
+ wire _1304_;
+ wire _1305_;
+ wire _1306_;
+ wire _1307_;
+ wire _1308_;
+ wire _1309_;
+ wire _1310_;
+ wire _1311_;
+ wire _1312_;
+ wire _1313_;
+ wire _1314_;
+ wire _1315_;
+ wire _1316_;
+ wire _1317_;
+ wire _1318_;
+ wire _1319_;
+ wire _1320_;
+ wire _1321_;
+ wire _1322_;
+ wire _1323_;
+ wire _1324_;
+ wire _1325_;
+ wire _1326_;
+ wire _1327_;
+ wire _1328_;
+ wire _1329_;
+ wire _1330_;
+ wire _1331_;
+ wire _1332_;
+ wire _1333_;
+ wire _1334_;
+ wire _1335_;
+ wire _1336_;
+ wire _1337_;
+ wire _1338_;
+ wire _1339_;
+ wire _1340_;
+ wire _1341_;
+ wire _1342_;
+ wire _1343_;
+ wire _1344_;
+ wire _1345_;
+ wire _1346_;
+ wire _1347_;
+ wire _1348_;
+ wire _1349_;
+ wire _1350_;
+ wire _1351_;
+ wire _1352_;
+ wire _1353_;
+ wire _1354_;
+ wire _1355_;
+ wire _1356_;
+ wire _1357_;
+ wire _1358_;
+ wire _1359_;
+ wire _1360_;
+ wire _1361_;
+ wire _1362_;
+ wire _1363_;
+ wire _1364_;
+ wire _1365_;
+ wire _1366_;
+ wire _1367_;
+ wire _1368_;
+ wire _1369_;
+ wire _1370_;
+ wire _1371_;
+ wire _1372_;
+ wire _1373_;
+ wire _1374_;
+ wire _1375_;
+ wire _1376_;
+ wire _1377_;
+ wire _1378_;
+ wire _1379_;
+ wire _1380_;
+ wire _1381_;
+ wire _1382_;
+ wire _1383_;
+ wire _1384_;
+ wire _1385_;
+ wire _1386_;
+ wire _1387_;
+ wire _1388_;
+ wire _1389_;
+ wire _1390_;
+ wire _1391_;
+ wire _1392_;
+ wire _1393_;
+ wire _1394_;
+ wire [63:0] a_in;
+ wire [63:0] b_in;
+ output busy_out;
+ wire [63:0] c_in;
+ input clk;
+ wire [63:0] countzero_result;
+ wire [31:0] cr_in;
+ reg [320:0] ctrl = 321'h000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ output [63:0] dbg_msr_out;
+ wire [65:0] divider_to_x;
+ input [379:0] e_in;
+ output [193:0] e_out;
+ input ext_irq_in;
+ output [68:0] f_out;
+ output flush_out;
+ input [3:0] fp_in;
+ output [306:0] fp_out;
+ output icache_inval;
+ input [8:0] l_in;
+ output [325:0] l_out;
+ output [14:0] log_out;
+ output [31:0] log_rd_addr;
+ input [63:0] log_rd_data;
+ input [31:0] log_wr_addr;
+ wire [63:0] logical_result;
+ wire [129:0] multiply_to_x;
+ reg [455:0] r;
+ wire [63:0] random_cond;
+ wire random_err;
+ wire [63:0] random_raw;
+ wire right_shift;
+ wire rot_clear_left;
+ wire rot_clear_right;
+ wire rot_sign_ext;
+ wire rotator_carry;
+ wire [63:0] rotator_result;
+ input rst;
+ output terminate_out;
+ wire valid_in;
+ reg [0:0] \$mem$\14259 [63:0];
+ reg [0:0] \14259 [63:0];
+ initial begin
+ \14259 [0] = 1'h0;
+ \14259 [1] = 1'h0;
+ \14259 [2] = 1'h0;
+ \14259 [3] = 1'h0;
+ \14259 [4] = 1'h0;
+ \14259 [5] = 1'h1;
+ \14259 [6] = 1'h0;
+ \14259 [7] = 1'h0;
+ \14259 [8] = 1'h0;
+ \14259 [9] = 1'h0;
+ \14259 [10] = 1'h0;
+ \14259 [11] = 1'h0;
+ \14259 [12] = 1'h0;
+ \14259 [13] = 1'h0;
+ \14259 [14] = 1'h1;
+ \14259 [15] = 1'h0;
+ \14259 [16] = 1'h0;
+ \14259 [17] = 1'h0;
+ \14259 [18] = 1'h0;
+ \14259 [19] = 1'h0;
+ \14259 [20] = 1'h0;
+ \14259 [21] = 1'h0;
+ \14259 [22] = 1'h1;
+ \14259 [23] = 1'h0;
+ \14259 [24] = 1'h0;
+ \14259 [25] = 1'h0;
+ \14259 [26] = 1'h1;
+ \14259 [27] = 1'h0;
+ \14259 [28] = 1'h0;
+ \14259 [29] = 1'h0;
+ \14259 [30] = 1'h0;
+ \14259 [31] = 1'h0;
+ \14259 [32] = 1'h0;
+ \14259 [33] = 1'h0;
+ \14259 [34] = 1'h0;
+ \14259 [35] = 1'h0;
+ \14259 [36] = 1'h0;
+ \14259 [37] = 1'h0;
+ \14259 [38] = 1'h0;
+ \14259 [39] = 1'h0;
+ \14259 [40] = 1'h0;
+ \14259 [41] = 1'h0;
+ \14259 [42] = 1'h0;
+ \14259 [43] = 1'h0;
+ \14259 [44] = 1'h0;
+ \14259 [45] = 1'h0;
+ \14259 [46] = 1'h0;
+ \14259 [47] = 1'h0;
+ \14259 [48] = 1'h0;
+ \14259 [49] = 1'h0;
+ \14259 [50] = 1'h0;
+ \14259 [51] = 1'h0;
+ \14259 [52] = 1'h0;
+ \14259 [53] = 1'h0;
+ \14259 [54] = 1'h0;
+ \14259 [55] = 1'h0;
+ \14259 [56] = 1'h0;
+ \14259 [57] = 1'h0;
+ \14259 [58] = 1'h0;
+ \14259 [59] = 1'h1;
+ \14259 [60] = 1'h0;
+ \14259 [61] = 1'h0;
+ \14259 [62] = 1'h0;
+ \14259 [63] = 1'h0;
+ end
+ assign _1168_ = \14259 [_0112_];
+ assign _1251_ = _0355_[0] ? cr_in[1] : cr_in[0];
+ assign _1252_ = _0355_[0] ? cr_in[5] : cr_in[4];
+ assign _1253_ = _0355_[0] ? cr_in[9] : cr_in[8];
+ assign _1254_ = _0355_[0] ? cr_in[13] : cr_in[12];
+ assign _1255_ = _0355_[0] ? cr_in[17] : cr_in[16];
+ assign _1256_ = _0355_[0] ? cr_in[21] : cr_in[20];
+ assign _1257_ = _0355_[0] ? cr_in[25] : cr_in[24];
+ assign _1258_ = _0355_[0] ? cr_in[29] : cr_in[28];
+ assign _1259_ = _0355_[2] ? _1170_ : _1169_;
+ assign _1260_ = _0355_[2] ? _1174_ : _1173_;
+ assign _1261_ = _0373_[0] ? cr_in[1] : cr_in[0];
+ assign _1262_ = _0373_[0] ? cr_in[5] : cr_in[4];
+ assign _1263_ = _0373_[0] ? cr_in[9] : cr_in[8];
+ assign _1264_ = _0373_[0] ? cr_in[13] : cr_in[12];
+ assign _1265_ = _0373_[0] ? cr_in[17] : cr_in[16];
+ assign _1266_ = _0373_[0] ? cr_in[21] : cr_in[20];
+ assign _1267_ = _0373_[0] ? cr_in[25] : cr_in[24];
+ assign _1268_ = _0373_[0] ? cr_in[29] : cr_in[28];
+ assign _1269_ = _0373_[2] ? _1181_ : _1180_;
+ assign _1270_ = _0373_[2] ? _1185_ : _1184_;
+ assign _1271_ = _0392_[0] ? cr_in[1] : cr_in[0];
+ assign _1272_ = _0392_[0] ? cr_in[5] : cr_in[4];
+ assign _1273_ = _0392_[0] ? cr_in[9] : cr_in[8];
+ assign _1274_ = _0392_[0] ? cr_in[13] : cr_in[12];
+ assign _1275_ = _0392_[0] ? cr_in[17] : cr_in[16];
+ assign _1276_ = _0392_[0] ? cr_in[21] : cr_in[20];
+ assign _1277_ = _0392_[0] ? cr_in[25] : cr_in[24];
+ assign _1278_ = _0392_[0] ? cr_in[29] : cr_in[28];
+ assign _1279_ = _0392_[2] ? _1192_ : _1191_;
+ assign _1280_ = _0392_[2] ? _1196_ : _1195_;
+ assign _1281_ = _0422_[0] ? cr_in[1] : cr_in[0];
+ assign _1282_ = _0422_[0] ? cr_in[5] : cr_in[4];
+ assign _1283_ = _0422_[0] ? cr_in[9] : cr_in[8];
+ assign _1284_ = _0422_[0] ? cr_in[13] : cr_in[12];
+ assign _1285_ = _0422_[0] ? cr_in[17] : cr_in[16];
+ assign _1286_ = _0422_[0] ? cr_in[21] : cr_in[20];
+ assign _1287_ = _0422_[0] ? cr_in[25] : cr_in[24];
+ assign _1288_ = _0422_[0] ? cr_in[29] : cr_in[28];
+ assign _1289_ = _0422_[2] ? _1203_ : _1202_;
+ assign _1290_ = _0422_[2] ? _1207_ : _1206_;
+ assign _1291_ = _0423_[0] ? cr_in[1] : cr_in[0];
+ assign _1292_ = _0423_[0] ? cr_in[5] : cr_in[4];
+ assign _1293_ = _0423_[0] ? cr_in[9] : cr_in[8];
+ assign _1294_ = _0423_[0] ? cr_in[13] : cr_in[12];
+ assign _1295_ = _0423_[0] ? cr_in[17] : cr_in[16];
+ assign _1296_ = _0423_[0] ? cr_in[21] : cr_in[20];
+ assign _1297_ = _0423_[0] ? cr_in[25] : cr_in[24];
+ assign _1298_ = _0423_[0] ? cr_in[29] : cr_in[28];
+ assign _1299_ = _0423_[2] ? _1214_ : _1213_;
+ assign _1300_ = _0423_[2] ? _1218_ : _1217_;
+ assign _1301_ = _0424_[0] ? e_in[341] : e_in[340];
+ assign _1302_ = _0424_[0] ? e_in[345] : e_in[344];
+ assign _1303_ = _0737_[0] ? cr_in[1] : cr_in[0];
+ assign _1304_ = _0737_[0] ? cr_in[5] : cr_in[4];
+ assign _1305_ = _0737_[0] ? cr_in[9] : cr_in[8];
+ assign _1306_ = _0737_[0] ? cr_in[13] : cr_in[12];
+ assign _1307_ = _0737_[0] ? cr_in[17] : cr_in[16];
+ assign _1308_ = _0737_[0] ? cr_in[21] : cr_in[20];
+ assign _1309_ = _0737_[0] ? cr_in[25] : cr_in[24];
+ assign _1310_ = _0737_[0] ? cr_in[29] : cr_in[28];
+ assign _1311_ = _0737_[2] ? _1230_ : _1229_;
+ assign _1312_ = _0737_[2] ? _1234_ : _1233_;
+ assign _1313_ = _0738_[0] ? cr_in[1] : cr_in[0];
+ assign _1314_ = _0738_[0] ? cr_in[5] : cr_in[4];
+ assign _1315_ = _0738_[0] ? cr_in[9] : cr_in[8];
+ assign _1316_ = _0738_[0] ? cr_in[13] : cr_in[12];
+ assign _1317_ = _0738_[0] ? cr_in[17] : cr_in[16];
+ assign _1318_ = _0738_[0] ? cr_in[21] : cr_in[20];
+ assign _1319_ = _0738_[0] ? cr_in[25] : cr_in[24];
+ assign _1320_ = _0738_[0] ? cr_in[29] : cr_in[28];
+ assign _1321_ = _0738_[2] ? _1241_ : _1240_;
+ assign _1322_ = _0738_[2] ? _1245_ : _1244_;
+ assign _1323_ = _0355_[0] ? cr_in[3] : cr_in[2];
+ assign _1324_ = _0355_[0] ? cr_in[7] : cr_in[6];
+ assign _1325_ = _0355_[0] ? cr_in[11] : cr_in[10];
+ assign _1326_ = _0355_[0] ? cr_in[15] : cr_in[14];
+ assign _1327_ = _0355_[0] ? cr_in[19] : cr_in[18];
+ assign _1328_ = _0355_[0] ? cr_in[23] : cr_in[22];
+ assign _1329_ = _0355_[0] ? cr_in[27] : cr_in[26];
+ assign _1330_ = _0355_[0] ? cr_in[31] : cr_in[30];
+ assign _1331_ = _0355_[2] ? _1172_ : _1171_;
+ assign _1332_ = _0355_[2] ? _1176_ : _1175_;
+ assign _1333_ = _0373_[0] ? cr_in[3] : cr_in[2];
+ assign _1334_ = _0373_[0] ? cr_in[7] : cr_in[6];
+ assign _1335_ = _0373_[0] ? cr_in[11] : cr_in[10];
+ assign _1336_ = _0373_[0] ? cr_in[15] : cr_in[14];
+ assign _1337_ = _0373_[0] ? cr_in[19] : cr_in[18];
+ assign _1338_ = _0373_[0] ? cr_in[23] : cr_in[22];
+ assign _1339_ = _0373_[0] ? cr_in[27] : cr_in[26];
+ assign _1340_ = _0373_[0] ? cr_in[31] : cr_in[30];
+ assign _1341_ = _0373_[2] ? _1183_ : _1182_;
+ assign _1342_ = _0373_[2] ? _1187_ : _1186_;
+ assign _1343_ = _0392_[0] ? cr_in[3] : cr_in[2];
+ assign _1344_ = _0392_[0] ? cr_in[7] : cr_in[6];
+ assign _1345_ = _0392_[0] ? cr_in[11] : cr_in[10];
+ assign _1346_ = _0392_[0] ? cr_in[15] : cr_in[14];
+ assign _1347_ = _0392_[0] ? cr_in[19] : cr_in[18];
+ assign _1348_ = _0392_[0] ? cr_in[23] : cr_in[22];
+ assign _1349_ = _0392_[0] ? cr_in[27] : cr_in[26];
+ assign _1350_ = _0392_[0] ? cr_in[31] : cr_in[30];
+ assign _1351_ = _0392_[2] ? _1194_ : _1193_;
+ assign _1352_ = _0392_[2] ? _1198_ : _1197_;
+ assign _1353_ = _0422_[0] ? cr_in[3] : cr_in[2];
+ assign _1354_ = _0422_[0] ? cr_in[7] : cr_in[6];
+ assign _1355_ = _0422_[0] ? cr_in[11] : cr_in[10];
+ assign _1356_ = _0422_[0] ? cr_in[15] : cr_in[14];
+ assign _1357_ = _0422_[0] ? cr_in[19] : cr_in[18];
+ assign _1358_ = _0422_[0] ? cr_in[23] : cr_in[22];
+ assign _1359_ = _0422_[0] ? cr_in[27] : cr_in[26];
+ assign _1360_ = _0422_[0] ? cr_in[31] : cr_in[30];
+ assign _1361_ = _0422_[2] ? _1205_ : _1204_;
+ assign _1362_ = _0422_[2] ? _1209_ : _1208_;
+ assign _1363_ = _0423_[0] ? cr_in[3] : cr_in[2];
+ assign _1364_ = _0423_[0] ? cr_in[7] : cr_in[6];
+ assign _1365_ = _0423_[0] ? cr_in[11] : cr_in[10];
+ assign _1366_ = _0423_[0] ? cr_in[15] : cr_in[14];
+ assign _1367_ = _0423_[0] ? cr_in[19] : cr_in[18];
+ assign _1368_ = _0423_[0] ? cr_in[23] : cr_in[22];
+ assign _1369_ = _0423_[0] ? cr_in[27] : cr_in[26];
+ assign _1370_ = _0423_[0] ? cr_in[31] : cr_in[30];
+ assign _1371_ = _0423_[2] ? _1216_ : _1215_;
+ assign _1372_ = _0423_[2] ? _1220_ : _1219_;
+ assign _1373_ = _0424_[0] ? e_in[343] : e_in[342];
+ assign _1374_ = _0424_[0] ? e_in[347] : e_in[346];
+ assign _1375_ = _0737_[0] ? cr_in[3] : cr_in[2];
+ assign _1376_ = _0737_[0] ? cr_in[7] : cr_in[6];
+ assign _1377_ = _0737_[0] ? cr_in[11] : cr_in[10];
+ assign _1378_ = _0737_[0] ? cr_in[15] : cr_in[14];
+ assign _1379_ = _0737_[0] ? cr_in[19] : cr_in[18];
+ assign _1380_ = _0737_[0] ? cr_in[23] : cr_in[22];
+ assign _1381_ = _0737_[0] ? cr_in[27] : cr_in[26];
+ assign _1382_ = _0737_[0] ? cr_in[31] : cr_in[30];
+ assign _1383_ = _0737_[2] ? _1232_ : _1231_;
+ assign _1384_ = _0737_[2] ? _1236_ : _1235_;
+ assign _1385_ = _0738_[0] ? cr_in[3] : cr_in[2];
+ assign _1386_ = _0738_[0] ? cr_in[7] : cr_in[6];
+ assign _1387_ = _0738_[0] ? cr_in[11] : cr_in[10];
+ assign _1388_ = _0738_[0] ? cr_in[15] : cr_in[14];
+ assign _1389_ = _0738_[0] ? cr_in[19] : cr_in[18];
+ assign _1390_ = _0738_[0] ? cr_in[23] : cr_in[22];
+ assign _1391_ = _0738_[0] ? cr_in[27] : cr_in[26];
+ assign _1392_ = _0738_[0] ? cr_in[31] : cr_in[30];
+ assign _1393_ = _0738_[2] ? _1243_ : _1242_;
+ assign _1394_ = _0738_[2] ? _1247_ : _1246_;
+ assign _1169_ = _0355_[1] ? _1323_ : _1251_;
+ assign _1170_ = _0355_[1] ? _1324_ : _1252_;
+ assign _1171_ = _0355_[1] ? _1325_ : _1253_;
+ assign _1172_ = _0355_[1] ? _1326_ : _1254_;
+ assign _1173_ = _0355_[1] ? _1327_ : _1255_;
+ assign _1174_ = _0355_[1] ? _1328_ : _1256_;
+ assign _1175_ = _0355_[1] ? _1329_ : _1257_;
+ assign _1176_ = _0355_[1] ? _1330_ : _1258_;
+ assign _1177_ = _0355_[3] ? _1331_ : _1259_;
+ assign _1178_ = _0355_[3] ? _1332_ : _1260_;
+ assign _1180_ = _0373_[1] ? _1333_ : _1261_;
+ assign _1181_ = _0373_[1] ? _1334_ : _1262_;
+ assign _1182_ = _0373_[1] ? _1335_ : _1263_;
+ assign _1183_ = _0373_[1] ? _1336_ : _1264_;
+ assign _1184_ = _0373_[1] ? _1337_ : _1265_;
+ assign _1185_ = _0373_[1] ? _1338_ : _1266_;
+ assign _1186_ = _0373_[1] ? _1339_ : _1267_;
+ assign _1187_ = _0373_[1] ? _1340_ : _1268_;
+ assign _1188_ = _0373_[3] ? _1341_ : _1269_;
+ assign _1189_ = _0373_[3] ? _1342_ : _1270_;
+ assign _1191_ = _0392_[1] ? _1343_ : _1271_;
+ assign _1192_ = _0392_[1] ? _1344_ : _1272_;
+ assign _1193_ = _0392_[1] ? _1345_ : _1273_;
+ assign _1194_ = _0392_[1] ? _1346_ : _1274_;
+ assign _1195_ = _0392_[1] ? _1347_ : _1275_;
+ assign _1196_ = _0392_[1] ? _1348_ : _1276_;
+ assign _1197_ = _0392_[1] ? _1349_ : _1277_;
+ assign _1198_ = _0392_[1] ? _1350_ : _1278_;
+ assign _1199_ = _0392_[3] ? _1351_ : _1279_;
+ assign _1200_ = _0392_[3] ? _1352_ : _1280_;
+ assign _1202_ = _0422_[1] ? _1353_ : _1281_;
+ assign _1203_ = _0422_[1] ? _1354_ : _1282_;
+ assign _1204_ = _0422_[1] ? _1355_ : _1283_;
+ assign _1205_ = _0422_[1] ? _1356_ : _1284_;
+ assign _1206_ = _0422_[1] ? _1357_ : _1285_;
+ assign _1207_ = _0422_[1] ? _1358_ : _1286_;
+ assign _1208_ = _0422_[1] ? _1359_ : _1287_;
+ assign _1209_ = _0422_[1] ? _1360_ : _1288_;
+ assign _1210_ = _0422_[3] ? _1361_ : _1289_;
+ assign _1211_ = _0422_[3] ? _1362_ : _1290_;
+ assign _1213_ = _0423_[1] ? _1363_ : _1291_;
+ assign _1214_ = _0423_[1] ? _1364_ : _1292_;
+ assign _1215_ = _0423_[1] ? _1365_ : _1293_;
+ assign _1216_ = _0423_[1] ? _1366_ : _1294_;
+ assign _1217_ = _0423_[1] ? _1367_ : _1295_;
+ assign _1218_ = _0423_[1] ? _1368_ : _1296_;
+ assign _1219_ = _0423_[1] ? _1369_ : _1297_;
+ assign _1220_ = _0423_[1] ? _1370_ : _1298_;
+ assign _1221_ = _0423_[3] ? _1371_ : _1299_;
+ assign _1222_ = _0423_[3] ? _1372_ : _1300_;
+ assign _1224_ = _0424_[1] ? _1373_ : _1301_;
+ assign _1225_ = _0424_[1] ? _1374_ : _1302_;
+ assign _1229_ = _0737_[1] ? _1375_ : _1303_;
+ assign _1230_ = _0737_[1] ? _1376_ : _1304_;
+ assign _1231_ = _0737_[1] ? _1377_ : _1305_;
+ assign _1232_ = _0737_[1] ? _1378_ : _1306_;
+ assign _1233_ = _0737_[1] ? _1379_ : _1307_;
+ assign _1234_ = _0737_[1] ? _1380_ : _1308_;
+ assign _1235_ = _0737_[1] ? _1381_ : _1309_;
+ assign _1236_ = _0737_[1] ? _1382_ : _1310_;
+ assign _1237_ = _0737_[3] ? _1383_ : _1311_;
+ assign _1238_ = _0737_[3] ? _1384_ : _1312_;
+ assign _1240_ = _0738_[1] ? _1385_ : _1313_;
+ assign _1241_ = _0738_[1] ? _1386_ : _1314_;
+ assign _1242_ = _0738_[1] ? _1387_ : _1315_;
+ assign _1243_ = _0738_[1] ? _1388_ : _1316_;
+ assign _1244_ = _0738_[1] ? _1389_ : _1317_;
+ assign _1245_ = _0738_[1] ? _1390_ : _1318_;
+ assign _1246_ = _0738_[1] ? _1391_ : _1319_;
+ assign _1247_ = _0738_[1] ? _1392_ : _1320_;
+ assign _1248_ = _0738_[3] ? _1393_ : _1321_;
+ assign _1249_ = _0738_[3] ? _1394_ : _1322_;
+ assign _0012_ = r[116] ? r[121:117] : e_in[326:322];
+ assign _0013_ = 1'h1 & e_in[321];
+ assign _0014_ = _0013_ & r[75];
+ assign _0015_ = r[76] ? r[87:84] : e_in[292:289];
+ assign _0016_ = r[77] ? r[91:88] : e_in[296:293];
+ assign _0017_ = r[78] ? r[95:92] : e_in[300:297];
+ assign _0018_ = r[79] ? r[99:96] : e_in[304:301];
+ assign _0019_ = r[80] ? r[103:100] : e_in[308:305];
+ assign _0020_ = r[81] ? r[107:104] : e_in[312:309];
+ assign _0021_ = r[82] ? r[111:108] : e_in[316:313];
+ assign _0022_ = r[83] ? r[115:112] : e_in[320:317];
+ assign cr_in = _0014_ ? { _0022_, _0021_, _0020_, _0019_, _0018_, _0017_, _0016_, _0015_ } : e_in[320:289];
+ assign _0023_ = ~ e_in[330];
+ assign _0024_ = ~ a_in;
+ assign _0025_ = _0023_ ? a_in : _0024_;
+ assign _0026_ = e_in[333:332] == 2'h0;
+ assign _0027_ = e_in[333:332] == 2'h1;
+ assign _0028_ = e_in[333:332] == 2'h2;
+ assign _0029_ = e_in[333:332] == 2'h3;
+ function [0:0] \10097 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \10097 = b[0:0];
+ 4'b??1?:
+ \10097 = b[1:1];
+ 4'b?1??:
+ \10097 = b[2:2];
+ 4'b1???:
+ \10097 = b[3:3];
+ default:
+ \10097 = a;
+ endcase
+ endfunction
+ assign _0030_ = \10097 (1'hx, { 1'h1, _0012_[2], _0012_[0], 1'h0 }, { _0029_, _0028_, _0027_, _0026_ });
+ assign _0031_ = { 1'h0, _0025_ } + { 1'h0, b_in };
+ assign _0032_ = _0031_ + { 64'h0000000000000000, _0030_ };
+ assign _0033_ = e_in[337] ? a_in[31] : a_in[63];
+ assign _0034_ = e_in[337] ? b_in[31] : b_in[63];
+ assign _0035_ = e_in[338] ? _0033_ : 1'h0;
+ assign _0036_ = e_in[338] ? _0034_ : 1'h0;
+ assign _0037_ = ~ _0035_;
+ assign _0038_ = - $signed(a_in);
+ assign _0039_ = _0037_ ? a_in : _0038_;
+ assign _0040_ = ~ _0036_;
+ assign _0041_ = - $signed(b_in);
+ assign _0042_ = _0040_ ? b_in : _0041_;
+ assign _0043_ = e_in[8:3] == 6'h27;
+ assign _0044_ = _0043_ ? 1'h1 : 1'h0;
+ assign _0045_ = ~ e_in[365];
+ assign _0046_ = e_in[338] ? { c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63] } : 64'h0000000000000000;
+ assign _0047_ = _0045_ ? { _0046_, c_in } : 128'h00000000000000000000000000000000;
+ assign _0048_ = _0035_ ^ _0036_;
+ assign _0049_ = ~ _0047_;
+ assign _0050_ = _0048_ ? _0049_ : _0047_;
+ assign _0051_ = _0035_ ^ _0036_;
+ assign _0052_ = ~ _0044_;
+ assign _0053_ = _0036_ & _0052_;
+ assign _0054_ = _0035_ ^ _0053_;
+ assign _0055_ = ~ e_in[337];
+ assign _0056_ = e_in[8:3] == 6'h16;
+ assign _0057_ = _0056_ ? 1'h1 : 1'h0;
+ assign _0058_ = e_in[8:3] == 6'h16;
+ assign _0059_ = _0058_ ? { _0039_[31:0], 32'h00000000 } : { 32'h00000000, _0039_[31:0] };
+ assign _0060_ = _0055_ ? { _0042_, _0039_ } : { 32'h00000000, _0042_[31:0], 32'h00000000, _0039_[31:0] };
+ assign _0061_ = _0055_ ? { _0042_, _0039_ } : { 32'h00000000, _0042_[31:0], _0059_ };
+ assign _0062_ = _0055_ ? _0057_ : 1'h0;
+ assign _0063_ = ctrl[63:0] + 64'h0000000000000001;
+ assign _0064_ = ctrl[127:64] - 64'h0000000000000001;
+ assign _0065_ = ext_irq_in ? 64'h0000000000000500 : r[262:199];
+ assign _0066_ = ext_irq_in ? 1'h1 : 1'h0;
+ assign _0067_ = ctrl[127] ? 64'h0000000000000900 : _0065_;
+ assign _0068_ = ctrl[127] ? 1'h1 : _0066_;
+ assign _0069_ = ctrl[143] ? _0067_ : r[262:199];
+ assign _0070_ = ctrl[143] ? _0068_ : 1'h0;
+ assign _0071_ = ~ ctrl[142];
+ assign _0072_ = ~ ctrl[128];
+ assign _0073_ = ~ ctrl[191];
+ assign _0074_ = e_in[72:9] + 64'h0000000000000004;
+ assign _0075_ = e_in[8:3] == 6'h38;
+ assign right_shift = _0075_ ? 1'h1 : 1'h0;
+ assign _0076_ = e_in[8:3] == 6'h32;
+ assign _0077_ = e_in[8:3] == 6'h33;
+ assign _0078_ = _0076_ | _0077_;
+ assign rot_clear_left = _0078_ ? 1'h1 : 1'h0;
+ assign _0079_ = e_in[8:3] == 6'h32;
+ assign _0080_ = e_in[8:3] == 6'h34;
+ assign _0081_ = _0079_ | _0080_;
+ assign rot_clear_right = _0081_ ? 1'h1 : 1'h0;
+ assign _0082_ = e_in[8:3] == 6'h18;
+ assign rot_sign_ext = _0082_ ? 1'h1 : 1'h0;
+ assign _0083_ = valid_in ? e_in[72:9] : r[423:360];
+ assign _0084_ = valid_in ? e_in[72:9] : r[423:360];
+ assign _0085_ = ~ ctrl[191];
+ assign _0086_ = valid_in & ctrl[138];
+ assign _0087_ = valid_in ? e_in[8:3] : r[272:267];
+ assign _0088_ = ctrl[256] == 1'h1;
+ assign _0089_ = 1'h0 | r[266];
+ assign _0090_ = valid_in & _0089_;
+ assign _0091_ = r[272:267] == 6'h1f;
+ assign _0092_ = r[272:267] == 6'h1b;
+ assign _0093_ = _0091_ | _0092_;
+ assign _0094_ = r[272:267] == 6'h1c;
+ assign _0095_ = _0093_ | _0094_;
+ assign _0096_ = r[272:267] == 6'h12;
+ assign _0097_ = _0095_ | _0096_;
+ assign _0098_ = r[272:267] == 6'h11;
+ assign _0099_ = _0097_ | _0098_;
+ assign _0100_ = r[272:267] == 6'h10;
+ assign _0101_ = _0099_ | _0100_;
+ assign _0102_ = r[272:267] == 6'h20;
+ assign _0103_ = r[272:267] == 6'h14;
+ assign _0104_ = _0102_ | _0103_;
+ assign _0105_ = r[272:267] == 6'h13;
+ assign _0106_ = _0104_ | _0105_;
+ assign _0107_ = _0106_ ? 1'h1 : 1'h0;
+ assign _0108_ = _0101_ ? 1'h0 : _0107_;
+ assign _0109_ = _0101_ ? 1'h1 : 1'h0;
+ assign _0110_ = _0070_ & valid_in;
+ assign _0111_ = valid_in & ctrl[142];
+ assign _0112_ = 6'h3f - e_in[8:3];
+ assign _0113_ = _1168_ == 1'h1;
+ assign _0114_ = e_in[8:3] == 6'h26;
+ assign _0115_ = e_in[8:3] == 6'h2a;
+ assign _0116_ = _0114_ | _0115_;
+ assign _0117_ = _0116_ ? e_in[359] : 1'h0;
+ assign _0118_ = _0113_ ? 1'h1 : _0117_;
+ assign _0119_ = _0111_ & _0118_;
+ assign _0120_ = 1'h1 & valid_in;
+ assign _0121_ = e_in[8:3] == 6'h21;
+ assign _0122_ = e_in[8:3] == 6'h22;
+ assign _0123_ = _0121_ | _0122_;
+ assign _0124_ = _0120_ & _0123_;
+ assign _0125_ = e_in[2:1] == 2'h1;
+ assign _0126_ = valid_in & _0125_;
+ assign _0127_ = e_in[8:3] == 6'h00;
+ assign _0128_ = e_in[340] ? 64'h0000000000000c00 : _0069_;
+ assign _0129_ = e_in[340] ? 1'h1 : 1'h0;
+ assign _0130_ = e_in[340] ? 1'h1 : 1'h0;
+ assign _0131_ = e_in[340] ? 1'h0 : 1'h1;
+ assign _0132_ = e_in[8:3] == 6'h35;
+ assign _0133_ = e_in[349:340] == 10'h100;
+ assign _0134_ = _0133_ ? 1'h1 : 1'h0;
+ assign _0135_ = _0133_ ? 1'h0 : 1'h1;
+ assign _0136_ = e_in[8:3] == 6'h04;
+ assign _0137_ = e_in[8:3] == 6'h01;
+ assign _0138_ = e_in[8:3] == 6'h10;
+ assign _0139_ = _0137_ | _0138_;
+ assign _0140_ = e_in[8:3] == 6'h11;
+ assign _0141_ = _0139_ | _0140_;
+ assign _0142_ = e_in[8:3] == 6'h12;
+ assign _0143_ = _0141_ | _0142_;
+ assign _0144_ = e_in[8:3] == 6'h13;
+ assign _0145_ = _0143_ | _0144_;
+ assign _0146_ = e_in[8:3] == 6'h1c;
+ assign _0147_ = _0145_ | _0146_;
+ assign _0148_ = _0032_[32] ^ _0025_[32];
+ assign _0149_ = _0148_ ^ b_in[32];
+ assign _0150_ = e_in[8:3] == 6'h02;
+ assign _0151_ = e_in[333:332] != 2'h2;
+ assign _0152_ = _0151_ ? { 105'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 } : { 105'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+ assign _0153_ = _0151_ ? 1'h1 : 1'h1;
+ assign _0154_ = r[116] ? r[118:117] : e_in[323:322];
+ assign _0155_ = _0151_ ? { _0149_, _0032_[64] } : _0154_;
+ assign _0156_ = _0151_ ? _0012_[3:2] : { _0149_, _0032_[64] };
+ assign _0157_ = r[116] ? r[121] : e_in[326];
+ assign _0158_ = _0151_ ? { _0083_, 8'h44, _0012_[4] } : { _0083_, 8'h44, _0157_ };
+ assign _0159_ = e_in[334] ? { _0158_, _0156_, _0155_, _0153_, _0152_ } : { _0083_, 8'h44, _0012_, 106'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+ assign _0160_ = _0032_[64] ^ _0032_[63];
+ assign _0161_ = _0025_[63] ^ b_in[63];
+ assign _0162_ = ~ _0161_;
+ assign _0163_ = _0160_ & _0162_;
+ assign _0164_ = _0149_ ^ _0032_[31];
+ assign _0165_ = _0025_[31] ^ b_in[31];
+ assign _0166_ = ~ _0165_;
+ assign _0167_ = _0164_ & _0166_;
+ assign _0168_ = _0163_ ? 1'h1 : _0159_[121];
+ assign _0169_ = e_in[329] ? { _0159_[193:122], _0168_, _0167_, _0163_, _0159_[118:117], 1'h1, _0159_[115:0] } : _0159_;
+ assign _0170_ = e_in[8:3] == 6'h09;
+ assign _0171_ = ~ e_in[337];
+ assign _0172_ = _0170_ ? e_in[360] : _0171_;
+ assign _0173_ = a_in[31:0] ^ b_in[31:0];
+ assign _0174_ = | _0173_;
+ assign _0175_ = ~ _0174_;
+ assign _0176_ = a_in[63:32] ^ b_in[63:32];
+ assign _0177_ = | _0176_;
+ assign _0178_ = ~ _0177_;
+ assign _0179_ = ~ _0172_;
+ assign _0180_ = _0179_ | _0178_;
+ assign _0181_ = _0175_ & _0180_;
+ assign _0182_ = _0172_ ? a_in[63] : a_in[31];
+ assign _0183_ = _0172_ ? b_in[63] : b_in[31];
+ assign _0184_ = _0182_ != _0183_;
+ assign _0185_ = ~ _0172_;
+ assign _0186_ = _0185_ & _0149_;
+ assign _0187_ = _0172_ & _0032_[64];
+ assign _0188_ = _0186_ | _0187_;
+ assign _0189_ = ~ _0188_;
+ assign _0190_ = ~ _0188_;
+ assign _0191_ = _0184_ ? { _0182_, _0183_, 1'h0, _0183_, _0182_ } : { _0188_, _0189_, 1'h0, _0188_, _0190_ };
+ assign _0192_ = _0181_ ? 5'h04 : _0191_;
+ assign _0193_ = e_in[8:3] == 6'h09;
+ assign _0194_ = e_in[338] ? { _0192_[4:2], _0012_[4] } : { _0192_[1:0], _0192_[2], _0012_[4] };
+ assign _0195_ = e_in[364:362] == 3'h0;
+ assign _0196_ = e_in[364:362] == 3'h1;
+ assign _0197_ = e_in[364:362] == 3'h2;
+ assign _0198_ = e_in[364:362] == 3'h3;
+ assign _0199_ = e_in[364:362] == 3'h4;
+ assign _0200_ = e_in[364:362] == 3'h5;
+ assign _0201_ = e_in[364:362] == 3'h6;
+ assign _0202_ = e_in[364:362] == 3'h7;
+ function [7:0] \10795 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \10795 = b[7:0];
+ 8'b??????1?:
+ \10795 = b[15:8];
+ 8'b?????1??:
+ \10795 = b[23:16];
+ 8'b????1???:
+ \10795 = b[31:24];
+ 8'b???1????:
+ \10795 = b[39:32];
+ 8'b??1?????:
+ \10795 = b[47:40];
+ 8'b?1??????:
+ \10795 = b[55:48];
+ 8'b1???????:
+ \10795 = b[63:56];
+ default:
+ \10795 = a;
+ endcase
+ endfunction
+ assign _0203_ = \10795 (8'h00, 64'h0102040810204080, { _0202_, _0201_, _0200_, _0199_, _0198_, _0197_, _0196_, _0195_ });
+ assign _0204_ = _0192_ & e_in[364:360];
+ assign _0205_ = | _0204_;
+ assign _0206_ = _0205_ ? 1'h1 : 1'h0;
+ assign _0207_ = _0193_ ? 1'h0 : 1'h1;
+ assign _0208_ = _0193_ ? { _0194_, _0194_, _0194_, _0194_, _0194_, _0194_, _0194_, _0194_, _0203_, 1'h1 } : 41'h00000000000;
+ assign _0209_ = _0193_ ? _0069_ : 64'h0000000000000700;
+ assign _0210_ = _0193_ ? 1'h0 : _0206_;
+ assign _0211_ = _0150_ ? 1'h0 : _0207_;
+ assign _0212_ = _0150_ ? _0169_[74:0] : { 64'h0000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+ assign _0213_ = _0150_ ? _0169_[115:75] : _0208_;
+ assign _0214_ = _0150_ ? _0169_[193:116] : { _0083_, 8'h44, _0012_, 1'h0 };
+ assign _0215_ = _0150_ ? _0069_ : _0209_;
+ assign _0216_ = _0150_ ? 1'h1 : 1'h0;
+ assign _0217_ = _0150_ ? 1'h0 : _0210_;
+ assign _0218_ = e_in[8:3] == 6'h02;
+ assign _0219_ = e_in[8:3] == 6'h09;
+ assign _0220_ = _0218_ | _0219_;
+ assign _0221_ = e_in[8:3] == 6'h3b;
+ assign _0222_ = _0220_ | _0221_;
+ assign _0223_ = a_in[4] ^ b_in[4];
+ assign _0224_ = _0223_ ^ _0032_[4];
+ assign _0225_ = ~ _0224_;
+ assign _0226_ = _0225_ ? 4'h6 : 4'h0;
+ assign _0227_ = a_in[8] ^ b_in[8];
+ assign _0228_ = _0227_ ^ _0032_[8];
+ assign _0229_ = ~ _0228_;
+ assign _0230_ = _0229_ ? 4'h6 : 4'h0;
+ assign _0231_ = a_in[12] ^ b_in[12];
+ assign _0232_ = _0231_ ^ _0032_[12];
+ assign _0233_ = ~ _0232_;
+ assign _0234_ = _0233_ ? 4'h6 : 4'h0;
+ assign _0235_ = a_in[16] ^ b_in[16];
+ assign _0236_ = _0235_ ^ _0032_[16];
+ assign _0237_ = ~ _0236_;
+ assign _0238_ = _0237_ ? 4'h6 : 4'h0;
+ assign _0239_ = a_in[20] ^ b_in[20];
+ assign _0240_ = _0239_ ^ _0032_[20];
+ assign _0241_ = ~ _0240_;
+ assign _0242_ = _0241_ ? 4'h6 : 4'h0;
+ assign _0243_ = a_in[24] ^ b_in[24];
+ assign _0244_ = _0243_ ^ _0032_[24];
+ assign _0245_ = ~ _0244_;
+ assign _0246_ = _0245_ ? 4'h6 : 4'h0;
+ assign _0247_ = a_in[28] ^ b_in[28];
+ assign _0248_ = _0247_ ^ _0032_[28];
+ assign _0249_ = ~ _0248_;
+ assign _0250_ = _0249_ ? 4'h6 : 4'h0;
+ assign _0251_ = a_in[32] ^ b_in[32];
+ assign _0252_ = _0251_ ^ _0032_[32];
+ assign _0253_ = ~ _0252_;
+ assign _0254_ = _0253_ ? 4'h6 : 4'h0;
+ assign _0255_ = a_in[36] ^ b_in[36];
+ assign _0256_ = _0255_ ^ _0032_[36];
+ assign _0257_ = ~ _0256_;
+ assign _0258_ = _0257_ ? 4'h6 : 4'h0;
+ assign _0259_ = a_in[40] ^ b_in[40];
+ assign _0260_ = _0259_ ^ _0032_[40];
+ assign _0261_ = ~ _0260_;
+ assign _0262_ = _0261_ ? 4'h6 : 4'h0;
+ assign _0263_ = a_in[44] ^ b_in[44];
+ assign _0264_ = _0263_ ^ _0032_[44];
+ assign _0265_ = ~ _0264_;
+ assign _0266_ = _0265_ ? 4'h6 : 4'h0;
+ assign _0267_ = a_in[48] ^ b_in[48];
+ assign _0268_ = _0267_ ^ _0032_[48];
+ assign _0269_ = ~ _0268_;
+ assign _0270_ = _0269_ ? 4'h6 : 4'h0;
+ assign _0271_ = a_in[52] ^ b_in[52];
+ assign _0272_ = _0271_ ^ _0032_[52];
+ assign _0273_ = ~ _0272_;
+ assign _0274_ = _0273_ ? 4'h6 : 4'h0;
+ assign _0275_ = a_in[56] ^ b_in[56];
+ assign _0276_ = _0275_ ^ _0032_[56];
+ assign _0277_ = ~ _0276_;
+ assign _0278_ = _0277_ ? 4'h6 : 4'h0;
+ assign _0279_ = a_in[60] ^ b_in[60];
+ assign _0280_ = _0279_ ^ _0032_[60];
+ assign _0281_ = ~ _0280_;
+ assign _0282_ = _0281_ ? 4'h6 : 4'h0;
+ assign _0283_ = ~ _0032_[64];
+ assign _0284_ = _0283_ ? 4'h6 : 4'h0;
+ assign _0285_ = e_in[8:3] == 6'h3e;
+ assign _0286_ = a_in[7:0] >= b_in[7:0];
+ assign _0287_ = a_in[7:0] <= b_in[15:8];
+ assign _0288_ = _0286_ & _0287_;
+ assign _0289_ = a_in[7:0] >= b_in[23:16];
+ assign _0290_ = e_in[360] & _0289_;
+ assign _0291_ = a_in[7:0] <= b_in[31:24];
+ assign _0292_ = _0290_ & _0291_;
+ assign _0293_ = _0292_ ? 1'h1 : 1'h0;
+ assign _0294_ = _0288_ ? 1'h1 : _0293_;
+ assign _0295_ = e_in[364:362] == 3'h0;
+ assign _0296_ = e_in[364:362] == 3'h1;
+ assign _0297_ = e_in[364:362] == 3'h2;
+ assign _0298_ = e_in[364:362] == 3'h3;
+ assign _0299_ = e_in[364:362] == 3'h4;
+ assign _0300_ = e_in[364:362] == 3'h5;
+ assign _0301_ = e_in[364:362] == 3'h6;
+ assign _0302_ = e_in[364:362] == 3'h7;
+ function [7:0] \11101 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \11101 = b[7:0];
+ 8'b??????1?:
+ \11101 = b[15:8];
+ 8'b?????1??:
+ \11101 = b[23:16];
+ 8'b????1???:
+ \11101 = b[31:24];
+ 8'b???1????:
+ \11101 = b[39:32];
+ 8'b??1?????:
+ \11101 = b[47:40];
+ 8'b?1??????:
+ \11101 = b[55:48];
+ 8'b1???????:
+ \11101 = b[63:56];
+ default:
+ \11101 = a;
+ endcase
+ endfunction
+ assign _0303_ = \11101 (8'h00, 64'h0102040810204080, { _0302_, _0301_, _0300_, _0299_, _0298_, _0297_, _0296_, _0295_ });
+ assign _0304_ = e_in[8:3] == 6'h0c;
+ assign _0305_ = a_in[7:0] == b_in[7:0];
+ assign _0306_ = _0305_ ? 1'h1 : 1'h0;
+ assign _0307_ = a_in[7:0] == b_in[15:8];
+ assign _0308_ = _0307_ ? 1'h1 : _0306_;
+ assign _0309_ = a_in[7:0] == b_in[23:16];
+ assign _0310_ = _0309_ ? 1'h1 : _0308_;
+ assign _0311_ = a_in[7:0] == b_in[31:24];
+ assign _0312_ = _0311_ ? 1'h1 : _0310_;
+ assign _0313_ = a_in[7:0] == b_in[39:32];
+ assign _0314_ = _0313_ ? 1'h1 : _0312_;
+ assign _0315_ = a_in[7:0] == b_in[47:40];
+ assign _0316_ = _0315_ ? 1'h1 : _0314_;
+ assign _0317_ = a_in[7:0] == b_in[55:48];
+ assign _0318_ = _0317_ ? 1'h1 : _0316_;
+ assign _0319_ = a_in[7:0] == b_in[63:56];
+ assign _0320_ = _0319_ ? 1'h1 : _0318_;
+ assign _0321_ = e_in[364:362] == 3'h0;
+ assign _0322_ = e_in[364:362] == 3'h1;
+ assign _0323_ = e_in[364:362] == 3'h2;
+ assign _0324_ = e_in[364:362] == 3'h3;
+ assign _0325_ = e_in[364:362] == 3'h4;
+ assign _0326_ = e_in[364:362] == 3'h5;
+ assign _0327_ = e_in[364:362] == 3'h6;
+ assign _0328_ = e_in[364:362] == 3'h7;
+ function [7:0] \11204 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \11204 = b[7:0];
+ 8'b??????1?:
+ \11204 = b[15:8];
+ 8'b?????1??:
+ \11204 = b[23:16];
+ 8'b????1???:
+ \11204 = b[31:24];
+ 8'b???1????:
+ \11204 = b[39:32];
+ 8'b??1?????:
+ \11204 = b[47:40];
+ 8'b?1??????:
+ \11204 = b[55:48];
+ 8'b1???????:
+ \11204 = b[63:56];
+ default:
+ \11204 = a;
+ endcase
+ endfunction
+ assign _0329_ = \11204 (8'h00, 64'h0102040810204080, { _0328_, _0327_, _0326_, _0325_, _0324_, _0323_, _0322_, _0321_ });
+ assign _0330_ = e_in[8:3] == 6'h0b;
+ assign _0331_ = e_in[8:3] == 6'h03;
+ assign _0332_ = e_in[8:3] == 6'h2e;
+ assign _0333_ = _0331_ | _0332_;
+ assign _0334_ = e_in[8:3] == 6'h3c;
+ assign _0335_ = _0333_ | _0334_;
+ assign _0336_ = e_in[8:3] == 6'h2f;
+ assign _0337_ = _0335_ | _0336_;
+ assign _0338_ = e_in[8:3] == 6'h30;
+ assign _0339_ = _0337_ | _0338_;
+ assign _0340_ = e_in[8:3] == 6'h0a;
+ assign _0341_ = _0339_ | _0340_;
+ assign _0342_ = e_in[8:3] == 6'h17;
+ assign _0343_ = _0341_ | _0342_;
+ assign _0344_ = e_in[8:3] == 6'h08;
+ assign _0345_ = _0343_ | _0344_;
+ assign _0346_ = e_in[8:3] == 6'h3d;
+ assign _0347_ = _0345_ | _0346_;
+ assign _0348_ = ctrl[137] ? 1'h1 : _0086_;
+ assign _0349_ = e_in[8:3] == 6'h05;
+ assign _0350_ = ~ e_in[362];
+ assign _0351_ = a_in - 64'h0000000000000001;
+ assign _0352_ = _0350_ ? 7'h21 : e_in[79:73];
+ assign _0353_ = _0350_ ? _0351_ : 64'h0000000000000000;
+ assign _0354_ = _0350_ ? 1'h1 : 1'h0;
+ assign _0355_ = 32'd31 - { 27'h0000000, e_in[359:355] };
+ assign _0356_ = _1179_ == e_in[363];
+ assign _0357_ = _0356_ ? 1'h1 : 1'h0;
+ assign _0358_ = a_in != 64'h0000000000000001;
+ assign _0359_ = _0358_ ? 1'h1 : 1'h0;
+ assign _0360_ = _0359_ ^ e_in[361];
+ assign _0361_ = e_in[362] | _0360_;
+ assign _0362_ = e_in[364] | _0357_;
+ assign _0363_ = _0361_ & _0362_;
+ assign _0364_ = ctrl[137] ? 1'h1 : _0086_;
+ assign _0365_ = e_in[8:3] == 6'h06;
+ assign _0366_ = ~ e_in[362];
+ assign _0367_ = ~ e_in[349];
+ assign _0368_ = _0366_ & _0367_;
+ assign _0369_ = a_in - 64'h0000000000000001;
+ assign _0370_ = _0368_ ? 7'h21 : e_in[79:73];
+ assign _0371_ = _0368_ ? _0369_ : 64'h0000000000000000;
+ assign _0372_ = _0368_ ? 1'h1 : 1'h0;
+ assign _0373_ = 32'd31 - { 27'h0000000, e_in[359:355] };
+ assign _0374_ = _1190_ == e_in[363];
+ assign _0375_ = _0374_ ? 1'h1 : 1'h0;
+ assign _0376_ = a_in != 64'h0000000000000001;
+ assign _0377_ = _0376_ ? 1'h1 : 1'h0;
+ assign _0378_ = _0377_ ^ e_in[361];
+ assign _0379_ = e_in[362] | _0378_;
+ assign _0380_ = e_in[364] | _0375_;
+ assign _0381_ = _0379_ & _0380_;
+ assign _0382_ = ctrl[137] ? 1'h1 : _0086_;
+ assign _0383_ = e_in[8:3] == 6'h07;
+ assign _0384_ = a_in[5] | a_in[14];
+ assign _0385_ = ~ a_in[14];
+ assign _0386_ = ~ a_in[0];
+ assign _0387_ = ~ a_in[63];
+ assign _0388_ = a_in[14] ? 2'h3 : a_in[5:4];
+ assign _0389_ = a_in[14] ? 1'h1 : a_in[15];
+ assign _0390_ = e_in[8:3] == 6'h31;
+ assign _0391_ = e_in[8:3] == 6'h0d;
+ assign _0392_ = 32'd31 - { 27'h0000000, e_in[349:345] };
+ assign _0393_ = _1201_ ? a_in : b_in;
+ assign _0394_ = e_in[8:3] == 6'h1d;
+ assign _0395_ = ~ e_in[340];
+ assign _0396_ = e_in[364:362] == 3'h0;
+ assign _0397_ = e_in[364:362] == 3'h1;
+ assign _0398_ = e_in[364:362] == 3'h2;
+ assign _0399_ = e_in[364:362] == 3'h3;
+ assign _0400_ = e_in[364:362] == 3'h4;
+ assign _0401_ = e_in[364:362] == 3'h5;
+ assign _0402_ = e_in[364:362] == 3'h6;
+ assign _0403_ = e_in[364:362] == 3'h7;
+ function [7:0] \11507 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \11507 = b[7:0];
+ 8'b??????1?:
+ \11507 = b[15:8];
+ 8'b?????1??:
+ \11507 = b[23:16];
+ 8'b????1???:
+ \11507 = b[31:24];
+ 8'b???1????:
+ \11507 = b[39:32];
+ 8'b??1?????:
+ \11507 = b[47:40];
+ 8'b?1??????:
+ \11507 = b[55:48];
+ 8'b1???????:
+ \11507 = b[63:56];
+ default:
+ \11507 = a;
+ endcase
+ endfunction
+ assign _0404_ = \11507 (8'h00, 64'h0102040810204080, { _0403_, _0402_, _0401_, _0400_, _0399_, _0398_, _0397_, _0396_ });
+ assign _0405_ = 32'd0 == { 29'h00000000, e_in[359:357] };
+ assign _0406_ = _0405_ ? cr_in[31:28] : 4'h0;
+ assign _0407_ = 32'd1 == { 29'h00000000, e_in[359:357] };
+ assign _0408_ = _0407_ ? cr_in[27:24] : _0406_;
+ assign _0409_ = 32'd2 == { 29'h00000000, e_in[359:357] };
+ assign _0410_ = _0409_ ? cr_in[23:20] : _0408_;
+ assign _0411_ = 32'd3 == { 29'h00000000, e_in[359:357] };
+ assign _0412_ = _0411_ ? cr_in[19:16] : _0410_;
+ assign _0413_ = 32'd4 == { 29'h00000000, e_in[359:357] };
+ assign _0414_ = _0413_ ? cr_in[15:12] : _0412_;
+ assign _0415_ = 32'd5 == { 29'h00000000, e_in[359:357] };
+ assign _0416_ = _0415_ ? cr_in[11:8] : _0414_;
+ assign _0417_ = 32'd6 == { 29'h00000000, e_in[359:357] };
+ assign _0418_ = _0417_ ? cr_in[7:4] : _0416_;
+ assign _0419_ = 32'd7 == { 29'h00000000, e_in[359:357] };
+ assign _0420_ = _0419_ ? cr_in[3:0] : _0418_;
+ assign _0421_ = 32'd31 - { 27'h0000000, e_in[364:360] };
+ assign _0422_ = 32'd31 - { 27'h0000000, e_in[359:355] };
+ assign _0423_ = 32'd31 - { 27'h0000000, e_in[354:350] };
+ assign _0424_ = 32'd5 + { 30'h00000000, _1212_, _1223_ };
+ assign _0425_ = 32'd31 - { 27'h0000000, _0421_[4:0] };
+ assign _0426_ = $signed(_0425_) / $signed(32'd4);
+ assign _0427_ = _0426_[2:0] == 3'h0;
+ assign _0428_ = _0426_[2:0] == 3'h1;
+ assign _0429_ = _0426_[2:0] == 3'h2;
+ assign _0430_ = _0426_[2:0] == 3'h3;
+ assign _0431_ = _0426_[2:0] == 3'h4;
+ assign _0432_ = _0426_[2:0] == 3'h5;
+ assign _0433_ = _0426_[2:0] == 3'h6;
+ assign _0434_ = _0426_[2:0] == 3'h7;
+ function [7:0] \11635 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \11635 = b[7:0];
+ 8'b??????1?:
+ \11635 = b[15:8];
+ 8'b?????1??:
+ \11635 = b[23:16];
+ 8'b????1???:
+ \11635 = b[31:24];
+ 8'b???1????:
+ \11635 = b[39:32];
+ 8'b??1?????:
+ \11635 = b[47:40];
+ 8'b?1??????:
+ \11635 = b[55:48];
+ 8'b1???????:
+ \11635 = b[63:56];
+ default:
+ \11635 = a;
+ endcase
+ endfunction
+ assign _0435_ = \11635 (8'h00, 64'h0102040810204080, { _0434_, _0433_, _0432_, _0431_, _0430_, _0429_, _0428_, _0427_ });
+ assign _0436_ = 32'd0 == { 27'h0000000, _0421_[4:0] };
+ assign _0437_ = _0436_ ? _1228_ : cr_in[0];
+ assign _0438_ = 32'd1 == { 27'h0000000, _0421_[4:0] };
+ assign _0439_ = _0438_ ? _1228_ : cr_in[1];
+ assign _0440_ = 32'd2 == { 27'h0000000, _0421_[4:0] };
+ assign _0441_ = _0440_ ? _1228_ : cr_in[2];
+ assign _0442_ = 32'd3 == { 27'h0000000, _0421_[4:0] };
+ assign _0443_ = _0442_ ? _1228_ : cr_in[3];
+ assign _0444_ = 32'd4 == { 27'h0000000, _0421_[4:0] };
+ assign _0445_ = _0444_ ? _1228_ : cr_in[4];
+ assign _0446_ = 32'd5 == { 27'h0000000, _0421_[4:0] };
+ assign _0447_ = _0446_ ? _1228_ : cr_in[5];
+ assign _0448_ = 32'd6 == { 27'h0000000, _0421_[4:0] };
+ assign _0449_ = _0448_ ? _1228_ : cr_in[6];
+ assign _0450_ = 32'd7 == { 27'h0000000, _0421_[4:0] };
+ assign _0451_ = _0450_ ? _1228_ : cr_in[7];
+ assign _0452_ = 32'd8 == { 27'h0000000, _0421_[4:0] };
+ assign _0453_ = _0452_ ? _1228_ : cr_in[8];
+ assign _0454_ = 32'd9 == { 27'h0000000, _0421_[4:0] };
+ assign _0455_ = _0454_ ? _1228_ : cr_in[9];
+ assign _0456_ = 32'd10 == { 27'h0000000, _0421_[4:0] };
+ assign _0457_ = _0456_ ? _1228_ : cr_in[10];
+ assign _0458_ = 32'd11 == { 27'h0000000, _0421_[4:0] };
+ assign _0459_ = _0458_ ? _1228_ : cr_in[11];
+ assign _0460_ = 32'd12 == { 27'h0000000, _0421_[4:0] };
+ assign _0461_ = _0460_ ? _1228_ : cr_in[12];
+ assign _0462_ = 32'd13 == { 27'h0000000, _0421_[4:0] };
+ assign _0463_ = _0462_ ? _1228_ : cr_in[13];
+ assign _0464_ = 32'd14 == { 27'h0000000, _0421_[4:0] };
+ assign _0465_ = _0464_ ? _1228_ : cr_in[14];
+ assign _0466_ = 32'd15 == { 27'h0000000, _0421_[4:0] };
+ assign _0467_ = _0466_ ? _1228_ : cr_in[15];
+ assign _0468_ = 32'd16 == { 27'h0000000, _0421_[4:0] };
+ assign _0469_ = _0468_ ? _1228_ : cr_in[16];
+ assign _0470_ = 32'd17 == { 27'h0000000, _0421_[4:0] };
+ assign _0471_ = _0470_ ? _1228_ : cr_in[17];
+ assign _0472_ = 32'd18 == { 27'h0000000, _0421_[4:0] };
+ assign _0473_ = _0472_ ? _1228_ : cr_in[18];
+ assign _0474_ = 32'd19 == { 27'h0000000, _0421_[4:0] };
+ assign _0475_ = _0474_ ? _1228_ : cr_in[19];
+ assign _0476_ = 32'd20 == { 27'h0000000, _0421_[4:0] };
+ assign _0477_ = _0476_ ? _1228_ : cr_in[20];
+ assign _0478_ = 32'd21 == { 27'h0000000, _0421_[4:0] };
+ assign _0479_ = _0478_ ? _1228_ : cr_in[21];
+ assign _0480_ = 32'd22 == { 27'h0000000, _0421_[4:0] };
+ assign _0481_ = _0480_ ? _1228_ : cr_in[22];
+ assign _0482_ = 32'd23 == { 27'h0000000, _0421_[4:0] };
+ assign _0483_ = _0482_ ? _1228_ : cr_in[23];
+ assign _0484_ = 32'd24 == { 27'h0000000, _0421_[4:0] };
+ assign _0485_ = _0484_ ? _1228_ : cr_in[24];
+ assign _0486_ = 32'd25 == { 27'h0000000, _0421_[4:0] };
+ assign _0487_ = _0486_ ? _1228_ : cr_in[25];
+ assign _0488_ = 32'd26 == { 27'h0000000, _0421_[4:0] };
+ assign _0489_ = _0488_ ? _1228_ : cr_in[26];
+ assign _0490_ = 32'd27 == { 27'h0000000, _0421_[4:0] };
+ assign _0491_ = _0490_ ? _1228_ : cr_in[27];
+ assign _0492_ = 32'd28 == { 27'h0000000, _0421_[4:0] };
+ assign _0493_ = _0492_ ? _1228_ : cr_in[28];
+ assign _0494_ = 32'd29 == { 27'h0000000, _0421_[4:0] };
+ assign _0495_ = _0494_ ? _1228_ : cr_in[29];
+ assign _0496_ = 32'd30 == { 27'h0000000, _0421_[4:0] };
+ assign _0497_ = _0496_ ? _1228_ : cr_in[30];
+ assign _0498_ = 32'd31 == { 27'h0000000, _0421_[4:0] };
+ assign _0499_ = _0498_ ? _1228_ : cr_in[31];
+ assign _0500_ = _0395_ ? { _0420_, _0420_, _0420_, _0420_, _0420_, _0420_, _0420_, _0420_, _0404_, 1'h1 } : { _0499_, _0497_, _0495_, _0493_, _0491_, _0489_, _0487_, _0485_, _0483_, _0481_, _0479_, _0477_, _0475_, _0473_, _0471_, _0469_, _0467_, _0465_, _0463_, _0461_, _0459_, _0457_, _0455_, _0453_, _0451_, _0449_, _0447_, _0445_, _0443_, _0441_, _0439_, _0437_, _0435_, 1'h1 };
+ assign _0501_ = e_in[8:3] == 6'h0e;
+ assign _0502_ = e_in[364:362] == 3'h0;
+ assign _0503_ = e_in[364:362] == 3'h1;
+ assign _0504_ = e_in[364:362] == 3'h2;
+ assign _0505_ = e_in[364:362] == 3'h3;
+ assign _0506_ = e_in[364:362] == 3'h4;
+ assign _0507_ = e_in[364:362] == 3'h5;
+ assign _0508_ = e_in[364:362] == 3'h6;
+ assign _0509_ = e_in[364:362] == 3'h7;
+ function [7:0] \11890 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \11890 = b[7:0];
+ 8'b??????1?:
+ \11890 = b[15:8];
+ 8'b?????1??:
+ \11890 = b[23:16];
+ 8'b????1???:
+ \11890 = b[31:24];
+ 8'b???1????:
+ \11890 = b[39:32];
+ 8'b??1?????:
+ \11890 = b[47:40];
+ 8'b?1??????:
+ \11890 = b[55:48];
+ 8'b1???????:
+ \11890 = b[63:56];
+ default:
+ \11890 = a;
+ endcase
+ endfunction
+ assign _0510_ = \11890 (8'h00, 64'h0102040810204080, { _0509_, _0508_, _0507_, _0506_, _0505_, _0504_, _0503_, _0502_ });
+ assign _0511_ = e_in[8:3] == 6'h23;
+ assign _0512_ = ~ random_err;
+ assign _0513_ = e_in[356:355] == 2'h0;
+ assign _0514_ = e_in[356:355] == 2'h2;
+ function [63:0] \11910 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \11910 = b[63:0];
+ 2'b1?:
+ \11910 = b[127:64];
+ default:
+ \11910 = a;
+ endcase
+ endfunction
+ assign _0515_ = \11910 (random_cond, { random_raw, 32'h00000000, random_cond[31:0] }, { _0514_, _0513_ });
+ assign _0516_ = _0512_ ? _0515_ : 64'hffffffffffffffff;
+ assign _0517_ = e_in[8:3] == 6'h0f;
+ assign _0518_ = e_in[8:3] == 6'h25;
+ assign _0519_ = { 22'h000000, e_in[354:350], e_in[359:355] } == 32'd1;
+ assign _0520_ = _0519_ ? { 32'h00000000, _0012_[4], _0012_[2], _0012_[0], 9'h000, _0012_[3], _0012_[1] } : a_in[63:18];
+ assign _0521_ = { e_in[354:350], e_in[359:355] } == 10'h10c;
+ assign _0522_ = { e_in[354:350], e_in[359:355] } == 10'h10d;
+ assign _0523_ = { e_in[354:350], e_in[359:355] } == 10'h016;
+ assign _0524_ = { e_in[354:350], e_in[359:355] } == 10'h01c;
+ assign _0525_ = { e_in[354:350], e_in[359:355] } == 10'h11f;
+ assign _0526_ = { e_in[354:350], e_in[359:355] } == 10'h2d4;
+ assign _0527_ = r[455:424] + 32'd1;
+ assign _0528_ = { e_in[354:350], e_in[359:355] } == 10'h2d5;
+ assign _0529_ = ctrl[142] ? 1'h1 : 1'h0;
+ function [31:0] \12020 ;
+ input [31:0] a;
+ input [223:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \12020 = b[31:0];
+ 7'b?????1?:
+ \12020 = b[63:32];
+ 7'b????1??:
+ \12020 = b[95:64];
+ 7'b???1???:
+ \12020 = b[127:96];
+ 7'b??1????:
+ \12020 = b[159:128];
+ 7'b?1?????:
+ \12020 = b[191:160];
+ 7'b1??????:
+ \12020 = b[223:192];
+ default:
+ \12020 = a;
+ endcase
+ endfunction
+ assign _0530_ = \12020 (r[455:424], { _0527_, r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424] }, { _0528_, _0526_, _0525_, _0524_, _0523_, _0522_, _0521_ });
+ function [0:0] \12022 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \12022 = b[0:0];
+ 7'b?????1?:
+ \12022 = b[1:1];
+ 7'b????1??:
+ \12022 = b[2:2];
+ 7'b???1???:
+ \12022 = b[3:3];
+ 7'b??1????:
+ \12022 = b[4:4];
+ 7'b?1?????:
+ \12022 = b[5:5];
+ 7'b1??????:
+ \12022 = b[6:6];
+ default:
+ \12022 = a;
+ endcase
+ endfunction
+ assign _0531_ = \12022 (_0529_, 7'h00, { _0528_, _0526_, _0525_, _0524_, _0523_, _0522_, _0521_ });
+ function [31:0] \12029 ;
+ input [31:0] a;
+ input [223:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \12029 = b[31:0];
+ 7'b?????1?:
+ \12029 = b[63:32];
+ 7'b????1??:
+ \12029 = b[95:64];
+ 7'b???1???:
+ \12029 = b[127:96];
+ 7'b??1????:
+ \12029 = b[159:128];
+ 7'b?1?????:
+ \12029 = b[191:160];
+ 7'b1??????:
+ \12029 = b[223:192];
+ default:
+ \12029 = a;
+ endcase
+ endfunction
+ assign _0532_ = \12029 (c_in[31:0], { log_rd_data[31:0], r[455:424], 32'h00630100, ctrl[223:192], ctrl[95:0] }, { _0528_, _0526_, _0525_, _0524_, _0523_, _0522_, _0521_ });
+ function [31:0] \12036 ;
+ input [31:0] a;
+ input [223:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \12036 = b[31:0];
+ 7'b?????1?:
+ \12036 = b[63:32];
+ 7'b????1??:
+ \12036 = b[95:64];
+ 7'b???1???:
+ \12036 = b[127:96];
+ 7'b??1????:
+ \12036 = b[159:128];
+ 7'b?1?????:
+ \12036 = b[191:160];
+ 7'b1??????:
+ \12036 = b[223:192];
+ default:
+ \12036 = a;
+ endcase
+ endfunction
+ assign _0533_ = \12036 (c_in[63:32], { log_rd_data[63:32], log_wr_addr, 32'h00000000, ctrl[255:224], ctrl[127:96], 32'h00000000, ctrl[63:32] }, { _0528_, _0526_, _0525_, _0524_, _0523_, _0522_, _0521_ });
+ assign _0534_ = e_in[85] ? r[455:424] : _0530_;
+ assign _0535_ = e_in[85] ? { _0520_, a_in[17:0] } : { _0533_, _0532_ };
+ assign _0536_ = e_in[85] ? 1'h0 : _0531_;
+ assign _0537_ = e_in[8:3] == 6'h26;
+ assign _0538_ = ~ e_in[359];
+ assign _0539_ = e_in[358] ? 1'h0 : 1'h1;
+ assign _0540_ = e_in[358] ? 1'h0 : 1'h1;
+ assign _0541_ = e_in[358] ? 3'h0 : 3'hx;
+ assign _0542_ = _0548_ ? 1'h0 : _0539_;
+ assign _0543_ = _0549_ ? 1'h0 : _0540_;
+ assign _0544_ = _0550_ ? 3'h1 : _0541_;
+ assign _0545_ = e_in[357] & _0539_;
+ assign _0546_ = e_in[357] & _0539_;
+ assign _0547_ = e_in[357] & _0539_;
+ assign _0548_ = _0539_ & _0545_;
+ assign _0549_ = _0539_ & _0546_;
+ assign _0550_ = _0539_ & _0547_;
+ assign _0551_ = _0557_ ? 1'h0 : _0542_;
+ assign _0552_ = _0558_ ? 1'h0 : _0543_;
+ assign _0553_ = _0559_ ? 3'h2 : _0544_;
+ assign _0554_ = e_in[356] & _0542_;
+ assign _0555_ = e_in[356] & _0542_;
+ assign _0556_ = e_in[356] & _0542_;
+ assign _0557_ = _0542_ & _0554_;
+ assign _0558_ = _0542_ & _0555_;
+ assign _0559_ = _0542_ & _0556_;
+ assign _0560_ = _0566_ ? 1'h0 : _0551_;
+ assign _0561_ = _0567_ ? 1'h0 : _0552_;
+ assign _0562_ = _0568_ ? 3'h3 : _0553_;
+ assign _0563_ = e_in[355] & _0551_;
+ assign _0564_ = e_in[355] & _0551_;
+ assign _0565_ = e_in[355] & _0551_;
+ assign _0566_ = _0551_ & _0563_;
+ assign _0567_ = _0551_ & _0564_;
+ assign _0568_ = _0551_ & _0565_;
+ assign _0569_ = _0575_ ? 1'h0 : _0560_;
+ assign _0570_ = _0576_ ? 1'h0 : _0561_;
+ assign _0571_ = _0577_ ? 3'h4 : _0562_;
+ assign _0572_ = e_in[354] & _0560_;
+ assign _0573_ = e_in[354] & _0560_;
+ assign _0574_ = e_in[354] & _0560_;
+ assign _0575_ = _0560_ & _0572_;
+ assign _0576_ = _0560_ & _0573_;
+ assign _0577_ = _0560_ & _0574_;
+ assign _0578_ = _0584_ ? 1'h0 : _0569_;
+ assign _0579_ = _0585_ ? 1'h0 : _0570_;
+ assign _0580_ = _0586_ ? 3'h5 : _0571_;
+ assign _0581_ = e_in[353] & _0569_;
+ assign _0582_ = e_in[353] & _0569_;
+ assign _0583_ = e_in[353] & _0569_;
+ assign _0584_ = _0569_ & _0581_;
+ assign _0585_ = _0569_ & _0582_;
+ assign _0586_ = _0569_ & _0583_;
+ assign _0587_ = _0593_ ? 1'h0 : _0578_;
+ assign _0588_ = _0594_ ? 1'h0 : _0579_;
+ assign _0589_ = _0595_ ? 3'h6 : _0580_;
+ assign _0590_ = e_in[352] & _0578_;
+ assign _0591_ = e_in[352] & _0578_;
+ assign _0592_ = e_in[352] & _0578_;
+ assign _0593_ = _0578_ & _0590_;
+ assign _0594_ = _0578_ & _0591_;
+ assign _0595_ = _0578_ & _0592_;
+ assign _0596_ = _0600_ ? 1'h0 : _0588_;
+ assign _0597_ = _0601_ ? 3'h7 : _0589_;
+ assign _0598_ = e_in[351] & _0587_;
+ assign _0599_ = e_in[351] & _0587_;
+ assign _0600_ = _0587_ & _0598_;
+ assign _0601_ = _0587_ & _0599_;
+ assign _0602_ = _0596_ ? 3'h7 : _0597_;
+ assign _0603_ = { 29'h00000000, _0602_ } == 32'd0;
+ assign _0604_ = _0603_ ? cr_in[31:28] : 4'h0;
+ assign _0605_ = { 29'h00000000, _0602_ } == 32'd1;
+ assign _0606_ = _0605_ ? cr_in[27:24] : 4'h0;
+ assign _0607_ = { 29'h00000000, _0602_ } == 32'd2;
+ assign _0608_ = _0607_ ? cr_in[23:20] : 4'h0;
+ assign _0609_ = { 29'h00000000, _0602_ } == 32'd3;
+ assign _0610_ = _0609_ ? cr_in[19:16] : 4'h0;
+ assign _0611_ = { 29'h00000000, _0602_ } == 32'd4;
+ assign _0612_ = _0611_ ? cr_in[15:12] : 4'h0;
+ assign _0613_ = { 29'h00000000, _0602_ } == 32'd5;
+ assign _0614_ = _0613_ ? cr_in[11:8] : 4'h0;
+ assign _0615_ = { 29'h00000000, _0602_ } == 32'd6;
+ assign _0616_ = _0615_ ? cr_in[7:4] : 4'h0;
+ assign _0617_ = { 29'h00000000, _0602_ } == 32'd7;
+ assign _0618_ = _0617_ ? cr_in[3:0] : 4'h0;
+ assign _0619_ = _0538_ ? { 32'h00000000, cr_in } : { 32'h00000000, _0604_, _0606_, _0608_, _0610_, _0612_, _0614_, _0616_, _0618_ };
+ assign _0620_ = e_in[8:3] == 6'h24;
+ assign _0621_ = ~ e_in[359];
+ assign _0622_ = e_in[358] ? 1'h0 : 1'h1;
+ assign _0623_ = e_in[358] ? 1'h0 : 1'h1;
+ assign _0624_ = e_in[358] ? 3'h0 : 3'hx;
+ assign _0625_ = _0631_ ? 1'h0 : _0622_;
+ assign _0626_ = _0632_ ? 1'h0 : _0623_;
+ assign _0627_ = _0633_ ? 3'h1 : _0624_;
+ assign _0628_ = e_in[357] & _0622_;
+ assign _0629_ = e_in[357] & _0622_;
+ assign _0630_ = e_in[357] & _0622_;
+ assign _0631_ = _0622_ & _0628_;
+ assign _0632_ = _0622_ & _0629_;
+ assign _0633_ = _0622_ & _0630_;
+ assign _0634_ = _0640_ ? 1'h0 : _0625_;
+ assign _0635_ = _0641_ ? 1'h0 : _0626_;
+ assign _0636_ = _0642_ ? 3'h2 : _0627_;
+ assign _0637_ = e_in[356] & _0625_;
+ assign _0638_ = e_in[356] & _0625_;
+ assign _0639_ = e_in[356] & _0625_;
+ assign _0640_ = _0625_ & _0637_;
+ assign _0641_ = _0625_ & _0638_;
+ assign _0642_ = _0625_ & _0639_;
+ assign _0643_ = _0649_ ? 1'h0 : _0634_;
+ assign _0644_ = _0650_ ? 1'h0 : _0635_;
+ assign _0645_ = _0651_ ? 3'h3 : _0636_;
+ assign _0646_ = e_in[355] & _0634_;
+ assign _0647_ = e_in[355] & _0634_;
+ assign _0648_ = e_in[355] & _0634_;
+ assign _0649_ = _0634_ & _0646_;
+ assign _0650_ = _0634_ & _0647_;
+ assign _0651_ = _0634_ & _0648_;
+ assign _0652_ = _0658_ ? 1'h0 : _0643_;
+ assign _0653_ = _0659_ ? 1'h0 : _0644_;
+ assign _0654_ = _0660_ ? 3'h4 : _0645_;
+ assign _0655_ = e_in[354] & _0643_;
+ assign _0656_ = e_in[354] & _0643_;
+ assign _0657_ = e_in[354] & _0643_;
+ assign _0658_ = _0643_ & _0655_;
+ assign _0659_ = _0643_ & _0656_;
+ assign _0660_ = _0643_ & _0657_;
+ assign _0661_ = _0667_ ? 1'h0 : _0652_;
+ assign _0662_ = _0668_ ? 1'h0 : _0653_;
+ assign _0663_ = _0669_ ? 3'h5 : _0654_;
+ assign _0664_ = e_in[353] & _0652_;
+ assign _0665_ = e_in[353] & _0652_;
+ assign _0666_ = e_in[353] & _0652_;
+ assign _0667_ = _0652_ & _0664_;
+ assign _0668_ = _0652_ & _0665_;
+ assign _0669_ = _0652_ & _0666_;
+ assign _0670_ = _0676_ ? 1'h0 : _0661_;
+ assign _0671_ = _0677_ ? 1'h0 : _0662_;
+ assign _0672_ = _0678_ ? 3'h6 : _0663_;
+ assign _0673_ = e_in[352] & _0661_;
+ assign _0674_ = e_in[352] & _0661_;
+ assign _0675_ = e_in[352] & _0661_;
+ assign _0676_ = _0661_ & _0673_;
+ assign _0677_ = _0661_ & _0674_;
+ assign _0678_ = _0661_ & _0675_;
+ assign _0679_ = _0683_ ? 1'h0 : _0671_;
+ assign _0680_ = _0684_ ? 3'h7 : _0672_;
+ assign _0681_ = e_in[351] & _0670_;
+ assign _0682_ = e_in[351] & _0670_;
+ assign _0683_ = _0670_ & _0681_;
+ assign _0684_ = _0670_ & _0682_;
+ assign _0685_ = _0679_ ? 3'h7 : _0680_;
+ assign _0686_ = _0685_ == 3'h0;
+ assign _0687_ = _0685_ == 3'h1;
+ assign _0688_ = _0685_ == 3'h2;
+ assign _0689_ = _0685_ == 3'h3;
+ assign _0690_ = _0685_ == 3'h4;
+ assign _0691_ = _0685_ == 3'h5;
+ assign _0692_ = _0685_ == 3'h6;
+ assign _0693_ = _0685_ == 3'h7;
+ function [7:0] \12398 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \12398 = b[7:0];
+ 8'b??????1?:
+ \12398 = b[15:8];
+ 8'b?????1??:
+ \12398 = b[23:16];
+ 8'b????1???:
+ \12398 = b[31:24];
+ 8'b???1????:
+ \12398 = b[39:32];
+ 8'b??1?????:
+ \12398 = b[47:40];
+ 8'b?1??????:
+ \12398 = b[55:48];
+ 8'b1???????:
+ \12398 = b[63:56];
+ default:
+ \12398 = a;
+ endcase
+ endfunction
+ assign _0694_ = \12398 (8'h00, 64'h0102040810204080, { _0693_, _0692_, _0691_, _0690_, _0689_, _0688_, _0687_, _0686_ });
+ assign _0695_ = _0621_ ? e_in[358:351] : _0694_;
+ assign _0696_ = e_in[8:3] == 6'h28;
+ assign _0697_ = ~ e_in[337];
+ assign _0698_ = _0697_ ? c_in[59:32] : ctrl[187:160];
+ assign _0699_ = _0697_ ? c_in[63:61] : ctrl[191:189];
+ assign _0700_ = c_in[14] ? 2'h3 : c_in[5:4];
+ assign _0701_ = c_in[14] ? 1'h1 : c_in[15];
+ assign _0702_ = e_in[355] ? c_in[1] : c_in[1];
+ assign _0703_ = e_in[355] ? ctrl[139:130] : { c_in[11:6], _0700_, c_in[3:2] };
+ assign _0704_ = e_in[355] ? ctrl[142:141] : c_in[14:13];
+ assign _0705_ = e_in[355] ? c_in[15] : _0701_;
+ assign _0706_ = e_in[355] ? ctrl[187:144] : { _0698_, c_in[31:16] };
+ assign _0707_ = e_in[355] ? ctrl[191:189] : _0699_;
+ assign _0708_ = e_in[8:3] == 6'h29;
+ assign _0709_ = { 22'h000000, e_in[354:350], e_in[359:355] } == 32'd1;
+ assign _0710_ = _0709_ ? { c_in[31], c_in[19], c_in[30], c_in[18], c_in[29], 1'h1 } : { _0012_, 1'h0 };
+ assign _0711_ = { e_in[354:350], e_in[359:355] } == 10'h016;
+ assign _0712_ = { e_in[354:350], e_in[359:355] } == 10'h2d4;
+ assign _0713_ = ctrl[142] ? 1'h1 : 1'h0;
+ function [63:0] \12499 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \12499 = b[63:0];
+ 2'b1?:
+ \12499 = b[127:64];
+ default:
+ \12499 = a;
+ endcase
+ endfunction
+ assign _0714_ = \12499 (_0064_, { _0064_, c_in }, { _0712_, _0711_ });
+ function [31:0] \12500 ;
+ input [31:0] a;
+ input [63:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \12500 = b[31:0];
+ 2'b1?:
+ \12500 = b[63:32];
+ default:
+ \12500 = a;
+ endcase
+ endfunction
+ assign _0715_ = \12500 (r[455:424], { c_in[31:0], r[455:424] }, { _0712_, _0711_ });
+ function [0:0] \12502 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \12502 = b[0:0];
+ 2'b1?:
+ \12502 = b[1:1];
+ default:
+ \12502 = a;
+ endcase
+ endfunction
+ assign _0716_ = \12502 (_0713_, 2'h0, { _0712_, _0711_ });
+ assign _0717_ = e_in[78] ? _0064_ : _0714_;
+ assign _0718_ = e_in[78] ? _0710_ : { _0012_, 1'h0 };
+ assign _0719_ = e_in[78] ? r[455:424] : _0715_;
+ assign _0720_ = e_in[78] ? c_in : 64'h0000000000000000;
+ assign _0721_ = e_in[78] ? 1'h1 : 1'h0;
+ assign _0722_ = e_in[78] ? 1'h0 : _0716_;
+ assign _0723_ = e_in[8:3] == 6'h2a;
+ assign _0724_ = e_in[334] ? { _0083_, 8'h44, _0012_[4:2], rotator_carry, rotator_carry, 106'h200000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 } : { _0083_, 8'h44, _0012_, 106'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+ assign _0725_ = e_in[8:3] == 6'h32;
+ assign _0726_ = e_in[8:3] == 6'h33;
+ assign _0727_ = _0725_ | _0726_;
+ assign _0728_ = e_in[8:3] == 6'h34;
+ assign _0729_ = _0727_ | _0728_;
+ assign _0730_ = e_in[8:3] == 6'h37;
+ assign _0731_ = _0729_ | _0730_;
+ assign _0732_ = e_in[8:3] == 6'h38;
+ assign _0733_ = _0731_ | _0732_;
+ assign _0734_ = e_in[8:3] == 6'h18;
+ assign _0735_ = _0733_ | _0734_;
+ assign _0736_ = $signed({ 29'h00000000, e_in[359:357] }) * $signed(32'd4);
+ assign _0737_ = 32'd31 - { 27'h0000000, _0736_[4:0] };
+ assign _0738_ = 32'd30 - { 27'h0000000, _0736_[4:0] };
+ assign _0739_ = _1250_ ? 1'h1 : 1'h0;
+ assign _0740_ = _1239_ ? 1'h1 : _0739_;
+ assign _0741_ = _1239_ ? 63'h7fffffffffffffff : 63'h0000000000000000;
+ assign _0742_ = e_in[8:3] == 6'h36;
+ assign _0743_ = e_in[8:3] == 6'h1e;
+ assign _0744_ = e_in[8:3] == 6'h1b;
+ assign _0745_ = e_in[8:3] == 6'h2b;
+ assign _0746_ = e_in[8:3] == 6'h2c;
+ assign _0747_ = _0745_ | _0746_;
+ assign _0748_ = e_in[8:3] == 6'h2d;
+ assign _0749_ = _0747_ | _0748_;
+ assign _0750_ = e_in[8:3] == 6'h15;
+ assign _0751_ = e_in[8:3] == 6'h16;
+ assign _0752_ = _0750_ | _0751_;
+ assign _0753_ = e_in[8:3] == 6'h27;
+ assign _0754_ = _0752_ | _0753_;
+ function [0:0] \12621 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12621 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12621 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12621 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12621 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12621 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12621 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12621 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12621 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12621 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12621 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12621 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12621 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12621 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12621 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12621 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12621 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12621 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12621 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12621 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12621 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12621 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12621 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12621 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12621 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12621 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12621 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12621 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12621 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12621 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12621 = b[29:29];
+ default:
+ \12621 = a;
+ endcase
+ endfunction
+ assign _0755_ = \12621 (1'h0, 30'h08000000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [63:0] \12622 ;
+ input [63:0] a;
+ input [1919:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12622 = b[63:0];
+ 30'b????????????????????????????1?:
+ \12622 = b[127:64];
+ 30'b???????????????????????????1??:
+ \12622 = b[191:128];
+ 30'b??????????????????????????1???:
+ \12622 = b[255:192];
+ 30'b?????????????????????????1????:
+ \12622 = b[319:256];
+ 30'b????????????????????????1?????:
+ \12622 = b[383:320];
+ 30'b???????????????????????1??????:
+ \12622 = b[447:384];
+ 30'b??????????????????????1???????:
+ \12622 = b[511:448];
+ 30'b?????????????????????1????????:
+ \12622 = b[575:512];
+ 30'b????????????????????1?????????:
+ \12622 = b[639:576];
+ 30'b???????????????????1??????????:
+ \12622 = b[703:640];
+ 30'b??????????????????1???????????:
+ \12622 = b[767:704];
+ 30'b?????????????????1????????????:
+ \12622 = b[831:768];
+ 30'b????????????????1?????????????:
+ \12622 = b[895:832];
+ 30'b???????????????1??????????????:
+ \12622 = b[959:896];
+ 30'b??????????????1???????????????:
+ \12622 = b[1023:960];
+ 30'b?????????????1????????????????:
+ \12622 = b[1087:1024];
+ 30'b????????????1?????????????????:
+ \12622 = b[1151:1088];
+ 30'b???????????1??????????????????:
+ \12622 = b[1215:1152];
+ 30'b??????????1???????????????????:
+ \12622 = b[1279:1216];
+ 30'b?????????1????????????????????:
+ \12622 = b[1343:1280];
+ 30'b????????1?????????????????????:
+ \12622 = b[1407:1344];
+ 30'b???????1??????????????????????:
+ \12622 = b[1471:1408];
+ 30'b??????1???????????????????????:
+ \12622 = b[1535:1472];
+ 30'b?????1????????????????????????:
+ \12622 = b[1599:1536];
+ 30'b????1?????????????????????????:
+ \12622 = b[1663:1600];
+ 30'b???1??????????????????????????:
+ \12622 = b[1727:1664];
+ 30'b??1???????????????????????????:
+ \12622 = b[1791:1728];
+ 30'b?1????????????????????????????:
+ \12622 = b[1855:1792];
+ 30'b1?????????????????????????????:
+ \12622 = b[1919:1856];
+ default:
+ \12622 = a;
+ endcase
+ endfunction
+ assign _0756_ = \12622 (_0064_, { _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0717_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_, _0064_ }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12625 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12625 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12625 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12625 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12625 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12625 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12625 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12625 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12625 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12625 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12625 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12625 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12625 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12625 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12625 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12625 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12625 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12625 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12625 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12625 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12625 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12625 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12625 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12625 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12625 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12625 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12625 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12625 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12625 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12625 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12625 = b[29:29];
+ default:
+ \12625 = a;
+ endcase
+ endfunction
+ assign _0757_ = \12625 (ctrl[128], { ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], a_in[0], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12628 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12628 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12628 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12628 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12628 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12628 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12628 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12628 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12628 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12628 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12628 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12628 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12628 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12628 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12628 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12628 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12628 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12628 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12628 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12628 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12628 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12628 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12628 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12628 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12628 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12628 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12628 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12628 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12628 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12628 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12628 = b[29:29];
+ default:
+ \12628 = a;
+ endcase
+ endfunction
+ assign _0758_ = \12628 (ctrl[129], { ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], _0702_, ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], a_in[1], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [1:0] \12632 ;
+ input [1:0] a;
+ input [59:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12632 = b[1:0];
+ 30'b????????????????????????????1?:
+ \12632 = b[3:2];
+ 30'b???????????????????????????1??:
+ \12632 = b[5:4];
+ 30'b??????????????????????????1???:
+ \12632 = b[7:6];
+ 30'b?????????????????????????1????:
+ \12632 = b[9:8];
+ 30'b????????????????????????1?????:
+ \12632 = b[11:10];
+ 30'b???????????????????????1??????:
+ \12632 = b[13:12];
+ 30'b??????????????????????1???????:
+ \12632 = b[15:14];
+ 30'b?????????????????????1????????:
+ \12632 = b[17:16];
+ 30'b????????????????????1?????????:
+ \12632 = b[19:18];
+ 30'b???????????????????1??????????:
+ \12632 = b[21:20];
+ 30'b??????????????????1???????????:
+ \12632 = b[23:22];
+ 30'b?????????????????1????????????:
+ \12632 = b[25:24];
+ 30'b????????????????1?????????????:
+ \12632 = b[27:26];
+ 30'b???????????????1??????????????:
+ \12632 = b[29:28];
+ 30'b??????????????1???????????????:
+ \12632 = b[31:30];
+ 30'b?????????????1????????????????:
+ \12632 = b[33:32];
+ 30'b????????????1?????????????????:
+ \12632 = b[35:34];
+ 30'b???????????1??????????????????:
+ \12632 = b[37:36];
+ 30'b??????????1???????????????????:
+ \12632 = b[39:38];
+ 30'b?????????1????????????????????:
+ \12632 = b[41:40];
+ 30'b????????1?????????????????????:
+ \12632 = b[43:42];
+ 30'b???????1??????????????????????:
+ \12632 = b[45:44];
+ 30'b??????1???????????????????????:
+ \12632 = b[47:46];
+ 30'b?????1????????????????????????:
+ \12632 = b[49:48];
+ 30'b????1?????????????????????????:
+ \12632 = b[51:50];
+ 30'b???1??????????????????????????:
+ \12632 = b[53:52];
+ 30'b??1???????????????????????????:
+ \12632 = b[55:54];
+ 30'b?1????????????????????????????:
+ \12632 = b[57:56];
+ 30'b1?????????????????????????????:
+ \12632 = b[59:58];
+ default:
+ \12632 = a;
+ endcase
+ endfunction
+ assign _0759_ = \12632 (ctrl[131:130], { ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], _0703_[1:0], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], a_in[3:2], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [1:0] \12635 ;
+ input [1:0] a;
+ input [59:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12635 = b[1:0];
+ 30'b????????????????????????????1?:
+ \12635 = b[3:2];
+ 30'b???????????????????????????1??:
+ \12635 = b[5:4];
+ 30'b??????????????????????????1???:
+ \12635 = b[7:6];
+ 30'b?????????????????????????1????:
+ \12635 = b[9:8];
+ 30'b????????????????????????1?????:
+ \12635 = b[11:10];
+ 30'b???????????????????????1??????:
+ \12635 = b[13:12];
+ 30'b??????????????????????1???????:
+ \12635 = b[15:14];
+ 30'b?????????????????????1????????:
+ \12635 = b[17:16];
+ 30'b????????????????????1?????????:
+ \12635 = b[19:18];
+ 30'b???????????????????1??????????:
+ \12635 = b[21:20];
+ 30'b??????????????????1???????????:
+ \12635 = b[23:22];
+ 30'b?????????????????1????????????:
+ \12635 = b[25:24];
+ 30'b????????????????1?????????????:
+ \12635 = b[27:26];
+ 30'b???????????????1??????????????:
+ \12635 = b[29:28];
+ 30'b??????????????1???????????????:
+ \12635 = b[31:30];
+ 30'b?????????????1????????????????:
+ \12635 = b[33:32];
+ 30'b????????????1?????????????????:
+ \12635 = b[35:34];
+ 30'b???????????1??????????????????:
+ \12635 = b[37:36];
+ 30'b??????????1???????????????????:
+ \12635 = b[39:38];
+ 30'b?????????1????????????????????:
+ \12635 = b[41:40];
+ 30'b????????1?????????????????????:
+ \12635 = b[43:42];
+ 30'b???????1??????????????????????:
+ \12635 = b[45:44];
+ 30'b??????1???????????????????????:
+ \12635 = b[47:46];
+ 30'b?????1????????????????????????:
+ \12635 = b[49:48];
+ 30'b????1?????????????????????????:
+ \12635 = b[51:50];
+ 30'b???1??????????????????????????:
+ \12635 = b[53:52];
+ 30'b??1???????????????????????????:
+ \12635 = b[55:54];
+ 30'b?1????????????????????????????:
+ \12635 = b[57:56];
+ 30'b1?????????????????????????????:
+ \12635 = b[59:58];
+ default:
+ \12635 = a;
+ endcase
+ endfunction
+ assign _0760_ = \12635 (ctrl[133:132], { ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], _0703_[3:2], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], _0388_, ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [5:0] \12639 ;
+ input [5:0] a;
+ input [179:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12639 = b[5:0];
+ 30'b????????????????????????????1?:
+ \12639 = b[11:6];
+ 30'b???????????????????????????1??:
+ \12639 = b[17:12];
+ 30'b??????????????????????????1???:
+ \12639 = b[23:18];
+ 30'b?????????????????????????1????:
+ \12639 = b[29:24];
+ 30'b????????????????????????1?????:
+ \12639 = b[35:30];
+ 30'b???????????????????????1??????:
+ \12639 = b[41:36];
+ 30'b??????????????????????1???????:
+ \12639 = b[47:42];
+ 30'b?????????????????????1????????:
+ \12639 = b[53:48];
+ 30'b????????????????????1?????????:
+ \12639 = b[59:54];
+ 30'b???????????????????1??????????:
+ \12639 = b[65:60];
+ 30'b??????????????????1???????????:
+ \12639 = b[71:66];
+ 30'b?????????????????1????????????:
+ \12639 = b[77:72];
+ 30'b????????????????1?????????????:
+ \12639 = b[83:78];
+ 30'b???????????????1??????????????:
+ \12639 = b[89:84];
+ 30'b??????????????1???????????????:
+ \12639 = b[95:90];
+ 30'b?????????????1????????????????:
+ \12639 = b[101:96];
+ 30'b????????????1?????????????????:
+ \12639 = b[107:102];
+ 30'b???????????1??????????????????:
+ \12639 = b[113:108];
+ 30'b??????????1???????????????????:
+ \12639 = b[119:114];
+ 30'b?????????1????????????????????:
+ \12639 = b[125:120];
+ 30'b????????1?????????????????????:
+ \12639 = b[131:126];
+ 30'b???????1??????????????????????:
+ \12639 = b[137:132];
+ 30'b??????1???????????????????????:
+ \12639 = b[143:138];
+ 30'b?????1????????????????????????:
+ \12639 = b[149:144];
+ 30'b????1?????????????????????????:
+ \12639 = b[155:150];
+ 30'b???1??????????????????????????:
+ \12639 = b[161:156];
+ 30'b??1???????????????????????????:
+ \12639 = b[167:162];
+ 30'b?1????????????????????????????:
+ \12639 = b[173:168];
+ 30'b1?????????????????????????????:
+ \12639 = b[179:174];
+ default:
+ \12639 = a;
+ endcase
+ endfunction
+ assign _0761_ = \12639 (ctrl[139:134], { ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], _0703_[9:4], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], a_in[11:6], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12642 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12642 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12642 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12642 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12642 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12642 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12642 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12642 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12642 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12642 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12642 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12642 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12642 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12642 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12642 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12642 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12642 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12642 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12642 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12642 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12642 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12642 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12642 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12642 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12642 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12642 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12642 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12642 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12642 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12642 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12642 = b[29:29];
+ default:
+ \12642 = a;
+ endcase
+ endfunction
+ assign _0762_ = \12642 (ctrl[140], { ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], a_in[12], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [1:0] \12645 ;
+ input [1:0] a;
+ input [59:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12645 = b[1:0];
+ 30'b????????????????????????????1?:
+ \12645 = b[3:2];
+ 30'b???????????????????????????1??:
+ \12645 = b[5:4];
+ 30'b??????????????????????????1???:
+ \12645 = b[7:6];
+ 30'b?????????????????????????1????:
+ \12645 = b[9:8];
+ 30'b????????????????????????1?????:
+ \12645 = b[11:10];
+ 30'b???????????????????????1??????:
+ \12645 = b[13:12];
+ 30'b??????????????????????1???????:
+ \12645 = b[15:14];
+ 30'b?????????????????????1????????:
+ \12645 = b[17:16];
+ 30'b????????????????????1?????????:
+ \12645 = b[19:18];
+ 30'b???????????????????1??????????:
+ \12645 = b[21:20];
+ 30'b??????????????????1???????????:
+ \12645 = b[23:22];
+ 30'b?????????????????1????????????:
+ \12645 = b[25:24];
+ 30'b????????????????1?????????????:
+ \12645 = b[27:26];
+ 30'b???????????????1??????????????:
+ \12645 = b[29:28];
+ 30'b??????????????1???????????????:
+ \12645 = b[31:30];
+ 30'b?????????????1????????????????:
+ \12645 = b[33:32];
+ 30'b????????????1?????????????????:
+ \12645 = b[35:34];
+ 30'b???????????1??????????????????:
+ \12645 = b[37:36];
+ 30'b??????????1???????????????????:
+ \12645 = b[39:38];
+ 30'b?????????1????????????????????:
+ \12645 = b[41:40];
+ 30'b????????1?????????????????????:
+ \12645 = b[43:42];
+ 30'b???????1??????????????????????:
+ \12645 = b[45:44];
+ 30'b??????1???????????????????????:
+ \12645 = b[47:46];
+ 30'b?????1????????????????????????:
+ \12645 = b[49:48];
+ 30'b????1?????????????????????????:
+ \12645 = b[51:50];
+ 30'b???1??????????????????????????:
+ \12645 = b[53:52];
+ 30'b??1???????????????????????????:
+ \12645 = b[55:54];
+ 30'b?1????????????????????????????:
+ \12645 = b[57:56];
+ 30'b1?????????????????????????????:
+ \12645 = b[59:58];
+ default:
+ \12645 = a;
+ endcase
+ endfunction
+ assign _0763_ = \12645 (ctrl[142:141], { ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], _0704_, ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], a_in[14:13], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12647 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12647 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12647 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12647 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12647 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12647 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12647 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12647 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12647 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12647 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12647 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12647 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12647 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12647 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12647 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12647 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12647 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12647 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12647 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12647 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12647 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12647 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12647 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12647 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12647 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12647 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12647 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12647 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12647 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12647 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12647 = b[29:29];
+ default:
+ \12647 = a;
+ endcase
+ endfunction
+ assign _0764_ = \12647 (ctrl[143], { ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], _0705_, ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], _0389_, ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [5:0] \12650 ;
+ input [5:0] a;
+ input [179:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12650 = b[5:0];
+ 30'b????????????????????????????1?:
+ \12650 = b[11:6];
+ 30'b???????????????????????????1??:
+ \12650 = b[17:12];
+ 30'b??????????????????????????1???:
+ \12650 = b[23:18];
+ 30'b?????????????????????????1????:
+ \12650 = b[29:24];
+ 30'b????????????????????????1?????:
+ \12650 = b[35:30];
+ 30'b???????????????????????1??????:
+ \12650 = b[41:36];
+ 30'b??????????????????????1???????:
+ \12650 = b[47:42];
+ 30'b?????????????????????1????????:
+ \12650 = b[53:48];
+ 30'b????????????????????1?????????:
+ \12650 = b[59:54];
+ 30'b???????????????????1??????????:
+ \12650 = b[65:60];
+ 30'b??????????????????1???????????:
+ \12650 = b[71:66];
+ 30'b?????????????????1????????????:
+ \12650 = b[77:72];
+ 30'b????????????????1?????????????:
+ \12650 = b[83:78];
+ 30'b???????????????1??????????????:
+ \12650 = b[89:84];
+ 30'b??????????????1???????????????:
+ \12650 = b[95:90];
+ 30'b?????????????1????????????????:
+ \12650 = b[101:96];
+ 30'b????????????1?????????????????:
+ \12650 = b[107:102];
+ 30'b???????????1??????????????????:
+ \12650 = b[113:108];
+ 30'b??????????1???????????????????:
+ \12650 = b[119:114];
+ 30'b?????????1????????????????????:
+ \12650 = b[125:120];
+ 30'b????????1?????????????????????:
+ \12650 = b[131:126];
+ 30'b???????1??????????????????????:
+ \12650 = b[137:132];
+ 30'b??????1???????????????????????:
+ \12650 = b[143:138];
+ 30'b?????1????????????????????????:
+ \12650 = b[149:144];
+ 30'b????1?????????????????????????:
+ \12650 = b[155:150];
+ 30'b???1??????????????????????????:
+ \12650 = b[161:156];
+ 30'b??1???????????????????????????:
+ \12650 = b[167:162];
+ 30'b?1????????????????????????????:
+ \12650 = b[173:168];
+ 30'b1?????????????????????????????:
+ \12650 = b[179:174];
+ default:
+ \12650 = a;
+ endcase
+ endfunction
+ assign _0765_ = \12650 (ctrl[149:144], { ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], _0706_[5:0], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [4:0] \12653 ;
+ input [4:0] a;
+ input [149:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12653 = b[4:0];
+ 30'b????????????????????????????1?:
+ \12653 = b[9:5];
+ 30'b???????????????????????????1??:
+ \12653 = b[14:10];
+ 30'b??????????????????????????1???:
+ \12653 = b[19:15];
+ 30'b?????????????????????????1????:
+ \12653 = b[24:20];
+ 30'b????????????????????????1?????:
+ \12653 = b[29:25];
+ 30'b???????????????????????1??????:
+ \12653 = b[34:30];
+ 30'b??????????????????????1???????:
+ \12653 = b[39:35];
+ 30'b?????????????????????1????????:
+ \12653 = b[44:40];
+ 30'b????????????????????1?????????:
+ \12653 = b[49:45];
+ 30'b???????????????????1??????????:
+ \12653 = b[54:50];
+ 30'b??????????????????1???????????:
+ \12653 = b[59:55];
+ 30'b?????????????????1????????????:
+ \12653 = b[64:60];
+ 30'b????????????????1?????????????:
+ \12653 = b[69:65];
+ 30'b???????????????1??????????????:
+ \12653 = b[74:70];
+ 30'b??????????????1???????????????:
+ \12653 = b[79:75];
+ 30'b?????????????1????????????????:
+ \12653 = b[84:80];
+ 30'b????????????1?????????????????:
+ \12653 = b[89:85];
+ 30'b???????????1??????????????????:
+ \12653 = b[94:90];
+ 30'b??????????1???????????????????:
+ \12653 = b[99:95];
+ 30'b?????????1????????????????????:
+ \12653 = b[104:100];
+ 30'b????????1?????????????????????:
+ \12653 = b[109:105];
+ 30'b???????1??????????????????????:
+ \12653 = b[114:110];
+ 30'b??????1???????????????????????:
+ \12653 = b[119:115];
+ 30'b?????1????????????????????????:
+ \12653 = b[124:120];
+ 30'b????1?????????????????????????:
+ \12653 = b[129:125];
+ 30'b???1??????????????????????????:
+ \12653 = b[134:130];
+ 30'b??1???????????????????????????:
+ \12653 = b[139:135];
+ 30'b?1????????????????????????????:
+ \12653 = b[144:140];
+ 30'b1?????????????????????????????:
+ \12653 = b[149:145];
+ default:
+ \12653 = a;
+ endcase
+ endfunction
+ assign _0766_ = \12653 (ctrl[154:150], { ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], _0706_[10:6], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], a_in[26:22], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12656 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12656 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12656 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12656 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12656 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12656 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12656 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12656 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12656 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12656 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12656 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12656 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12656 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12656 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12656 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12656 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12656 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12656 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12656 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12656 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12656 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12656 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12656 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12656 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12656 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12656 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12656 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12656 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12656 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12656 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12656 = b[119:116];
+ default:
+ \12656 = a;
+ endcase
+ endfunction
+ assign _0767_ = \12656 (ctrl[158:155], { ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], _0706_[14:11], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [28:0] \12660 ;
+ input [28:0] a;
+ input [869:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12660 = b[28:0];
+ 30'b????????????????????????????1?:
+ \12660 = b[57:29];
+ 30'b???????????????????????????1??:
+ \12660 = b[86:58];
+ 30'b??????????????????????????1???:
+ \12660 = b[115:87];
+ 30'b?????????????????????????1????:
+ \12660 = b[144:116];
+ 30'b????????????????????????1?????:
+ \12660 = b[173:145];
+ 30'b???????????????????????1??????:
+ \12660 = b[202:174];
+ 30'b??????????????????????1???????:
+ \12660 = b[231:203];
+ 30'b?????????????????????1????????:
+ \12660 = b[260:232];
+ 30'b????????????????????1?????????:
+ \12660 = b[289:261];
+ 30'b???????????????????1??????????:
+ \12660 = b[318:290];
+ 30'b??????????????????1???????????:
+ \12660 = b[347:319];
+ 30'b?????????????????1????????????:
+ \12660 = b[376:348];
+ 30'b????????????????1?????????????:
+ \12660 = b[405:377];
+ 30'b???????????????1??????????????:
+ \12660 = b[434:406];
+ 30'b??????????????1???????????????:
+ \12660 = b[463:435];
+ 30'b?????????????1????????????????:
+ \12660 = b[492:464];
+ 30'b????????????1?????????????????:
+ \12660 = b[521:493];
+ 30'b???????????1??????????????????:
+ \12660 = b[550:522];
+ 30'b??????????1???????????????????:
+ \12660 = b[579:551];
+ 30'b?????????1????????????????????:
+ \12660 = b[608:580];
+ 30'b????????1?????????????????????:
+ \12660 = b[637:609];
+ 30'b???????1??????????????????????:
+ \12660 = b[666:638];
+ 30'b??????1???????????????????????:
+ \12660 = b[695:667];
+ 30'b?????1????????????????????????:
+ \12660 = b[724:696];
+ 30'b????1?????????????????????????:
+ \12660 = b[753:725];
+ 30'b???1??????????????????????????:
+ \12660 = b[782:754];
+ 30'b??1???????????????????????????:
+ \12660 = b[811:783];
+ 30'b?1????????????????????????????:
+ \12660 = b[840:812];
+ 30'b1?????????????????????????????:
+ \12660 = b[869:841];
+ default:
+ \12660 = a;
+ endcase
+ endfunction
+ assign _0768_ = \12660 (ctrl[187:159], { ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], _0706_[43:15], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], a_in[59:31], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12663 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12663 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12663 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12663 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12663 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12663 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12663 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12663 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12663 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12663 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12663 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12663 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12663 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12663 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12663 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12663 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12663 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12663 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12663 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12663 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12663 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12663 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12663 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12663 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12663 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12663 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12663 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12663 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12663 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12663 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12663 = b[29:29];
+ default:
+ \12663 = a;
+ endcase
+ endfunction
+ assign _0769_ = \12663 (ctrl[188], { ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], a_in[60], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [2:0] \12666 ;
+ input [2:0] a;
+ input [89:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12666 = b[2:0];
+ 30'b????????????????????????????1?:
+ \12666 = b[5:3];
+ 30'b???????????????????????????1??:
+ \12666 = b[8:6];
+ 30'b??????????????????????????1???:
+ \12666 = b[11:9];
+ 30'b?????????????????????????1????:
+ \12666 = b[14:12];
+ 30'b????????????????????????1?????:
+ \12666 = b[17:15];
+ 30'b???????????????????????1??????:
+ \12666 = b[20:18];
+ 30'b??????????????????????1???????:
+ \12666 = b[23:21];
+ 30'b?????????????????????1????????:
+ \12666 = b[26:24];
+ 30'b????????????????????1?????????:
+ \12666 = b[29:27];
+ 30'b???????????????????1??????????:
+ \12666 = b[32:30];
+ 30'b??????????????????1???????????:
+ \12666 = b[35:33];
+ 30'b?????????????????1????????????:
+ \12666 = b[38:36];
+ 30'b????????????????1?????????????:
+ \12666 = b[41:39];
+ 30'b???????????????1??????????????:
+ \12666 = b[44:42];
+ 30'b??????????????1???????????????:
+ \12666 = b[47:45];
+ 30'b?????????????1????????????????:
+ \12666 = b[50:48];
+ 30'b????????????1?????????????????:
+ \12666 = b[53:51];
+ 30'b???????????1??????????????????:
+ \12666 = b[56:54];
+ 30'b??????????1???????????????????:
+ \12666 = b[59:57];
+ 30'b?????????1????????????????????:
+ \12666 = b[62:60];
+ 30'b????????1?????????????????????:
+ \12666 = b[65:63];
+ 30'b???????1??????????????????????:
+ \12666 = b[68:66];
+ 30'b??????1???????????????????????:
+ \12666 = b[71:69];
+ 30'b?????1????????????????????????:
+ \12666 = b[74:72];
+ 30'b????1?????????????????????????:
+ \12666 = b[77:75];
+ 30'b???1??????????????????????????:
+ \12666 = b[80:78];
+ 30'b??1???????????????????????????:
+ \12666 = b[83:81];
+ 30'b?1????????????????????????????:
+ \12666 = b[86:84];
+ 30'b1?????????????????????????????:
+ \12666 = b[89:87];
+ default:
+ \12666 = a;
+ endcase
+ endfunction
+ assign _0770_ = \12666 (ctrl[191:189], { ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], _0707_, ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], a_in[63:61], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12668 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12668 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12668 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12668 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12668 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12668 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12668 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12668 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12668 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12668 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12668 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12668 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12668 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12668 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12668 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12668 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12668 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12668 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12668 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12668 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12668 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12668 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12668 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12668 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12668 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12668 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12668 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12668 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12668 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12668 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12668 = b[29:29];
+ default:
+ \12668 = a;
+ endcase
+ endfunction
+ assign _0771_ = \12668 (1'h0, { 25'h0000000, _0211_, 4'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12669 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12669 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12669 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12669 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12669 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12669 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12669 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12669 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12669 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12669 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12669 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12669 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12669 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12669 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12669 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12669 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12669 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12669 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12669 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12669 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12669 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12669 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12669 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12669 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12669 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12669 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12669 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12669 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12669 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12669 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12669 = b[29:29];
+ default:
+ \12669 = a;
+ endcase
+ endfunction
+ assign _0772_ = \12669 (1'h0, 30'h10000000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12670 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12670 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12670 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12670 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12670 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12670 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12670 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12670 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12670 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12670 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12670 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12670 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12670 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12670 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12670 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12670 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12670 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12670 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12670 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12670 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12670 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12670 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12670 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12670 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12670 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12670 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12670 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12670 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12670 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12670 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12670 = b[29:29];
+ default:
+ \12670 = a;
+ endcase
+ endfunction
+ assign _0773_ = \12670 (1'h0, 30'h20000000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12673 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12673 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12673 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12673 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12673 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12673 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12673 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12673 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12673 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12673 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12673 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12673 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12673 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12673 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12673 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12673 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12673 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12673 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12673 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12673 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12673 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12673 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12673 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12673 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12673 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12673 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12673 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12673 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12673 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12673 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12673 = b[29:29];
+ default:
+ \12673 = a;
+ endcase
+ endfunction
+ assign _0774_ = \12673 (1'h1, { 5'h07, _0724_[0], 19'h7feff, _0212_[0], 4'hf }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [2:0] \12679 ;
+ input [2:0] a;
+ input [89:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12679 = b[2:0];
+ 30'b????????????????????????????1?:
+ \12679 = b[5:3];
+ 30'b???????????????????????????1??:
+ \12679 = b[8:6];
+ 30'b??????????????????????????1???:
+ \12679 = b[11:9];
+ 30'b?????????????????????????1????:
+ \12679 = b[14:12];
+ 30'b????????????????????????1?????:
+ \12679 = b[17:15];
+ 30'b???????????????????????1??????:
+ \12679 = b[20:18];
+ 30'b??????????????????????1???????:
+ \12679 = b[23:21];
+ 30'b?????????????????????1????????:
+ \12679 = b[26:24];
+ 30'b????????????????????1?????????:
+ \12679 = b[29:27];
+ 30'b???????????????????1??????????:
+ \12679 = b[32:30];
+ 30'b??????????????????1???????????:
+ \12679 = b[35:33];
+ 30'b?????????????????1????????????:
+ \12679 = b[38:36];
+ 30'b????????????????1?????????????:
+ \12679 = b[41:39];
+ 30'b???????????????1??????????????:
+ \12679 = b[44:42];
+ 30'b??????????????1???????????????:
+ \12679 = b[47:45];
+ 30'b?????????????1????????????????:
+ \12679 = b[50:48];
+ 30'b????????????1?????????????????:
+ \12679 = b[53:51];
+ 30'b???????????1??????????????????:
+ \12679 = b[56:54];
+ 30'b??????????1???????????????????:
+ \12679 = b[59:57];
+ 30'b?????????1????????????????????:
+ \12679 = b[62:60];
+ 30'b????????1?????????????????????:
+ \12679 = b[65:63];
+ 30'b???????1??????????????????????:
+ \12679 = b[68:66];
+ 30'b??????1???????????????????????:
+ \12679 = b[71:69];
+ 30'b?????1????????????????????????:
+ \12679 = b[74:72];
+ 30'b????1?????????????????????????:
+ \12679 = b[77:75];
+ 30'b???1??????????????????????????:
+ \12679 = b[80:78];
+ 30'b??1???????????????????????????:
+ \12679 = b[83:81];
+ 30'b?1????????????????????????????:
+ \12679 = b[86:84];
+ 30'b1?????????????????????????????:
+ \12679 = b[89:87];
+ default:
+ \12679 = a;
+ endcase
+ endfunction
+ assign _0775_ = \12679 ({ 1'h0, _0085_, 1'h0 }, { 1'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 1'h0, _0724_[3:1], 1'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 1'h0, _0212_[3:1], 1'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 2'h0, _0085_, 1'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [6:0] \12682 ;
+ input [6:0] a;
+ input [209:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12682 = b[6:0];
+ 30'b????????????????????????????1?:
+ \12682 = b[13:7];
+ 30'b???????????????????????????1??:
+ \12682 = b[20:14];
+ 30'b??????????????????????????1???:
+ \12682 = b[27:21];
+ 30'b?????????????????????????1????:
+ \12682 = b[34:28];
+ 30'b????????????????????????1?????:
+ \12682 = b[41:35];
+ 30'b???????????????????????1??????:
+ \12682 = b[48:42];
+ 30'b??????????????????????1???????:
+ \12682 = b[55:49];
+ 30'b?????????????????????1????????:
+ \12682 = b[62:56];
+ 30'b????????????????????1?????????:
+ \12682 = b[69:63];
+ 30'b???????????????????1??????????:
+ \12682 = b[76:70];
+ 30'b??????????????????1???????????:
+ \12682 = b[83:77];
+ 30'b?????????????????1????????????:
+ \12682 = b[90:84];
+ 30'b????????????????1?????????????:
+ \12682 = b[97:91];
+ 30'b???????????????1??????????????:
+ \12682 = b[104:98];
+ 30'b??????????????1???????????????:
+ \12682 = b[111:105];
+ 30'b?????????????1????????????????:
+ \12682 = b[118:112];
+ 30'b????????????1?????????????????:
+ \12682 = b[125:119];
+ 30'b???????????1??????????????????:
+ \12682 = b[132:126];
+ 30'b??????????1???????????????????:
+ \12682 = b[139:133];
+ 30'b?????????1????????????????????:
+ \12682 = b[146:140];
+ 30'b????????1?????????????????????:
+ \12682 = b[153:147];
+ 30'b???????1??????????????????????:
+ \12682 = b[160:154];
+ 30'b??????1???????????????????????:
+ \12682 = b[167:161];
+ 30'b?????1????????????????????????:
+ \12682 = b[174:168];
+ 30'b????1?????????????????????????:
+ \12682 = b[181:175];
+ 30'b???1??????????????????????????:
+ \12682 = b[188:182];
+ 30'b??1???????????????????????????:
+ \12682 = b[195:189];
+ 30'b?1????????????????????????????:
+ \12682 = b[202:196];
+ 30'b1?????????????????????????????:
+ \12682 = b[209:203];
+ default:
+ \12682 = a;
+ endcase
+ endfunction
+ assign _0776_ = \12682 (e_in[79:73], { e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], _0724_[10:4], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], _0370_, _0352_, e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73], _0212_[10:4], e_in[79:73], e_in[79:73], e_in[79:73], e_in[79:73] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [63:0] \12686 ;
+ input [63:0] a;
+ input [1919:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12686 = b[63:0];
+ 30'b????????????????????????????1?:
+ \12686 = b[127:64];
+ 30'b???????????????????????????1??:
+ \12686 = b[191:128];
+ 30'b??????????????????????????1???:
+ \12686 = b[255:192];
+ 30'b?????????????????????????1????:
+ \12686 = b[319:256];
+ 30'b????????????????????????1?????:
+ \12686 = b[383:320];
+ 30'b???????????????????????1??????:
+ \12686 = b[447:384];
+ 30'b??????????????????????1???????:
+ \12686 = b[511:448];
+ 30'b?????????????????????1????????:
+ \12686 = b[575:512];
+ 30'b????????????????????1?????????:
+ \12686 = b[639:576];
+ 30'b???????????????????1??????????:
+ \12686 = b[703:640];
+ 30'b??????????????????1???????????:
+ \12686 = b[767:704];
+ 30'b?????????????????1????????????:
+ \12686 = b[831:768];
+ 30'b????????????????1?????????????:
+ \12686 = b[895:832];
+ 30'b???????????????1??????????????:
+ \12686 = b[959:896];
+ 30'b??????????????1???????????????:
+ \12686 = b[1023:960];
+ 30'b?????????????1????????????????:
+ \12686 = b[1087:1024];
+ 30'b????????????1?????????????????:
+ \12686 = b[1151:1088];
+ 30'b???????????1??????????????????:
+ \12686 = b[1215:1152];
+ 30'b??????????1???????????????????:
+ \12686 = b[1279:1216];
+ 30'b?????????1????????????????????:
+ \12686 = b[1343:1280];
+ 30'b????????1?????????????????????:
+ \12686 = b[1407:1344];
+ 30'b???????1??????????????????????:
+ \12686 = b[1471:1408];
+ 30'b??????1???????????????????????:
+ \12686 = b[1535:1472];
+ 30'b?????1????????????????????????:
+ \12686 = b[1599:1536];
+ 30'b????1?????????????????????????:
+ \12686 = b[1663:1600];
+ 30'b???1??????????????????????????:
+ \12686 = b[1727:1664];
+ 30'b??1???????????????????????????:
+ \12686 = b[1791:1728];
+ 30'b?1????????????????????????????:
+ \12686 = b[1855:1792];
+ 30'b1?????????????????????????????:
+ \12686 = b[1919:1856];
+ default:
+ \12686 = a;
+ endcase
+ endfunction
+ assign _0777_ = \12686 (64'h0000000000000000, { 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000, _0724_[74:11], 1216'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _0212_[74:11], 256'h0000000000000000000000000000000000000000000000000000000000000000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12691 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12691 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12691 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12691 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12691 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12691 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12691 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12691 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12691 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12691 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12691 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12691 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12691 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12691 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12691 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12691 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12691 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12691 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12691 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12691 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12691 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12691 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12691 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12691 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12691 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12691 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12691 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12691 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12691 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12691 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12691 = b[29:29];
+ default:
+ \12691 = a;
+ endcase
+ endfunction
+ assign _0778_ = \12691 (1'h0, { 5'h00, _0724_[75], 8'h21, _0500_[0], 10'h006, _0213_[0], 4'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [7:0] \12696 ;
+ input [7:0] a;
+ input [239:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12696 = b[7:0];
+ 30'b????????????????????????????1?:
+ \12696 = b[15:8];
+ 30'b???????????????????????????1??:
+ \12696 = b[23:16];
+ 30'b??????????????????????????1???:
+ \12696 = b[31:24];
+ 30'b?????????????????????????1????:
+ \12696 = b[39:32];
+ 30'b????????????????????????1?????:
+ \12696 = b[47:40];
+ 30'b???????????????????????1??????:
+ \12696 = b[55:48];
+ 30'b??????????????????????1???????:
+ \12696 = b[63:56];
+ 30'b?????????????????????1????????:
+ \12696 = b[71:64];
+ 30'b????????????????????1?????????:
+ \12696 = b[79:72];
+ 30'b???????????????????1??????????:
+ \12696 = b[87:80];
+ 30'b??????????????????1???????????:
+ \12696 = b[95:88];
+ 30'b?????????????????1????????????:
+ \12696 = b[103:96];
+ 30'b????????????????1?????????????:
+ \12696 = b[111:104];
+ 30'b???????????????1??????????????:
+ \12696 = b[119:112];
+ 30'b??????????????1???????????????:
+ \12696 = b[127:120];
+ 30'b?????????????1????????????????:
+ \12696 = b[135:128];
+ 30'b????????????1?????????????????:
+ \12696 = b[143:136];
+ 30'b???????????1??????????????????:
+ \12696 = b[151:144];
+ 30'b??????????1???????????????????:
+ \12696 = b[159:152];
+ 30'b?????????1????????????????????:
+ \12696 = b[167:160];
+ 30'b????????1?????????????????????:
+ \12696 = b[175:168];
+ 30'b???????1??????????????????????:
+ \12696 = b[183:176];
+ 30'b??????1???????????????????????:
+ \12696 = b[191:184];
+ 30'b?????1????????????????????????:
+ \12696 = b[199:192];
+ 30'b????1?????????????????????????:
+ \12696 = b[207:200];
+ 30'b???1??????????????????????????:
+ \12696 = b[215:208];
+ 30'b??1???????????????????????????:
+ \12696 = b[223:216];
+ 30'b?1????????????????????????????:
+ \12696 = b[231:224];
+ 30'b1?????????????????????????????:
+ \12696 = b[239:232];
+ default:
+ \12696 = a;
+ endcase
+ endfunction
+ assign _0779_ = \12696 (8'h00, { 40'h0000000000, _0724_[83:76], 16'h0000, _0695_, 32'h00000000, _0510_, _0500_[8:1], 56'h00000000000000, _0329_, _0303_, 8'h00, _0213_[8:1], 32'h00000000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [31:0] \12701 ;
+ input [31:0] a;
+ input [959:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12701 = b[31:0];
+ 30'b????????????????????????????1?:
+ \12701 = b[63:32];
+ 30'b???????????????????????????1??:
+ \12701 = b[95:64];
+ 30'b??????????????????????????1???:
+ \12701 = b[127:96];
+ 30'b?????????????????????????1????:
+ \12701 = b[159:128];
+ 30'b????????????????????????1?????:
+ \12701 = b[191:160];
+ 30'b???????????????????????1??????:
+ \12701 = b[223:192];
+ 30'b??????????????????????1???????:
+ \12701 = b[255:224];
+ 30'b?????????????????????1????????:
+ \12701 = b[287:256];
+ 30'b????????????????????1?????????:
+ \12701 = b[319:288];
+ 30'b???????????????????1??????????:
+ \12701 = b[351:320];
+ 30'b??????????????????1???????????:
+ \12701 = b[383:352];
+ 30'b?????????????????1????????????:
+ \12701 = b[415:384];
+ 30'b????????????????1?????????????:
+ \12701 = b[447:416];
+ 30'b???????????????1??????????????:
+ \12701 = b[479:448];
+ 30'b??????????????1???????????????:
+ \12701 = b[511:480];
+ 30'b?????????????1????????????????:
+ \12701 = b[543:512];
+ 30'b????????????1?????????????????:
+ \12701 = b[575:544];
+ 30'b???????????1??????????????????:
+ \12701 = b[607:576];
+ 30'b??????????1???????????????????:
+ \12701 = b[639:608];
+ 30'b?????????1????????????????????:
+ \12701 = b[671:640];
+ 30'b????????1?????????????????????:
+ \12701 = b[703:672];
+ 30'b???????1??????????????????????:
+ \12701 = b[735:704];
+ 30'b??????1???????????????????????:
+ \12701 = b[767:736];
+ 30'b?????1????????????????????????:
+ \12701 = b[799:768];
+ 30'b????1?????????????????????????:
+ \12701 = b[831:800];
+ 30'b???1??????????????????????????:
+ \12701 = b[863:832];
+ 30'b??1???????????????????????????:
+ \12701 = b[895:864];
+ 30'b?1????????????????????????????:
+ \12701 = b[927:896];
+ 30'b1?????????????????????????????:
+ \12701 = b[959:928];
+ default:
+ \12701 = a;
+ endcase
+ endfunction
+ assign _0780_ = \12701 (32'd0, { 160'h0000000000000000000000000000000000000000, _0724_[115:84], 64'h0000000000000000, c_in[31:0], 128'h00000000000000000000000000000000, _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0012_[2], _0012_[0], _0012_[3], _0012_[1], _0500_[40:9], 225'h000000000000000000000000000000000000000000000000000000000, _0320_, 3'h0, _0320_, 3'h0, _0320_, 3'h0, _0320_, 3'h0, _0320_, 3'h0, _0320_, 3'h0, _0320_, 3'h0, _0320_, 3'h0, _0294_, 3'h0, _0294_, 3'h0, _0294_, 3'h0, _0294_, 3'h0, _0294_, 3'h0, _0294_, 3'h0, _0294_, 3'h0, _0294_, 34'h000000000, _0213_[40:9], 128'h00000000000000000000000000000000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [5:0] \12706 ;
+ input [5:0] a;
+ input [179:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12706 = b[5:0];
+ 30'b????????????????????????????1?:
+ \12706 = b[11:6];
+ 30'b???????????????????????????1??:
+ \12706 = b[17:12];
+ 30'b??????????????????????????1???:
+ \12706 = b[23:18];
+ 30'b?????????????????????????1????:
+ \12706 = b[29:24];
+ 30'b????????????????????????1?????:
+ \12706 = b[35:30];
+ 30'b???????????????????????1??????:
+ \12706 = b[41:36];
+ 30'b??????????????????????1???????:
+ \12706 = b[47:42];
+ 30'b?????????????????????1????????:
+ \12706 = b[53:48];
+ 30'b????????????????????1?????????:
+ \12706 = b[59:54];
+ 30'b???????????????????1??????????:
+ \12706 = b[65:60];
+ 30'b??????????????????1???????????:
+ \12706 = b[71:66];
+ 30'b?????????????????1????????????:
+ \12706 = b[77:72];
+ 30'b????????????????1?????????????:
+ \12706 = b[83:78];
+ 30'b???????????????1??????????????:
+ \12706 = b[89:84];
+ 30'b??????????????1???????????????:
+ \12706 = b[95:90];
+ 30'b?????????????1????????????????:
+ \12706 = b[101:96];
+ 30'b????????????1?????????????????:
+ \12706 = b[107:102];
+ 30'b???????????1??????????????????:
+ \12706 = b[113:108];
+ 30'b??????????1???????????????????:
+ \12706 = b[119:114];
+ 30'b?????????1????????????????????:
+ \12706 = b[125:120];
+ 30'b????????1?????????????????????:
+ \12706 = b[131:126];
+ 30'b???????1??????????????????????:
+ \12706 = b[137:132];
+ 30'b??????1???????????????????????:
+ \12706 = b[143:138];
+ 30'b?????1????????????????????????:
+ \12706 = b[149:144];
+ 30'b????1?????????????????????????:
+ \12706 = b[155:150];
+ 30'b???1??????????????????????????:
+ \12706 = b[161:156];
+ 30'b??1???????????????????????????:
+ \12706 = b[167:162];
+ 30'b?1????????????????????????????:
+ \12706 = b[173:168];
+ 30'b1?????????????????????????????:
+ \12706 = b[179:174];
+ default:
+ \12706 = a;
+ endcase
+ endfunction
+ assign _0781_ = \12706 ({ _0012_, 1'h0 }, { _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0724_[121:116], _0718_, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0214_[5:0], _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0, _0012_, 1'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [71:0] \12710 ;
+ input [71:0] a;
+ input [2159:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12710 = b[71:0];
+ 30'b????????????????????????????1?:
+ \12710 = b[143:72];
+ 30'b???????????????????????????1??:
+ \12710 = b[215:144];
+ 30'b??????????????????????????1???:
+ \12710 = b[287:216];
+ 30'b?????????????????????????1????:
+ \12710 = b[359:288];
+ 30'b????????????????????????1?????:
+ \12710 = b[431:360];
+ 30'b???????????????????????1??????:
+ \12710 = b[503:432];
+ 30'b??????????????????????1???????:
+ \12710 = b[575:504];
+ 30'b?????????????????????1????????:
+ \12710 = b[647:576];
+ 30'b????????????????????1?????????:
+ \12710 = b[719:648];
+ 30'b???????????????????1??????????:
+ \12710 = b[791:720];
+ 30'b??????????????????1???????????:
+ \12710 = b[863:792];
+ 30'b?????????????????1????????????:
+ \12710 = b[935:864];
+ 30'b????????????????1?????????????:
+ \12710 = b[1007:936];
+ 30'b???????????????1??????????????:
+ \12710 = b[1079:1008];
+ 30'b??????????????1???????????????:
+ \12710 = b[1151:1080];
+ 30'b?????????????1????????????????:
+ \12710 = b[1223:1152];
+ 30'b????????????1?????????????????:
+ \12710 = b[1295:1224];
+ 30'b???????????1??????????????????:
+ \12710 = b[1367:1296];
+ 30'b??????????1???????????????????:
+ \12710 = b[1439:1368];
+ 30'b?????????1????????????????????:
+ \12710 = b[1511:1440];
+ 30'b????????1?????????????????????:
+ \12710 = b[1583:1512];
+ 30'b???????1??????????????????????:
+ \12710 = b[1655:1584];
+ 30'b??????1???????????????????????:
+ \12710 = b[1727:1656];
+ 30'b?????1????????????????????????:
+ \12710 = b[1799:1728];
+ 30'b????1?????????????????????????:
+ \12710 = b[1871:1800];
+ 30'b???1??????????????????????????:
+ \12710 = b[1943:1872];
+ 30'b??1???????????????????????????:
+ \12710 = b[2015:1944];
+ 30'b?1????????????????????????????:
+ \12710 = b[2087:2016];
+ 30'b1?????????????????????????????:
+ \12710 = b[2159:2088];
+ default:
+ \12710 = a;
+ endcase
+ endfunction
+ assign _0782_ = \12710 ({ _0083_, 8'h44 }, { _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0724_[193:122], _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0214_[77:6], _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44, _0083_, 8'h44 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12711 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12711 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12711 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12711 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12711 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12711 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12711 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12711 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12711 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12711 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12711 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12711 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12711 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12711 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12711 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12711 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12711 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12711 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12711 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12711 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12711 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12711 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12711 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12711 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12711 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12711 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12711 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12711 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12711 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12711 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12711 = b[29:29];
+ default:
+ \12711 = a;
+ endcase
+ endfunction
+ assign _0783_ = \12711 (1'h0, 30'h04000000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12712 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12712 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12712 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12712 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12712 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12712 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12712 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12712 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12712 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12712 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12712 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12712 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12712 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12712 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12712 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12712 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12712 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12712 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12712 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12712 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12712 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12712 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12712 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12712 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12712 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12712 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12712 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12712 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12712 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12712 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12712 = b[29:29];
+ default:
+ \12712 = a;
+ endcase
+ endfunction
+ assign _0784_ = \12712 (ctrl[133], { ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], _0384_, ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12713 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12713 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12713 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12713 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12713 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12713 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12713 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12713 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12713 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12713 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12713 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12713 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12713 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12713 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12713 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12713 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12713 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12713 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12713 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12713 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12713 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12713 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12713 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12713 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12713 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12713 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12713 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12713 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12713 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12713 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12713 = b[29:29];
+ default:
+ \12713 = a;
+ endcase
+ endfunction
+ assign _0785_ = \12713 (_0071_, { _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0385_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_, _0071_ }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12714 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12714 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12714 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12714 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12714 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12714 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12714 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12714 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12714 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12714 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12714 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12714 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12714 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12714 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12714 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12714 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12714 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12714 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12714 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12714 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12714 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12714 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12714 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12714 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12714 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12714 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12714 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12714 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12714 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12714 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12714 = b[29:29];
+ default:
+ \12714 = a;
+ endcase
+ endfunction
+ assign _0786_ = \12714 (_0072_, { _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0386_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_, _0072_ }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12715 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12715 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12715 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12715 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12715 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12715 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12715 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12715 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12715 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12715 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12715 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12715 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12715 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12715 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12715 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12715 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12715 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12715 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12715 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12715 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12715 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12715 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12715 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12715 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12715 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12715 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12715 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12715 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12715 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12715 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12715 = b[29:29];
+ default:
+ \12715 = a;
+ endcase
+ endfunction
+ assign _0787_ = \12715 (_0073_, { _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0387_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_, _0073_ }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [63:0] \12716 ;
+ input [63:0] a;
+ input [1919:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12716 = b[63:0];
+ 30'b????????????????????????????1?:
+ \12716 = b[127:64];
+ 30'b???????????????????????????1??:
+ \12716 = b[191:128];
+ 30'b??????????????????????????1???:
+ \12716 = b[255:192];
+ 30'b?????????????????????????1????:
+ \12716 = b[319:256];
+ 30'b????????????????????????1?????:
+ \12716 = b[383:320];
+ 30'b???????????????????????1??????:
+ \12716 = b[447:384];
+ 30'b??????????????????????1???????:
+ \12716 = b[511:448];
+ 30'b?????????????????????1????????:
+ \12716 = b[575:512];
+ 30'b????????????????????1?????????:
+ \12716 = b[639:576];
+ 30'b???????????????????1??????????:
+ \12716 = b[703:640];
+ 30'b??????????????????1???????????:
+ \12716 = b[767:704];
+ 30'b?????????????????1????????????:
+ \12716 = b[831:768];
+ 30'b????????????????1?????????????:
+ \12716 = b[895:832];
+ 30'b???????????????1??????????????:
+ \12716 = b[959:896];
+ 30'b??????????????1???????????????:
+ \12716 = b[1023:960];
+ 30'b?????????????1????????????????:
+ \12716 = b[1087:1024];
+ 30'b????????????1?????????????????:
+ \12716 = b[1151:1088];
+ 30'b???????????1??????????????????:
+ \12716 = b[1215:1152];
+ 30'b??????????1???????????????????:
+ \12716 = b[1279:1216];
+ 30'b?????????1????????????????????:
+ \12716 = b[1343:1280];
+ 30'b????????1?????????????????????:
+ \12716 = b[1407:1344];
+ 30'b???????1??????????????????????:
+ \12716 = b[1471:1408];
+ 30'b??????1???????????????????????:
+ \12716 = b[1535:1472];
+ 30'b?????1????????????????????????:
+ \12716 = b[1599:1536];
+ 30'b????1?????????????????????????:
+ \12716 = b[1663:1600];
+ 30'b???1??????????????????????????:
+ \12716 = b[1727:1664];
+ 30'b??1???????????????????????????:
+ \12716 = b[1791:1728];
+ 30'b?1????????????????????????????:
+ \12716 = b[1855:1792];
+ 30'b1?????????????????????????????:
+ \12716 = b[1919:1856];
+ default:
+ \12716 = a;
+ endcase
+ endfunction
+ assign _0788_ = \12716 (_0069_, { _0069_, _0069_, _0069_, _0074_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0069_, _0215_, _0069_, _0069_, _0128_, _0069_ }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12717 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12717 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12717 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12717 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12717 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12717 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12717 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12717 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12717 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12717 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12717 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12717 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12717 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12717 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12717 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12717 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12717 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12717 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12717 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12717 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12717 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12717 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12717 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12717 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12717 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12717 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12717 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12717 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12717 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12717 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12717 = b[29:29];
+ default:
+ \12717 = a;
+ endcase
+ endfunction
+ assign _0789_ = \12717 (1'h0, 30'h30002000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12718 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12718 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12718 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12718 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12718 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12718 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12718 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12718 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12718 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12718 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12718 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12718 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12718 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12718 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12718 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12718 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12718 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12718 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12718 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12718 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12718 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12718 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12718 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12718 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12718 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12718 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12718 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12718 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12718 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12718 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12718 = b[29:29];
+ default:
+ \12718 = a;
+ endcase
+ endfunction
+ assign _0790_ = \12718 (1'h1, { 27'h0000000, _0134_, 2'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12719 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12719 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12719 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12719 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12719 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12719 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12719 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12719 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12719 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12719 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12719 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12719 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12719 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12719 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12719 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12719 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12719 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12719 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12719 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12719 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12719 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12719 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12719 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12719 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12719 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12719 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12719 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12719 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12719 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12719 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12719 = b[29:29];
+ default:
+ \12719 = a;
+ endcase
+ endfunction
+ assign _0791_ = \12719 (1'h0, 30'h10000000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12720 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12720 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12720 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12720 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12720 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12720 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12720 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12720 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12720 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12720 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12720 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12720 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12720 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12720 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12720 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12720 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12720 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12720 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12720 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12720 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12720 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12720 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12720 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12720 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12720 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12720 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12720 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12720 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12720 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12720 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12720 = b[29:29];
+ default:
+ \12720 = a;
+ endcase
+ endfunction
+ assign _0792_ = \12720 (1'h0, 30'h20000000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12721 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12721 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12721 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12721 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12721 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12721 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12721 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12721 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12721 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12721 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12721 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12721 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12721 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12721 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12721 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12721 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12721 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12721 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12721 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12721 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12721 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12721 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12721 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12721 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12721 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12721 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12721 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12721 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12721 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12721 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12721 = b[29:29];
+ default:
+ \12721 = a;
+ endcase
+ endfunction
+ assign _0793_ = \12721 (1'h0, 30'h00002000, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [31:0] \12722 ;
+ input [31:0] a;
+ input [959:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12722 = b[31:0];
+ 30'b????????????????????????????1?:
+ \12722 = b[63:32];
+ 30'b???????????????????????????1??:
+ \12722 = b[95:64];
+ 30'b??????????????????????????1???:
+ \12722 = b[127:96];
+ 30'b?????????????????????????1????:
+ \12722 = b[159:128];
+ 30'b????????????????????????1?????:
+ \12722 = b[191:160];
+ 30'b???????????????????????1??????:
+ \12722 = b[223:192];
+ 30'b??????????????????????1???????:
+ \12722 = b[255:224];
+ 30'b?????????????????????1????????:
+ \12722 = b[287:256];
+ 30'b????????????????????1?????????:
+ \12722 = b[319:288];
+ 30'b???????????????????1??????????:
+ \12722 = b[351:320];
+ 30'b??????????????????1???????????:
+ \12722 = b[383:352];
+ 30'b?????????????????1????????????:
+ \12722 = b[415:384];
+ 30'b????????????????1?????????????:
+ \12722 = b[447:416];
+ 30'b???????????????1??????????????:
+ \12722 = b[479:448];
+ 30'b??????????????1???????????????:
+ \12722 = b[511:480];
+ 30'b?????????????1????????????????:
+ \12722 = b[543:512];
+ 30'b????????????1?????????????????:
+ \12722 = b[575:544];
+ 30'b???????????1??????????????????:
+ \12722 = b[607:576];
+ 30'b??????????1???????????????????:
+ \12722 = b[639:608];
+ 30'b?????????1????????????????????:
+ \12722 = b[671:640];
+ 30'b????????1?????????????????????:
+ \12722 = b[703:672];
+ 30'b???????1??????????????????????:
+ \12722 = b[735:704];
+ 30'b??????1???????????????????????:
+ \12722 = b[767:736];
+ 30'b?????1????????????????????????:
+ \12722 = b[799:768];
+ 30'b????1?????????????????????????:
+ \12722 = b[831:800];
+ 30'b???1??????????????????????????:
+ \12722 = b[863:832];
+ 30'b??1???????????????????????????:
+ \12722 = b[895:864];
+ 30'b?1????????????????????????????:
+ \12722 = b[927:896];
+ 30'b1?????????????????????????????:
+ \12722 = b[959:928];
+ default:
+ \12722 = a;
+ endcase
+ endfunction
+ assign _0794_ = \12722 (r[455:424], { r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], _0719_, r[455:424], r[455:424], r[455:424], _0534_, r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424], r[455:424] }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12736 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12736 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12736 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12736 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12736 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12736 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12736 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12736 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12736 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12736 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12736 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12736 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12736 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12736 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12736 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12736 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12736 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12736 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12736 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12736 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12736 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12736 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12736 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12736 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12736 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12736 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12736 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12736 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12736 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12736 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12736 = b[29:29];
+ default:
+ \12736 = a;
+ endcase
+ endfunction
+ assign _0795_ = \12736 (1'h0, { 4'h0, _0740_, rotator_result[0], _0720_[0], 2'h0, _0619_[0], _0535_[0], ctrl[128], _0516_[0], 2'h0, _0393_[0], 2'h0, _0371_[0], _0353_[0], 1'h0, logical_result[0], 2'h0, _0226_[0], _0032_[0], 4'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [2:0] \12751 ;
+ input [2:0] a;
+ input [89:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12751 = b[2:0];
+ 30'b????????????????????????????1?:
+ \12751 = b[5:3];
+ 30'b???????????????????????????1??:
+ \12751 = b[8:6];
+ 30'b??????????????????????????1???:
+ \12751 = b[11:9];
+ 30'b?????????????????????????1????:
+ \12751 = b[14:12];
+ 30'b????????????????????????1?????:
+ \12751 = b[17:15];
+ 30'b???????????????????????1??????:
+ \12751 = b[20:18];
+ 30'b??????????????????????1???????:
+ \12751 = b[23:21];
+ 30'b?????????????????????1????????:
+ \12751 = b[26:24];
+ 30'b????????????????????1?????????:
+ \12751 = b[29:27];
+ 30'b???????????????????1??????????:
+ \12751 = b[32:30];
+ 30'b??????????????????1???????????:
+ \12751 = b[35:33];
+ 30'b?????????????????1????????????:
+ \12751 = b[38:36];
+ 30'b????????????????1?????????????:
+ \12751 = b[41:39];
+ 30'b???????????????1??????????????:
+ \12751 = b[44:42];
+ 30'b??????????????1???????????????:
+ \12751 = b[47:45];
+ 30'b?????????????1????????????????:
+ \12751 = b[50:48];
+ 30'b????????????1?????????????????:
+ \12751 = b[53:51];
+ 30'b???????????1??????????????????:
+ \12751 = b[56:54];
+ 30'b??????????1???????????????????:
+ \12751 = b[59:57];
+ 30'b?????????1????????????????????:
+ \12751 = b[62:60];
+ 30'b????????1?????????????????????:
+ \12751 = b[65:63];
+ 30'b???????1??????????????????????:
+ \12751 = b[68:66];
+ 30'b??????1???????????????????????:
+ \12751 = b[71:69];
+ 30'b?????1????????????????????????:
+ \12751 = b[74:72];
+ 30'b????1?????????????????????????:
+ \12751 = b[77:75];
+ 30'b???1??????????????????????????:
+ \12751 = b[80:78];
+ 30'b??1???????????????????????????:
+ \12751 = b[83:81];
+ 30'b?1????????????????????????????:
+ \12751 = b[86:84];
+ 30'b1?????????????????????????????:
+ \12751 = b[89:87];
+ default:
+ \12751 = a;
+ endcase
+ endfunction
+ assign _0796_ = \12751 (3'h0, { 12'h000, _0741_[2:0], rotator_result[3:1], _0720_[3:1], 6'h00, _0619_[3:1], _0535_[3:1], ctrl[131:129], _0516_[3:1], 6'h00, _0393_[3:1], 6'h00, _0371_[3:1], _0353_[3:1], 3'h0, logical_result[3:1], 6'h00, _0226_[3:1], _0032_[3:1], 12'h000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12765 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12765 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12765 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12765 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12765 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12765 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12765 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12765 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12765 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12765 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12765 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12765 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12765 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12765 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12765 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12765 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12765 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12765 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12765 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12765 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12765 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12765 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12765 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12765 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12765 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12765 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12765 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12765 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12765 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12765 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12765 = b[119:116];
+ default:
+ \12765 = a;
+ endcase
+ endfunction
+ assign _0797_ = \12765 (4'h0, { 16'h0000, _0741_[6:3], rotator_result[7:4], _0720_[7:4], 8'h00, _0619_[7:4], _0535_[7:4], ctrl[135:132], _0516_[7:4], 8'h00, _0393_[7:4], 8'h00, _0371_[7:4], _0353_[7:4], 4'h0, logical_result[7:4], 8'h00, _0230_, _0032_[7:4], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12779 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12779 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12779 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12779 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12779 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12779 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12779 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12779 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12779 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12779 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12779 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12779 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12779 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12779 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12779 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12779 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12779 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12779 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12779 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12779 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12779 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12779 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12779 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12779 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12779 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12779 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12779 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12779 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12779 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12779 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12779 = b[119:116];
+ default:
+ \12779 = a;
+ endcase
+ endfunction
+ assign _0798_ = \12779 (4'h0, { 16'h0000, _0741_[10:7], rotator_result[11:8], _0720_[11:8], 8'h00, _0619_[11:8], _0535_[11:8], ctrl[139:136], _0516_[11:8], 8'h00, _0393_[11:8], 8'h00, _0371_[11:8], _0353_[11:8], 4'h0, logical_result[11:8], 8'h00, _0234_, _0032_[11:8], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12793 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12793 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12793 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12793 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12793 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12793 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12793 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12793 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12793 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12793 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12793 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12793 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12793 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12793 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12793 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12793 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12793 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12793 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12793 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12793 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12793 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12793 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12793 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12793 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12793 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12793 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12793 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12793 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12793 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12793 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12793 = b[119:116];
+ default:
+ \12793 = a;
+ endcase
+ endfunction
+ assign _0799_ = \12793 (4'h0, { 16'h0000, _0741_[14:11], rotator_result[15:12], _0720_[15:12], 8'h00, _0619_[15:12], _0535_[15:12], ctrl[143:140], _0516_[15:12], 8'h00, _0393_[15:12], 8'h00, _0371_[15:12], _0353_[15:12], 4'h0, logical_result[15:12], 8'h00, _0238_, _0032_[15:12], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12807 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12807 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12807 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12807 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12807 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12807 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12807 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12807 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12807 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12807 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12807 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12807 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12807 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12807 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12807 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12807 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12807 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12807 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12807 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12807 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12807 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12807 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12807 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12807 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12807 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12807 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12807 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12807 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12807 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12807 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12807 = b[119:116];
+ default:
+ \12807 = a;
+ endcase
+ endfunction
+ assign _0800_ = \12807 (4'h0, { 16'h0000, _0741_[18:15], rotator_result[19:16], _0720_[19:16], 8'h00, _0619_[19:16], _0535_[19:16], ctrl[147:144], _0516_[19:16], 8'h00, _0393_[19:16], 8'h00, _0371_[19:16], _0353_[19:16], 4'h0, logical_result[19:16], 8'h00, _0242_, _0032_[19:16], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12821 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12821 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12821 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12821 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12821 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12821 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12821 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12821 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12821 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12821 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12821 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12821 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12821 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12821 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12821 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12821 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12821 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12821 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12821 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12821 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12821 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12821 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12821 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12821 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12821 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12821 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12821 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12821 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12821 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12821 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12821 = b[119:116];
+ default:
+ \12821 = a;
+ endcase
+ endfunction
+ assign _0801_ = \12821 (4'h0, { 16'h0000, _0741_[22:19], rotator_result[23:20], _0720_[23:20], 8'h00, _0619_[23:20], _0535_[23:20], ctrl[151:148], _0516_[23:20], 8'h00, _0393_[23:20], 8'h00, _0371_[23:20], _0353_[23:20], 4'h0, logical_result[23:20], 8'h00, _0246_, _0032_[23:20], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12835 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12835 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12835 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12835 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12835 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12835 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12835 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12835 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12835 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12835 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12835 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12835 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12835 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12835 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12835 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12835 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12835 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12835 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12835 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12835 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12835 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12835 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12835 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12835 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12835 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12835 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12835 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12835 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12835 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12835 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12835 = b[119:116];
+ default:
+ \12835 = a;
+ endcase
+ endfunction
+ assign _0802_ = \12835 (4'h0, { 16'h0000, _0741_[26:23], rotator_result[27:24], _0720_[27:24], 8'h00, _0619_[27:24], _0535_[27:24], ctrl[155:152], _0516_[27:24], 8'h00, _0393_[27:24], 8'h00, _0371_[27:24], _0353_[27:24], 4'h0, logical_result[27:24], 8'h00, _0250_, _0032_[27:24], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12849 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12849 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12849 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12849 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12849 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12849 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12849 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12849 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12849 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12849 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12849 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12849 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12849 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12849 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12849 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12849 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12849 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12849 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12849 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12849 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12849 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12849 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12849 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12849 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12849 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12849 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12849 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12849 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12849 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12849 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12849 = b[119:116];
+ default:
+ \12849 = a;
+ endcase
+ endfunction
+ assign _0803_ = \12849 (4'h0, { 16'h0000, _0741_[30:27], rotator_result[31:28], _0720_[31:28], 8'h00, _0619_[31:28], _0535_[31:28], ctrl[159:156], _0516_[31:28], 8'h00, _0393_[31:28], 8'h00, _0371_[31:28], _0353_[31:28], 4'h0, logical_result[31:28], 8'h00, _0254_, _0032_[31:28], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12863 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12863 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12863 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12863 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12863 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12863 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12863 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12863 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12863 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12863 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12863 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12863 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12863 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12863 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12863 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12863 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12863 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12863 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12863 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12863 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12863 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12863 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12863 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12863 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12863 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12863 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12863 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12863 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12863 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12863 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12863 = b[119:116];
+ default:
+ \12863 = a;
+ endcase
+ endfunction
+ assign _0804_ = \12863 (4'h0, { 16'h0000, _0741_[34:31], rotator_result[35:32], _0720_[35:32], 8'h00, _0619_[35:32], _0535_[35:32], ctrl[163:160], _0516_[35:32], 8'h00, _0393_[35:32], 8'h00, _0371_[35:32], _0353_[35:32], 4'h0, logical_result[35:32], 8'h00, _0258_, _0032_[35:32], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12877 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12877 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12877 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12877 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12877 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12877 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12877 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12877 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12877 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12877 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12877 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12877 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12877 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12877 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12877 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12877 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12877 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12877 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12877 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12877 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12877 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12877 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12877 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12877 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12877 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12877 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12877 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12877 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12877 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12877 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12877 = b[119:116];
+ default:
+ \12877 = a;
+ endcase
+ endfunction
+ assign _0805_ = \12877 (4'h0, { 16'h0000, _0741_[38:35], rotator_result[39:36], _0720_[39:36], 8'h00, _0619_[39:36], _0535_[39:36], ctrl[167:164], _0516_[39:36], 8'h00, _0393_[39:36], 8'h00, _0371_[39:36], _0353_[39:36], 4'h0, logical_result[39:36], 8'h00, _0262_, _0032_[39:36], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12891 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12891 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12891 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12891 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12891 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12891 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12891 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12891 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12891 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12891 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12891 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12891 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12891 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12891 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12891 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12891 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12891 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12891 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12891 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12891 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12891 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12891 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12891 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12891 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12891 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12891 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12891 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12891 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12891 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12891 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12891 = b[119:116];
+ default:
+ \12891 = a;
+ endcase
+ endfunction
+ assign _0806_ = \12891 (4'h0, { 16'h0000, _0741_[42:39], rotator_result[43:40], _0720_[43:40], 8'h00, _0619_[43:40], _0535_[43:40], ctrl[171:168], _0516_[43:40], 8'h00, _0393_[43:40], 8'h00, _0371_[43:40], _0353_[43:40], 4'h0, logical_result[43:40], 8'h00, _0266_, _0032_[43:40], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12905 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12905 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12905 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12905 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12905 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12905 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12905 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12905 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12905 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12905 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12905 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12905 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12905 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12905 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12905 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12905 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12905 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12905 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12905 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12905 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12905 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12905 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12905 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12905 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12905 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12905 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12905 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12905 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12905 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12905 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12905 = b[119:116];
+ default:
+ \12905 = a;
+ endcase
+ endfunction
+ assign _0807_ = \12905 (4'h0, { 16'h0000, _0741_[46:43], rotator_result[47:44], _0720_[47:44], 8'h00, _0619_[47:44], _0535_[47:44], ctrl[175:172], _0516_[47:44], 8'h00, _0393_[47:44], 8'h00, _0371_[47:44], _0353_[47:44], 4'h0, logical_result[47:44], 8'h00, _0270_, _0032_[47:44], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12919 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12919 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12919 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12919 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12919 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12919 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12919 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12919 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12919 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12919 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12919 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12919 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12919 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12919 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12919 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12919 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12919 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12919 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12919 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12919 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12919 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12919 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12919 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12919 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12919 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12919 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12919 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12919 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12919 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12919 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12919 = b[119:116];
+ default:
+ \12919 = a;
+ endcase
+ endfunction
+ assign _0808_ = \12919 (4'h0, { 16'h0000, _0741_[50:47], rotator_result[51:48], _0720_[51:48], 8'h00, _0619_[51:48], _0535_[51:48], ctrl[179:176], _0516_[51:48], 8'h00, _0393_[51:48], 8'h00, _0371_[51:48], _0353_[51:48], 4'h0, logical_result[51:48], 8'h00, _0274_, _0032_[51:48], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12933 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12933 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12933 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12933 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12933 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12933 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12933 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12933 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12933 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12933 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12933 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12933 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12933 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12933 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12933 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12933 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12933 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12933 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12933 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12933 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12933 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12933 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12933 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12933 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12933 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12933 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12933 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12933 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12933 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12933 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12933 = b[119:116];
+ default:
+ \12933 = a;
+ endcase
+ endfunction
+ assign _0809_ = \12933 (4'h0, { 16'h0000, _0741_[54:51], rotator_result[55:52], _0720_[55:52], 8'h00, _0619_[55:52], _0535_[55:52], ctrl[183:180], _0516_[55:52], 8'h00, _0393_[55:52], 8'h00, _0371_[55:52], _0353_[55:52], 4'h0, logical_result[55:52], 8'h00, _0278_, _0032_[55:52], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12947 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12947 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12947 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12947 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12947 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12947 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12947 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12947 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12947 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12947 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12947 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12947 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12947 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12947 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12947 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12947 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12947 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12947 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12947 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12947 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12947 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12947 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12947 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12947 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12947 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12947 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12947 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12947 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12947 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12947 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12947 = b[119:116];
+ default:
+ \12947 = a;
+ endcase
+ endfunction
+ assign _0810_ = \12947 (4'h0, { 16'h0000, _0741_[58:55], rotator_result[59:56], _0720_[59:56], 8'h00, _0619_[59:56], _0535_[59:56], ctrl[187:184], _0516_[59:56], 8'h00, _0393_[59:56], 8'h00, _0371_[59:56], _0353_[59:56], 4'h0, logical_result[59:56], 8'h00, _0282_, _0032_[59:56], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [3:0] \12961 ;
+ input [3:0] a;
+ input [119:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12961 = b[3:0];
+ 30'b????????????????????????????1?:
+ \12961 = b[7:4];
+ 30'b???????????????????????????1??:
+ \12961 = b[11:8];
+ 30'b??????????????????????????1???:
+ \12961 = b[15:12];
+ 30'b?????????????????????????1????:
+ \12961 = b[19:16];
+ 30'b????????????????????????1?????:
+ \12961 = b[23:20];
+ 30'b???????????????????????1??????:
+ \12961 = b[27:24];
+ 30'b??????????????????????1???????:
+ \12961 = b[31:28];
+ 30'b?????????????????????1????????:
+ \12961 = b[35:32];
+ 30'b????????????????????1?????????:
+ \12961 = b[39:36];
+ 30'b???????????????????1??????????:
+ \12961 = b[43:40];
+ 30'b??????????????????1???????????:
+ \12961 = b[47:44];
+ 30'b?????????????????1????????????:
+ \12961 = b[51:48];
+ 30'b????????????????1?????????????:
+ \12961 = b[55:52];
+ 30'b???????????????1??????????????:
+ \12961 = b[59:56];
+ 30'b??????????????1???????????????:
+ \12961 = b[63:60];
+ 30'b?????????????1????????????????:
+ \12961 = b[67:64];
+ 30'b????????????1?????????????????:
+ \12961 = b[71:68];
+ 30'b???????????1??????????????????:
+ \12961 = b[75:72];
+ 30'b??????????1???????????????????:
+ \12961 = b[79:76];
+ 30'b?????????1????????????????????:
+ \12961 = b[83:80];
+ 30'b????????1?????????????????????:
+ \12961 = b[87:84];
+ 30'b???????1??????????????????????:
+ \12961 = b[91:88];
+ 30'b??????1???????????????????????:
+ \12961 = b[95:92];
+ 30'b?????1????????????????????????:
+ \12961 = b[99:96];
+ 30'b????1?????????????????????????:
+ \12961 = b[103:100];
+ 30'b???1??????????????????????????:
+ \12961 = b[107:104];
+ 30'b??1???????????????????????????:
+ \12961 = b[111:108];
+ 30'b?1????????????????????????????:
+ \12961 = b[115:112];
+ 30'b1?????????????????????????????:
+ \12961 = b[119:116];
+ default:
+ \12961 = a;
+ endcase
+ endfunction
+ assign _0811_ = \12961 (4'h0, { 16'h0000, _0741_[62:59], rotator_result[63:60], _0720_[63:60], 8'h00, _0619_[63:60], _0535_[63:60], ctrl[191:188], _0516_[63:60], 8'h00, _0393_[63:60], 8'h00, _0371_[63:60], _0353_[63:60], 4'h0, logical_result[63:60], 8'h00, _0284_, _0032_[63:60], 16'h0000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \12973 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \12973 = b[0:0];
+ 30'b????????????????????????????1?:
+ \12973 = b[1:1];
+ 30'b???????????????????????????1??:
+ \12973 = b[2:2];
+ 30'b??????????????????????????1???:
+ \12973 = b[3:3];
+ 30'b?????????????????????????1????:
+ \12973 = b[4:4];
+ 30'b????????????????????????1?????:
+ \12973 = b[5:5];
+ 30'b???????????????????????1??????:
+ \12973 = b[6:6];
+ 30'b??????????????????????1???????:
+ \12973 = b[7:7];
+ 30'b?????????????????????1????????:
+ \12973 = b[8:8];
+ 30'b????????????????????1?????????:
+ \12973 = b[9:9];
+ 30'b???????????????????1??????????:
+ \12973 = b[10:10];
+ 30'b??????????????????1???????????:
+ \12973 = b[11:11];
+ 30'b?????????????????1????????????:
+ \12973 = b[12:12];
+ 30'b????????????????1?????????????:
+ \12973 = b[13:13];
+ 30'b???????????????1??????????????:
+ \12973 = b[14:14];
+ 30'b??????????????1???????????????:
+ \12973 = b[15:15];
+ 30'b?????????????1????????????????:
+ \12973 = b[16:16];
+ 30'b????????????1?????????????????:
+ \12973 = b[17:17];
+ 30'b???????????1??????????????????:
+ \12973 = b[18:18];
+ 30'b??????????1???????????????????:
+ \12973 = b[19:19];
+ 30'b?????????1????????????????????:
+ \12973 = b[20:20];
+ 30'b????????1?????????????????????:
+ \12973 = b[21:21];
+ 30'b???????1??????????????????????:
+ \12973 = b[22:22];
+ 30'b??????1???????????????????????:
+ \12973 = b[23:23];
+ 30'b?????1????????????????????????:
+ \12973 = b[24:24];
+ 30'b????1?????????????????????????:
+ \12973 = b[25:25];
+ 30'b???1??????????????????????????:
+ \12973 = b[26:26];
+ 30'b??1???????????????????????????:
+ \12973 = b[27:27];
+ 30'b?1????????????????????????????:
+ \12973 = b[28:28];
+ 30'b1?????????????????????????????:
+ \12973 = b[29:29];
+ default:
+ \12973 = a;
+ endcase
+ endfunction
+ assign _0812_ = \12973 (1'h0, { 6'h01, _0721_, 11'h1e4, _0372_, _0354_, 5'h09, _0216_, 4'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13003 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13003 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13003 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13003 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13003 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13003 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13003 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13003 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13003 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13003 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13003 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13003 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13003 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13003 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13003 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13003 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13003 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13003 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13003 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13003 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13003 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13003 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13003 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13003 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13003 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13003 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13003 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13003 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13003 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13003 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13003 = b[29:29];
+ default:
+ \13003 = a;
+ endcase
+ endfunction
+ assign _0813_ = \13003 (1'h0, { 25'h0000000, _0217_, 2'h0, _0129_, 1'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13005 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13005 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13005 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13005 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13005 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13005 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13005 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13005 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13005 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13005 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13005 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13005 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13005 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13005 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13005 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13005 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13005 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13005 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13005 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13005 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13005 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13005 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13005 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13005 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13005 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13005 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13005 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13005 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13005 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13005 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13005 = b[29:29];
+ default:
+ \13005 = a;
+ endcase
+ endfunction
+ assign _0814_ = \13005 (1'h0, { 28'h0000000, _0130_, 1'h0 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13009 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13009 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13009 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13009 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13009 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13009 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13009 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13009 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13009 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13009 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13009 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13009 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13009 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13009 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13009 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13009 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13009 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13009 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13009 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13009 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13009 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13009 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13009 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13009 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13009 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13009 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13009 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13009 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13009 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13009 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13009 = b[29:29];
+ default:
+ \13009 = a;
+ endcase
+ endfunction
+ assign _0815_ = \13009 (1'h0, { 6'h00, _0722_, 3'h0, _0536_, 16'h0000, _0135_, _0131_, 1'h1 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13015 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13015 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13015 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13015 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13015 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13015 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13015 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13015 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13015 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13015 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13015 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13015 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13015 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13015 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13015 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13015 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13015 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13015 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13015 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13015 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13015 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13015 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13015 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13015 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13015 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13015 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13015 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13015 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13015 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13015 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13015 = b[29:29];
+ default:
+ \13015 = a;
+ endcase
+ endfunction
+ assign _0816_ = \13015 (1'h0, 30'h00001e00, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13019 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13019 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13019 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13019 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13019 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13019 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13019 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13019 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13019 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13019 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13019 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13019 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13019 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13019 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13019 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13019 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13019 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13019 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13019 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13019 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13019 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13019 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13019 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13019 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13019 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13019 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13019 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13019 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13019 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13019 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13019 = b[29:29];
+ default:
+ \13019 = a;
+ endcase
+ endfunction
+ assign _0817_ = \13019 (1'h0, { 18'h00001, _0381_, _0363_, 10'h200 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13023 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13023 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13023 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13023 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13023 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13023 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13023 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13023 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13023 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13023 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13023 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13023 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13023 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13023 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13023 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13023 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13023 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13023 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13023 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13023 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13023 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13023 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13023 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13023 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13023 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13023 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13023 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13023 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13023 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13023 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13023 = b[29:29];
+ default:
+ \13023 = a;
+ endcase
+ endfunction
+ assign _0818_ = \13023 (1'h0, { 19'h00003, e_in[340], e_in[340], 9'h000 }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ function [0:0] \13026 ;
+ input [0:0] a;
+ input [29:0] b;
+ input [29:0] s;
+ (* parallel_case *)
+ casez (s)
+ 30'b?????????????????????????????1:
+ \13026 = b[0:0];
+ 30'b????????????????????????????1?:
+ \13026 = b[1:1];
+ 30'b???????????????????????????1??:
+ \13026 = b[2:2];
+ 30'b??????????????????????????1???:
+ \13026 = b[3:3];
+ 30'b?????????????????????????1????:
+ \13026 = b[4:4];
+ 30'b????????????????????????1?????:
+ \13026 = b[5:5];
+ 30'b???????????????????????1??????:
+ \13026 = b[6:6];
+ 30'b??????????????????????1???????:
+ \13026 = b[7:7];
+ 30'b?????????????????????1????????:
+ \13026 = b[8:8];
+ 30'b????????????????????1?????????:
+ \13026 = b[9:9];
+ 30'b???????????????????1??????????:
+ \13026 = b[10:10];
+ 30'b??????????????????1???????????:
+ \13026 = b[11:11];
+ 30'b?????????????????1????????????:
+ \13026 = b[12:12];
+ 30'b????????????????1?????????????:
+ \13026 = b[13:13];
+ 30'b???????????????1??????????????:
+ \13026 = b[14:14];
+ 30'b??????????????1???????????????:
+ \13026 = b[15:15];
+ 30'b?????????????1????????????????:
+ \13026 = b[16:16];
+ 30'b????????????1?????????????????:
+ \13026 = b[17:17];
+ 30'b???????????1??????????????????:
+ \13026 = b[18:18];
+ 30'b??????????1???????????????????:
+ \13026 = b[19:19];
+ 30'b?????????1????????????????????:
+ \13026 = b[20:20];
+ 30'b????????1?????????????????????:
+ \13026 = b[21:21];
+ 30'b???????1??????????????????????:
+ \13026 = b[22:22];
+ 30'b??????1???????????????????????:
+ \13026 = b[23:23];
+ 30'b?????1????????????????????????:
+ \13026 = b[24:24];
+ 30'b????1?????????????????????????:
+ \13026 = b[25:25];
+ 30'b???1??????????????????????????:
+ \13026 = b[26:26];
+ 30'b??1???????????????????????????:
+ \13026 = b[27:27];
+ 30'b?1????????????????????????????:
+ \13026 = b[28:28];
+ 30'b1?????????????????????????????:
+ \13026 = b[29:29];
+ default:
+ \13026 = a;
+ endcase
+ endfunction
+ assign _0819_ = \13026 (_0086_, { _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, 1'h0, _0382_, _0364_, _0348_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_, _0086_ }, { _0754_, _0749_, _0744_, _0743_, _0742_, _0735_, _0723_, _0708_, _0696_, _0620_, _0537_, _0518_, _0517_, _0511_, _0501_, _0394_, _0391_, _0390_, _0383_, _0365_, _0349_, _0347_, _0330_, _0304_, _0285_, _0222_, _0147_, _0136_, _0132_, _0127_ });
+ assign _0820_ = e_in[328] & valid_in;
+ assign _0821_ = _0828_ ? e_in[72:9] : ctrl[255:192];
+ assign _0822_ = ~ e_in[379];
+ assign _0823_ = e_in[72:9] + b_in;
+ assign _0824_ = _0818_ ? b_in : _0823_;
+ assign _0825_ = _0822_ ? _0824_ : _0074_;
+ assign _0826_ = _0817_ != e_in[379];
+ assign _0827_ = _0829_ ? 1'h1 : _0783_;
+ assign _0828_ = _0816_ & _0817_;
+ assign _0829_ = _0816_ & _0826_;
+ assign _0830_ = _0816_ ? _0825_ : _0788_;
+ assign _0831_ = ~ _0812_;
+ assign _0832_ = _0831_ ? _0774_ : 1'h0;
+ assign _0833_ = _0837_ ? { _0074_, 8'h41 } : _0782_;
+ assign _0834_ = _0831_ ? _0789_ : 1'h1;
+ assign _0835_ = _0831_ ? { r[337:274], 1'h0 } : { _0074_, 1'h1 };
+ assign _0836_ = e_in[327] ? _0832_ : _0774_;
+ assign _0837_ = e_in[327] & _0831_;
+ assign _0838_ = e_in[327] ? _0834_ : _0789_;
+ assign _0839_ = e_in[327] ? _0835_ : { r[337:274], 1'h0 };
+ assign _0840_ = e_in[2:1] == 2'h2;
+ assign _0841_ = e_in[2:1] == 2'h0;
+ assign _0842_ = _0841_ ? 1'h1 : 1'h0;
+ assign _0843_ = _0840_ ? 1'h1 : 1'h0;
+ assign _0844_ = _0840_ ? 1'h0 : _0842_;
+ assign _0845_ = e_in[8:3] == 6'h3f;
+ assign _0846_ = _0849_ ? 1'h0 : _0086_;
+ assign _0847_ = valid_in ? _0843_ : 1'h0;
+ assign _0848_ = valid_in ? _0844_ : 1'h0;
+ assign _0849_ = valid_in & _0845_;
+ assign _0850_ = _0126_ ? _0755_ : 1'h0;
+ assign _0851_ = _0126_ ? { _0821_, _0770_, _0769_, _0768_, _0767_, _0766_, _0765_, _0764_, _0763_, _0762_, _0761_, _0760_, _0759_, _0758_, _0757_, _0756_ } : { ctrl[255:128], _0064_ };
+ assign _0852_ = _0126_ ? _0771_ : 1'h0;
+ assign _0853_ = _0126_ ? _0772_ : 1'h0;
+ assign _0854_ = _0126_ ? _0773_ : 1'h0;
+ assign _0855_ = _0126_ ? { _0790_, _0838_, _0830_, _0787_, _0786_, _0785_, _0784_, _0827_, _0833_, _0781_, _0780_, _0779_, _0778_, _0777_, _0776_, _0775_[2:1], _0820_, _0836_ } : { 2'h0, _0069_, _0073_, _0072_, _0071_, ctrl[133], 1'h0, _0083_, 8'h44, _0012_, 114'h00000000000000000000000000000, _0085_, 2'h0 };
+ assign _0856_ = _0126_ ? _0794_ : r[455:424];
+ assign _0857_ = _0126_ ? { _0811_, _0810_, _0809_, _0808_, _0807_, _0806_, _0805_, _0804_, _0803_, _0802_, _0801_, _0800_, _0799_, _0798_, _0797_, _0796_, _0795_ } : 64'h0000000000000000;
+ assign _0858_ = _0126_ ? _0812_ : 1'h0;
+ assign _0859_ = _0126_ ? 1'h0 : _0847_;
+ assign _0860_ = _0126_ ? _0813_ : 1'h0;
+ assign _0861_ = _0126_ ? _0814_ : 1'h0;
+ assign _0862_ = _0126_ ? _0815_ : _0848_;
+ assign _0863_ = _0126_ ? _0819_ : _0846_;
+ assign _0864_ = _0124_ ? 1'h0 : _0850_;
+ assign _0865_ = _0124_ ? { ctrl[255:128], _0064_ } : _0851_;
+ assign _0866_ = _0124_ ? 1'h0 : _0852_;
+ assign _0867_ = _0124_ ? 1'h0 : _0853_;
+ assign _0868_ = _0124_ ? 1'h0 : _0854_;
+ assign _0869_ = _0124_ ? { 2'h0, _0069_, _0073_, _0072_, _0071_, ctrl[133], 1'h0, _0083_, 8'h44, _0012_, 114'h00000000000000000000000000000, _0085_, 2'h0 } : _0855_;
+ assign _0870_ = _0124_ ? r[455:424] : _0856_;
+ assign _0871_ = _0124_ ? 64'h0000000000000000 : _0857_;
+ assign _0872_ = _0124_ ? 1'h0 : _0858_;
+ assign _0873_ = _0124_ ? 1'h0 : _0859_;
+ assign _0874_ = _0124_ ? 1'h0 : _0860_;
+ assign _0875_ = _0124_ ? 1'h0 : _0861_;
+ assign _0876_ = _0124_ ? 1'h1 : _0862_;
+ assign _0877_ = _0124_ ? _0086_ : _0863_;
+ assign _0878_ = _0119_ ? 1'h0 : _0864_;
+ assign _0879_ = _0119_ ? { ctrl[255:128], _0064_ } : _0865_;
+ assign _0880_ = _0119_ ? 1'h0 : _0866_;
+ assign _0881_ = _0119_ ? 1'h1 : 1'h0;
+ assign _0882_ = _0119_ ? 1'h0 : _0867_;
+ assign _0883_ = _0119_ ? 1'h0 : _0868_;
+ assign _0884_ = _0119_ ? { _0073_, _0072_, _0071_, ctrl[133], 1'h0, _0083_, 8'h44, _0012_, 114'h00000000000000000000000000000, _0085_, 2'h0 } : _0869_[198:0];
+ assign _0885_ = _0119_ ? 64'h0000000000000700 : _0869_[262:199];
+ assign _0886_ = _0119_ ? 2'h0 : _0869_[264:263];
+ assign _0887_ = _0119_ ? r[455:424] : _0870_;
+ assign _0888_ = _0119_ ? 64'h0000000000000000 : _0871_;
+ assign _0889_ = _0119_ ? 1'h0 : _0872_;
+ assign _0890_ = _0119_ ? 1'h0 : _0873_;
+ assign _0891_ = _0119_ ? 1'h1 : _0874_;
+ assign _0892_ = _0119_ ? 1'h0 : _0875_;
+ assign _0893_ = _0119_ ? 1'h0 : _0876_;
+ assign _0894_ = _0119_ ? _0086_ : _0877_;
+ assign _0895_ = _0110_ ? 1'h0 : _0878_;
+ assign _0896_ = _0110_ ? { ctrl[255:128], _0064_ } : _0879_;
+ assign _0897_ = _0110_ ? 1'h0 : _0882_;
+ assign _0898_ = _0110_ ? 1'h0 : _0883_;
+ assign _0899_ = _0110_ ? { 2'h0, _0069_, _0073_, _0072_, _0071_, ctrl[133], 1'h0, _0083_, 8'h44, _0012_, 114'h00000000000000000000000000000, _0085_, 2'h0 } : { _0886_, _0885_, _0884_ };
+ assign _0900_ = _0110_ ? r[455:424] : _0887_;
+ assign _0901_ = _0110_ ? 64'h0000000000000000 : _0888_;
+ assign _0902_ = _0110_ ? 1'h0 : _0889_;
+ assign _0903_ = _0110_ ? 1'h0 : _0890_;
+ assign _0904_ = _0110_ ? 1'h1 : _0891_;
+ assign _0905_ = _0110_ ? 1'h0 : _0892_;
+ assign _0906_ = _0110_ ? 1'h0 : _0893_;
+ assign _0907_ = _0110_ ? _0086_ : _0894_;
+ assign _0908_ = _0090_ ? 1'h0 : _0895_;
+ assign _0909_ = _0090_ ? { ctrl[255:128], _0064_ } : _0896_;
+ assign _0910_ = _0090_ ? 1'h1 : 1'h0;
+ assign _0911_ = _0090_ ? 1'h0 : _0897_;
+ assign _0912_ = _0090_ ? 1'h0 : _0898_;
+ assign _0913_ = _0090_ ? { _0073_, _0072_, _0071_, ctrl[133], 1'h0, _0083_, 8'h44, _0012_, 114'h00000000000000000000000000000, _0085_, 2'h0 } : _0899_[198:0];
+ assign _0914_ = _0090_ ? 64'h0000000000000d00 : _0899_[262:199];
+ assign _0915_ = _0090_ ? 2'h0 : _0899_[264:263];
+ assign _0916_ = _0090_ ? r[455:424] : _0900_;
+ assign _0917_ = _0090_ ? 64'h0000000000000000 : _0901_;
+ assign _0918_ = _0090_ ? 1'h0 : _0902_;
+ assign _0919_ = _0090_ ? 1'h0 : _0903_;
+ assign _0920_ = _0090_ ? 1'h1 : _0904_;
+ assign _0921_ = _0090_ ? 1'h0 : _0905_;
+ assign _0922_ = _0090_ ? 1'h0 : _0906_;
+ assign _0923_ = _0090_ ? _0086_ : _0907_;
+ assign _0924_ = _0088_ ? 1'h0 : _0908_;
+ assign _0925_ = _0088_ ? _0064_ : _0909_[63:0];
+ assign _0926_ = _0088_ ? 2'h1 : _0909_[65:64];
+ assign _0927_ = _0088_ ? ctrl[131:130] : _0909_[67:66];
+ assign _0928_ = _0088_ ? 2'h0 : _0909_[69:68];
+ assign _0929_ = _0088_ ? ctrl[135:134] : _0909_[71:70];
+ assign _0930_ = _0088_ ? 4'h0 : _0909_[75:72];
+ assign _0931_ = _0088_ ? ctrl[140] : _0909_[76];
+ assign _0932_ = _0088_ ? 3'h0 : _0909_[79:77];
+ assign _0933_ = _0088_ ? ctrl[190:144] : _0909_[126:80];
+ assign _0934_ = _0088_ ? 1'h1 : _0909_[127];
+ assign _0935_ = _0088_ ? ctrl[255:192] : _0909_[191:128];
+ assign _0936_ = _0088_ ? 1'h0 : _0910_;
+ assign _0937_ = _0088_ ? 1'h0 : _0911_;
+ assign _0938_ = _0088_ ? 1'h0 : _0912_;
+ assign _0939_ = _0088_ ? 1'h1 : _0913_[0];
+ assign _0940_ = _0088_ ? r[455:424] : _0916_;
+ assign _0941_ = _0088_ ? 64'h0000000000000000 : _0917_;
+ assign _0942_ = _0088_ ? 1'h0 : _0918_;
+ assign _0943_ = _0088_ ? 1'h0 : _0919_;
+ assign _0944_ = _0088_ ? 1'h0 : _0920_;
+ assign _0945_ = _0088_ ? 1'h0 : _0921_;
+ assign _0946_ = _0088_ ? 1'h0 : _0922_;
+ assign _0947_ = _0088_ ? _0086_ : _0923_;
+ assign _0948_ = r[194] ? 1'h1 : _0939_;
+ assign _0949_ = r[338] | r[340];
+ assign _0950_ = r[338] & multiply_to_x[0];
+ assign _0951_ = r[340] & divider_to_x[0];
+ assign _0952_ = _0950_ | _0951_;
+ assign _0953_ = r[347:342] == 6'h2d;
+ assign _0954_ = r[347:342] == 6'h2c;
+ function [63:0] \13620 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \13620 = b[63:0];
+ 2'b1?:
+ \13620 = b[127:64];
+ default:
+ \13620 = a;
+ endcase
+ endfunction
+ assign _0955_ = \13620 (multiply_to_x[64:1], { multiply_to_x[128:33], multiply_to_x[64:33] }, { _0954_, _0953_ });
+ assign _0956_ = r[338] ? _0955_ : divider_to_x[64:1];
+ assign _0957_ = r[338] ? 1'h0 : divider_to_x[65];
+ assign _0958_ = r[338] & r[354];
+ assign _0959_ = r[359] | _0957_;
+ assign _0960_ = r[354] ? { _0959_, _0957_, _0957_ } : r[359:357];
+ assign _0961_ = _0088_ ? 1'h0 : _0913_[1];
+ assign _0962_ = _0958_ ? { _0961_, _0948_ } : { r[353], 1'h1 };
+ assign _0963_ = _0088_ ? 7'h00 : _0913_[10:4];
+ assign _0964_ = _0958_ ? _0963_ : { 2'h0, r[352:348] };
+ assign _0965_ = _0088_ ? { _0012_, 1'h0 } : _0913_[121:116];
+ assign _0966_ = _0958_ ? _0965_ : { _0960_, r[356:354] };
+ assign _0967_ = _0088_ ? 1'h0 : _0915_[0];
+ assign _0968_ = _0958_ ? 1'h1 : _0967_;
+ assign _0969_ = _0985_ ? 1'h1 : 1'h0;
+ assign _0970_ = _0958_ ? _0942_ : 1'h1;
+ assign _0971_ = _0088_ ? 1'h0 : _0913_[1];
+ assign _0972_ = _0952_ ? _0962_ : { _0971_, _0948_ };
+ assign _0973_ = _0088_ ? 7'h00 : _0913_[10:4];
+ assign _0974_ = _0952_ ? _0964_ : _0973_;
+ assign _0975_ = _0088_ ? { _0012_, 1'h0 } : _0913_[121:116];
+ assign _0976_ = _0952_ ? _0966_ : _0975_;
+ assign _0977_ = _0952_ ? _0968_ : 1'h1;
+ assign _0978_ = _0126_ ? _0791_ : 1'h0;
+ assign _0979_ = _0124_ ? 1'h0 : _0978_;
+ assign _0980_ = _0119_ ? 1'h0 : _0979_;
+ assign _0981_ = _0110_ ? 1'h0 : _0980_;
+ assign _0982_ = _0090_ ? 1'h0 : _0981_;
+ assign _0983_ = _0088_ ? 1'h0 : _0982_;
+ assign _0984_ = _0952_ ? _0983_ : r[338];
+ assign _0985_ = _0952_ & _0958_;
+ assign _0986_ = _0126_ ? _0792_ : 1'h0;
+ assign _0987_ = _0124_ ? 1'h0 : _0986_;
+ assign _0988_ = _0119_ ? 1'h0 : _0987_;
+ assign _0989_ = _0110_ ? 1'h0 : _0988_;
+ assign _0990_ = _0090_ ? 1'h0 : _0989_;
+ assign _0991_ = _0088_ ? 1'h0 : _0990_;
+ assign _0992_ = _0952_ ? _0991_ : r[340];
+ assign _0993_ = _0952_ ? _0956_ : _0941_;
+ assign _0994_ = _0952_ ? _0970_ : _0942_;
+ assign _0995_ = r[359] | multiply_to_x[129];
+ assign _0996_ = _0088_ ? 1'h0 : _0913_[1];
+ assign _0997_ = r[339] ? { r[353], 1'h1 } : { _0996_, _0948_ };
+ assign _0998_ = _0088_ ? 7'h00 : _0913_[10:4];
+ assign _0999_ = r[339] ? { 2'h0, r[352:348] } : _0998_;
+ assign _1000_ = _0088_ ? { _0012_, 1'h0 } : _0913_[121:116];
+ assign _1001_ = r[339] ? { _0995_, multiply_to_x[129], multiply_to_x[129], r[356:354] } : _1000_;
+ assign _1002_ = r[339] ? r[74:11] : _0941_;
+ assign _1003_ = r[339] ? 1'h1 : _0942_;
+ assign _1004_ = _0949_ ? _0972_ : _0997_;
+ assign _1005_ = _0949_ ? _0974_ : _0999_;
+ assign _1006_ = _0949_ ? _0976_ : _1001_;
+ assign _1007_ = _0088_ ? 1'h0 : _0915_[0];
+ assign _1008_ = _0949_ ? _0977_ : _1007_;
+ assign _1009_ = _0126_ ? _0791_ : 1'h0;
+ assign _1010_ = _0124_ ? 1'h0 : _1009_;
+ assign _1011_ = _0119_ ? 1'h0 : _1010_;
+ assign _1012_ = _0110_ ? 1'h0 : _1011_;
+ assign _1013_ = _0090_ ? 1'h0 : _1012_;
+ assign _1014_ = _0088_ ? 1'h0 : _1013_;
+ assign _1015_ = _0126_ ? _0792_ : 1'h0;
+ assign _1016_ = _0124_ ? 1'h0 : _1015_;
+ assign _1017_ = _0119_ ? 1'h0 : _1016_;
+ assign _1018_ = _0110_ ? 1'h0 : _1017_;
+ assign _1019_ = _0090_ ? 1'h0 : _1018_;
+ assign _1020_ = _0088_ ? 1'h0 : _1019_;
+ assign _1021_ = _0949_ ? { _0992_, _0969_, _0984_ } : { _1020_, 1'h0, _1014_ };
+ assign _1022_ = _0949_ ? _0993_ : _1002_;
+ assign _1023_ = _0949_ ? _0994_ : _1003_;
+ assign _1024_ = r[341] ? { r[353], 1'h1 } : _1004_;
+ assign _1025_ = r[341] ? { 2'h0, r[352:348] } : _1005_;
+ assign _1026_ = _0088_ ? 1'h0 : _0913_[116];
+ assign _1027_ = r[341] ? _1026_ : _1006_[0];
+ assign _1028_ = r[341] ? r[359:355] : _1006_[5:1];
+ assign _1029_ = _0088_ ? 1'h0 : _0915_[0];
+ assign _1030_ = r[341] ? _1029_ : _1008_;
+ assign _1031_ = _0126_ ? _0791_ : 1'h0;
+ assign _1032_ = _0124_ ? 1'h0 : _1031_;
+ assign _1033_ = _0119_ ? 1'h0 : _1032_;
+ assign _1034_ = _0110_ ? 1'h0 : _1033_;
+ assign _1035_ = _0090_ ? 1'h0 : _1034_;
+ assign _1036_ = _0088_ ? 1'h0 : _1035_;
+ assign _1037_ = _0126_ ? _0792_ : 1'h0;
+ assign _1038_ = _0124_ ? 1'h0 : _1037_;
+ assign _1039_ = _0119_ ? 1'h0 : _1038_;
+ assign _1040_ = _0110_ ? 1'h0 : _1039_;
+ assign _1041_ = _0090_ ? 1'h0 : _1040_;
+ assign _1042_ = _0088_ ? 1'h0 : _1041_;
+ assign _1043_ = r[341] ? { _1042_, 1'h0, _1036_ } : _1021_;
+ assign _1044_ = r[341] ? countzero_result : _1022_;
+ assign _1045_ = r[341] ? 1'h1 : _1023_;
+ assign _1046_ = r[273] ? 1'h1 : _1024_[0];
+ assign _1047_ = _0088_ ? 1'h0 : _0913_[1];
+ assign _1048_ = r[273] ? _1047_ : _1024_[1];
+ assign _1049_ = _0088_ ? 7'h00 : _0913_[10:4];
+ assign _1050_ = r[273] ? _1049_ : _1025_;
+ assign _1051_ = _0088_ ? { _0012_, 1'h0 } : _0913_[121:116];
+ assign _1052_ = r[273] ? _1051_ : { _1028_, _1027_ };
+ assign _1053_ = _0088_ ? 1'h0 : _0915_[0];
+ assign _1054_ = r[273] ? _1053_ : _1030_;
+ assign _1055_ = _0126_ ? _0791_ : 1'h0;
+ assign _1056_ = _0124_ ? 1'h0 : _1055_;
+ assign _1057_ = _0119_ ? 1'h0 : _1056_;
+ assign _1058_ = _0110_ ? 1'h0 : _1057_;
+ assign _1059_ = _0090_ ? 1'h0 : _1058_;
+ assign _1060_ = _0088_ ? 1'h0 : _1059_;
+ assign _1061_ = _0126_ ? _0792_ : 1'h0;
+ assign _1062_ = _0124_ ? 1'h0 : _1061_;
+ assign _1063_ = _0119_ ? 1'h0 : _1062_;
+ assign _1064_ = _0110_ ? 1'h0 : _1063_;
+ assign _1065_ = _0090_ ? 1'h0 : _1064_;
+ assign _1066_ = _0088_ ? 1'h0 : _1065_;
+ assign _1067_ = r[273] ? { _1066_, 1'h0, _1060_ } : _1043_;
+ assign _1068_ = _0088_ ? 1'h0 : _0915_[1];
+ assign _1069_ = _0126_ ? _0839_ : { r[337:274], 1'h0 };
+ assign _1070_ = _0124_ ? { r[337:274], 1'h0 } : _1069_;
+ assign _1071_ = _0119_ ? { r[337:274], 1'h0 } : _1070_;
+ assign _1072_ = _0110_ ? { r[337:274], 1'h0 } : _1071_;
+ assign _1073_ = _0090_ ? { r[337:274], 1'h0 } : _1072_;
+ assign _1074_ = _0088_ ? { r[337:274], 1'h0 } : _1073_;
+ assign _1075_ = _0126_ ? { _0012_, e_in[329:328], e_in[77:73], e_in[8:3], _0793_ } : { r[359:342], 1'h0 };
+ assign _1076_ = _0124_ ? { r[359:342], 1'h0 } : _1075_;
+ assign _1077_ = _0119_ ? { r[359:342], 1'h0 } : _1076_;
+ assign _1078_ = _0110_ ? { r[359:342], 1'h0 } : _1077_;
+ assign _1079_ = _0090_ ? { r[359:342], 1'h0 } : _1078_;
+ assign _1080_ = _0088_ ? { r[359:342], 1'h0 } : _1079_;
+ assign _1081_ = r[273] ? r[74:11] : _1044_;
+ assign _1082_ = r[273] ? _0942_ : _1045_;
+ assign _1083_ = _0946_ | 1'h0;
+ assign _1084_ = _1083_ ? 1'h1 : 1'h0;
+ assign _1085_ = _0088_ ? _0069_ : _0914_;
+ assign _1086_ = _1083_ ? 64'h0000000000000700 : _1085_;
+ assign _1087_ = _0088_ ? { _0073_, _0072_, _0071_, ctrl[133], 1'h0 } : _0913_[198:194];
+ assign _1088_ = _1083_ ? 1'h1 : _0944_;
+ assign _1089_ = _0088_ ? ctrl[320:257] : _0913_[193:130];
+ assign _1090_ = r[273] ? r[337:274] : _1089_;
+ assign _1091_ = _0945_ ? _0074_ : _1090_;
+ assign _1092_ = _0088_ ? 1'h1 : _0913_[122];
+ assign _1093_ = r[273] ? 1'h1 : _1092_;
+ assign _1094_ = _1088_ ? 1'h1 : _1093_;
+ assign _1095_ = _0088_ ? ctrl[320:257] : _0913_[193:130];
+ assign _1096_ = r[273] ? r[337:274] : _1095_;
+ assign _1097_ = _1088_ ? _1091_ : _1096_;
+ assign _1098_ = _0088_ ? 7'h23 : _0913_[129:123];
+ assign _1099_ = r[273] ? 7'h20 : _1098_;
+ assign _1100_ = _0088_ ? 1'h0 : r[266];
+ assign _1101_ = _0947_ ? 1'h1 : _1100_;
+ assign _1102_ = _0088_ ? 1'h0 : r[265];
+ assign _1103_ = _0088_ ? 41'h00000000000 : _0913_[115:75];
+ assign _1104_ = ~ _1088_;
+ assign _1105_ = _1082_ & _1104_;
+ assign _1106_ = _0088_ ? _0085_ : _0913_[2];
+ assign _1107_ = ~ l_in[8];
+ assign _1108_ = ~ l_in[7];
+ assign _1109_ = _1108_ ? 64'h0000000000000300 : 64'h0000000000000380;
+ assign _1110_ = ~ l_in[7];
+ assign _1111_ = _0110_ ? 1'h0 : _0881_;
+ assign _1112_ = _0090_ ? 1'h0 : _1111_;
+ assign _1113_ = _0088_ ? 1'h0 : _1112_;
+ assign _1114_ = _1110_ ? l_in[6:5] : { _1084_, _1113_ };
+ assign _1115_ = _0090_ ? _0109_ : 1'h0;
+ assign _1116_ = _0088_ ? 1'h0 : _1115_;
+ assign _1117_ = _1110_ ? l_in[4] : _1116_;
+ assign _1118_ = _1110_ ? l_in[3] : _0936_;
+ assign _1119_ = _1110_ ? 64'h0000000000000400 : 64'h0000000000000480;
+ assign _1120_ = _0110_ ? 1'h0 : _0881_;
+ assign _1121_ = _0090_ ? 1'h0 : _1120_;
+ assign _1122_ = _0088_ ? 1'h0 : _1121_;
+ assign _1123_ = _1107_ ? { _1084_, _1122_ } : _1114_;
+ assign _1124_ = _0090_ ? _0109_ : 1'h0;
+ assign _1125_ = _0088_ ? 1'h0 : _1124_;
+ assign _1126_ = _1107_ ? _1125_ : _1117_;
+ assign _1127_ = _1107_ ? _0936_ : _1118_;
+ assign _1128_ = _1107_ ? _1109_ : _1119_;
+ assign _1129_ = _0110_ ? 1'h0 : _0881_;
+ assign _1130_ = _0090_ ? 1'h0 : _1129_;
+ assign _1131_ = _0088_ ? 1'h0 : _1130_;
+ assign _1132_ = l_in[2] ? { _1084_, _1131_ } : _1123_;
+ assign _1133_ = _0090_ ? _0109_ : 1'h0;
+ assign _1134_ = _0088_ ? 1'h0 : _1133_;
+ assign _1135_ = l_in[2] ? _1134_ : _1126_;
+ assign _1136_ = l_in[2] ? _0936_ : _1127_;
+ assign _1137_ = l_in[2] ? 64'h0000000000000600 : _1128_;
+ assign _1138_ = _0110_ ? 1'h0 : _0881_;
+ assign _1139_ = _0090_ ? 1'h0 : _1138_;
+ assign _1140_ = _0088_ ? 1'h0 : _1139_;
+ assign _1141_ = l_in[1] ? _1132_ : { _1084_, _1140_ };
+ assign _1142_ = _0090_ ? _0109_ : 1'h0;
+ assign _1143_ = _0088_ ? 1'h0 : _1142_;
+ assign _1144_ = l_in[1] ? _1135_ : _1143_;
+ assign _1145_ = l_in[1] ? _1136_ : _0936_;
+ assign _1146_ = _0110_ ? 1'h0 : _0880_;
+ assign _1147_ = _0090_ ? 1'h0 : _1146_;
+ assign _1148_ = _0088_ ? 1'h0 : _1147_;
+ assign _1149_ = _0090_ ? _0108_ : 1'h0;
+ assign _1150_ = _0088_ ? 1'h0 : _1149_;
+ assign _1151_ = l_in[1] ? 8'h45 : { _1099_, _1094_ };
+ assign _1152_ = l_in[1] ? _1137_ : _1086_;
+ assign _1153_ = _1088_ | l_in[1];
+ assign _1154_ = _1153_ ? 1'h1 : 1'h0;
+ assign _1155_ = _1153_ ? 5'h05 : _1087_;
+ assign _1156_ = _1155_[0] ? 1'h0 : _1046_;
+ assign _1157_ = _1155_[0] ? 1'h1 : _1054_;
+ assign _1158_ = e_in[375] ~^ ctrl[128];
+ assign _1159_ = e_in[370:365] == 6'h1f;
+ assign _1160_ = e_in[349:348] == 2'h3;
+ assign _1161_ = _1159_ & _1160_;
+ assign _1162_ = e_in[344:340] == 5'h15;
+ assign _1163_ = _1161_ & _1162_;
+ assign _1164_ = _1163_ ? 1'h1 : 1'h0;
+ assign _1165_ = ~ ctrl[142];
+ assign _1166_ = ~ ctrl[191];
+ assign _1179_ = _0355_[4] ? _1178_ : _1177_;
+ assign _1190_ = _0373_[4] ? _1189_ : _1188_;
+ assign _1201_ = _0392_[4] ? _1200_ : _1199_;
+ assign _1212_ = _0422_[4] ? _1211_ : _1210_;
+ assign _1223_ = _0423_[4] ? _1222_ : _1221_;
+ assign _1226_ = _0424_[0] ? e_in[349] : e_in[348];
+ assign _1227_ = _0424_[2] ? _1225_ : _1224_;
+ assign _1228_ = _0424_[3] ? _1226_ : _1227_;
+ assign _1239_ = _0737_[4] ? _1238_ : _1237_;
+ assign _1250_ = _0738_[4] ? _1249_ : _1248_;
+ assign _0000_ = 1'h1 & e_in[286];
+ assign a_in = _0000_ ? r[74:11] : e_in[157:94];
+ assign _0001_ = 1'h1 & e_in[287];
+ assign b_in = _0001_ ? r[74:11] : e_in[221:158];
+ assign _0002_ = 1'h1 & e_in[288];
+ assign c_in = _0002_ ? r[74:11] : e_in[285:222];
+ assign _0003_ = l_in[0] | r[263];
+ assign _0004_ = _0003_ | fp_in[0];
+ assign _0005_ = ~ _0004_;
+ assign valid_in = e_in[0] & _0005_;
+ assign _0006_ = rst ? 456'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { _0940_, _0084_, _1080_, _1067_, _1074_, _0087_, _1101_, _1102_, _1068_, _1157_, _1152_, _1155_, _1097_, _1151_, _1052_, _1103_, _1081_, _1050_, _1105_, _1106_, _1048_, _1156_ };
+ assign _0007_ = rst ? ctrl[127:0] : { _0925_, _0063_ };
+ assign _0008_ = rst ? 64'h8000000000000001 : { _0934_, _0933_, _0932_, _0931_, _0930_, _0929_, _0928_, _0927_, _0926_ };
+ assign _0009_ = rst ? ctrl[255:192] : _0935_;
+ assign _0010_ = rst ? 1'h0 : _1154_;
+ assign _0011_ = rst ? ctrl[320:257] : { ctrl[191:159], _1145_, 1'h0, _1144_, _1150_, ctrl[154:150], 2'h0, _1141_, _1148_, 1'h0, ctrl[143:128] };
+ always @(posedge clk)
+ r <= _0006_;
+ always @(posedge clk)
+ ctrl <= { _0011_, _0010_, _0009_, _0008_, _0007_ };
+ zero_counter countzero_0 (
+ .clk(clk),
+ .count_right(e_in[349]),
+ .is_32bit(e_in[337]),
+ .result(countzero_result),
+ .rs(c_in)
+ );
+ divider divider_0 (
+ .clk(clk),
+ .d_in({ _0054_, _0044_, _0062_, e_in[337], e_in[338], _0061_, _0938_ }),
+ .d_out(divider_to_x),
+ .rst(rst)
+ );
+ logical logical_0 (
+ .datalen(e_in[374:371]),
+ .invert_in(e_in[330]),
+ .invert_out(e_in[331]),
+ .op(e_in[8:3]),
+ .rb(b_in),
+ .result(logical_result),
+ .rs(c_in)
+ );
+ multiply_4 multiply_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .clk(clk),
+ .m_in({ _0051_, e_in[337], _0050_, _0060_, _0937_ }),
+ .m_out(multiply_to_x)
+ );
+ random random_0 (
+ .clk(clk),
+ .data(random_cond),
+ .err(random_err),
+ .raw(random_raw)
+ );
+ rotator rotator_0 (
+ .arith(e_in[338]),
+ .carry_out(rotator_carry),
+ .clear_left(rot_clear_left),
+ .clear_right(rot_clear_right),
+ .insn(e_in[370:339]),
+ .is_32bit(e_in[337]),
+ .ra(a_in),
+ .result(rotator_result),
+ .right_shift(right_shift),
+ .rs(c_in),
+ .shift(b_in[6:0]),
+ .sign_ext_rs(rot_sign_ext)
+ );
+ assign flush_out = r[194];
+ assign busy_out = _0004_;
+ assign l_out = { e_in[337], _1166_, _1165_, ctrl[132], e_in[328], e_in[378], _1052_[5:1], e_in[84:80], e_in[377:376], _1158_, _1164_, e_in[374:371], e_in[79:73], c_in, b_in, a_in, e_in[370:339], e_in[72:3], _0943_ };
+ assign f_out = r[262:194];
+ assign fp_out = { e_in[336], e_in[328], e_in[79:73], c_in, b_in, a_in, ctrl[139], ctrl[136], e_in[337], e_in[370:339], e_in[72:3], 1'h0 };
+ assign e_out = r[193:0];
+ assign dbg_msr_out = ctrl[191:128];
+ assign icache_inval = _0924_;
+ assign terminate_out = r[264];
+ assign log_out = 15'hzzzz;
+ assign log_rd_addr = r[455:424];
+endmodule
+
+module fetch1_05c2030ccbceb505e9c9c1e14c8b4fa317497e84(clk, rst, stall_in, flush_in, stop_in, alt_reset_in, e_in, d_in, i_out, log_out);
+ wire [63:0] _00_;
+ wire [31:0] _01_;
+ wire [31:0] _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [63:0] _06_;
+ wire [31:0] _07_;
+ wire [63:0] _08_;
+ wire [64:0] _09_;
+ wire [64:0] _10_;
+ wire _11_;
+ wire [63:0] _12_;
+ wire [2:0] _13_;
+ wire _14_;
+ wire [63:0] _15_;
+ wire _16_;
+ wire [2:0] _17_;
+ wire _18_;
+ wire [63:0] _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ input alt_reset_in;
+ input clk;
+ input [64:0] d_in;
+ input [68:0] e_in;
+ input flush_in;
+ output [69:0] i_out;
+ reg [42:0] log_nia;
+ output [42:0] log_out;
+ reg [69:0] r;
+ reg r_int;
+ wire r_next_int;
+ input rst;
+ input stall_in;
+ input stop_in;
+ always @(posedge clk)
+ r <= { _19_, _18_, stop_in, _17_, _22_ };
+ always @(posedge clk)
+ r_int <= r_next_int;
+ always @(posedge clk)
+ log_nia <= { r[69], r[49:8] };
+ assign _00_ = alt_reset_in ? 64'hfffffffff0000000 : 64'h0000000000000000;
+ assign _01_ = e_in[4] ? 32'd0 : e_in[68:37];
+ assign _02_ = r_int ? 32'd0 : d_in[64:33];
+ assign _03_ = ~ stall_in;
+ assign _04_ = ~ r[4];
+ assign _05_ = ~ r_int;
+ assign _06_ = r[69:6] + 64'h0000000000000004;
+ assign _07_ = r[37:6] + 32'd4;
+ assign _08_ = _05_ ? _06_ : { 32'h00000000, _07_ };
+ assign _09_ = _04_ ? { _08_, 1'h1 } : { r[69:6], 1'h0 };
+ assign _10_ = _03_ ? _09_ : { r[69:6], 1'h0 };
+ assign _11_ = d_in[0] ? 1'h0 : _10_[0];
+ assign _12_ = d_in[0] ? { _02_, d_in[32:3], 2'h0 } : _10_[64:1];
+ assign _13_ = e_in[0] ? e_in[3:1] : r[3:1];
+ assign _14_ = e_in[0] ? 1'h0 : _11_;
+ assign _15_ = e_in[0] ? { _01_, e_in[36:7], 2'h0 } : _12_;
+ assign _16_ = e_in[0] ? e_in[4] : r_int;
+ assign _17_ = rst ? 3'h2 : _13_;
+ assign _18_ = rst ? 1'h0 : _14_;
+ assign _19_ = rst ? _00_ : _15_;
+ assign r_next_int = rst ? 1'h0 : _16_;
+ assign _20_ = ~ rst;
+ assign _21_ = ~ stop_in;
+ assign _22_ = _20_ & _21_;
+ assign i_out = r;
+ assign log_out = log_nia;
+endmodule
+
+module gpr_hazard_1(clk, busy_in, deferred, complete_in, flush_in, issuing, gpr_write_valid_in, gpr_write_in, bypass_avail, gpr_read_valid_in, gpr_read_in, ugpr_write_valid, ugpr_write_reg, stall_out, use_bypass);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire [6:0] _35_;
+ wire [7:0] _36_;
+ wire [6:0] _37_;
+ wire [7:0] _38_;
+ input busy_in;
+ input bypass_avail;
+ input clk;
+ input complete_in;
+ input deferred;
+ input flush_in;
+ input [6:0] gpr_read_in;
+ input gpr_read_valid_in;
+ input [6:0] gpr_write_in;
+ input gpr_write_valid_in;
+ input issuing;
+ reg [33:0] r = 34'h000000000;
+ output stall_out;
+ input [6:0] ugpr_write_reg;
+ input ugpr_write_valid;
+ output use_bypass;
+ always @(posedge clk)
+ r <= { _37_, _34_, _38_, _32_, _35_, _30_, _36_, _28_ };
+ assign _00_ = complete_in ? 1'h0 : r[0];
+ assign _01_ = complete_in ? 1'h0 : r[9];
+ assign _02_ = r[25:19] == gpr_read_in;
+ assign _03_ = r[17] & _02_;
+ assign _04_ = r[18] ? 1'h0 : 1'h1;
+ assign _05_ = r[18] ? 1'h1 : 1'h0;
+ assign _06_ = _03_ ? _04_ : 1'h0;
+ assign _07_ = _03_ ? _05_ : 1'h0;
+ assign _08_ = r[33:27] == gpr_read_in;
+ assign _09_ = r[26] & _08_;
+ assign _10_ = _09_ ? 1'h1 : _06_;
+ assign _11_ = r[8:2] == gpr_read_in;
+ assign _12_ = _00_ & _11_;
+ assign _13_ = r[1] ? _10_ : 1'h1;
+ assign _14_ = _16_ ? 1'h1 : _07_;
+ assign _15_ = _12_ ? _13_ : _10_;
+ assign _16_ = _12_ & r[1];
+ assign _17_ = r[16:10] == gpr_read_in;
+ assign _18_ = _01_ & _17_;
+ assign _19_ = _18_ ? 1'h1 : _15_;
+ assign _20_ = gpr_read_valid_in ? _19_ : 1'h0;
+ assign _21_ = gpr_read_valid_in ? _14_ : 1'h0;
+ assign _22_ = ~ busy_in;
+ assign _23_ = _22_ ? 1'h0 : r[26];
+ assign _24_ = ~ deferred;
+ assign _25_ = _24_ & issuing;
+ assign _26_ = _22_ ? 1'h0 : r[17];
+ assign _27_ = _22_ ? r[17] : _00_;
+ assign _28_ = flush_in ? 1'h0 : _27_;
+ assign _29_ = _22_ ? r[26] : _01_;
+ assign _30_ = flush_in ? 1'h0 : _29_;
+ assign _31_ = _25_ ? gpr_write_valid_in : _26_;
+ assign _32_ = flush_in ? 1'h0 : _31_;
+ assign _33_ = _25_ ? ugpr_write_valid : _23_;
+ assign _34_ = flush_in ? 1'h0 : _33_;
+ assign _35_ = _22_ ? r[33:27] : r[16:10];
+ assign _36_ = _22_ ? r[25:18] : r[8:1];
+ assign _37_ = _25_ ? ugpr_write_reg : r[33:27];
+ assign _38_ = _25_ ? { gpr_write_in, bypass_avail } : r[25:18];
+ assign stall_out = _20_;
+ assign use_bypass = _21_;
+endmodule
+
+
+module loadstore1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst, l_in, d_in, m_in, dc_stall, e_out, l_out, d_out, m_out, log_out);
+ wire [63:0] _000_;
+ wire [224:0] _001_;
+ wire [2:0] _002_;
+ wire [179:0] _003_;
+ wire _004_;
+ wire [1:0] _005_;
+ wire _006_;
+ wire [73:0] _007_;
+ wire [2:0] _008_;
+ wire [2:0] _009_;
+ wire [2:0] _010_;
+ wire [3:0] _011_;
+ wire [2:0] _012_;
+ wire [3:0] _013_;
+ wire [2:0] _014_;
+ wire [3:0] _015_;
+ wire [2:0] _016_;
+ wire [3:0] _017_;
+ wire [2:0] _018_;
+ wire [3:0] _019_;
+ wire [2:0] _020_;
+ wire [3:0] _021_;
+ wire [2:0] _022_;
+ wire [3:0] _023_;
+ wire [2:0] _024_;
+ wire [3:0] _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire [1:0] _044_;
+ wire _045_;
+ wire [1:0] _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire [7:0] _050_;
+ wire _051_;
+ wire _052_;
+ wire [1:0] _053_;
+ wire _054_;
+ wire [1:0] _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire [7:0] _059_;
+ wire _060_;
+ wire _061_;
+ wire [1:0] _062_;
+ wire _063_;
+ wire [1:0] _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire [7:0] _068_;
+ wire _069_;
+ wire _070_;
+ wire [1:0] _071_;
+ wire _072_;
+ wire [1:0] _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire [7:0] _077_;
+ wire _078_;
+ wire _079_;
+ wire [1:0] _080_;
+ wire _081_;
+ wire [1:0] _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire [7:0] _086_;
+ wire _087_;
+ wire _088_;
+ wire [1:0] _089_;
+ wire _090_;
+ wire [1:0] _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire [7:0] _095_;
+ wire _096_;
+ wire _097_;
+ wire [1:0] _098_;
+ wire _099_;
+ wire [1:0] _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire [7:0] _104_;
+ wire _105_;
+ wire _106_;
+ wire [1:0] _107_;
+ wire _108_;
+ wire [1:0] _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire [7:0] _113_;
+ wire _114_;
+ wire [2:0] _115_;
+ wire [2:0] _116_;
+ wire [2:0] _117_;
+ wire [2:0] _118_;
+ wire [2:0] _119_;
+ wire [2:0] _120_;
+ wire [2:0] _121_;
+ wire [2:0] _122_;
+ wire [2:0] _123_;
+ wire [2:0] _124_;
+ wire [2:0] _125_;
+ wire [2:0] _126_;
+ wire [2:0] _127_;
+ wire [2:0] _128_;
+ wire [2:0] _129_;
+ wire [2:0] _130_;
+ wire [2:0] _131_;
+ wire [2:0] _132_;
+ wire [63:0] _133_;
+ wire [60:0] _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire [7:0] _146_;
+ wire [31:0] _147_;
+ wire [31:0] _148_;
+ wire [31:0] _149_;
+ wire _150_;
+ wire _151_;
+ wire [2:0] _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire [2:0] _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire [2:0] _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire [63:0] _167_;
+ wire _168_;
+ wire _169_;
+ wire [2:0] _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire [2:0] _174_;
+ wire [1:0] _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire [4:0] _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire [2:0] _191_;
+ wire [2:0] _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire [1:0] _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire [63:0] _206_;
+ wire [2:0] _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire [1:0] _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire _224_;
+ wire [2:0] _225_;
+ wire _226_;
+ wire [31:0] _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire _233_;
+ wire _234_;
+ wire _235_;
+ wire [7:0] _236_;
+ wire [15:0] _237_;
+ wire [2:0] _238_;
+ wire [2:0] _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire _245_;
+ wire _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire _250_;
+ wire _251_;
+ wire [63:0] _252_;
+ wire [63:0] _253_;
+ wire _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire [63:0] _259_;
+ wire [31:0] _260_;
+ wire [2:0] _261_;
+ wire [95:0] _262_;
+ wire _263_;
+ wire _264_;
+ wire _265_;
+ wire _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire _270_;
+ wire [2:0] _271_;
+ wire [95:0] _272_;
+ wire _273_;
+ wire _274_;
+ wire [63:0] _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire [63:0] _279_;
+ wire _280_;
+ wire _281_;
+ wire _282_;
+ wire [2:0] _283_;
+ wire [2:0] _284_;
+ wire [2:0] _285_;
+ wire _286_;
+ wire _287_;
+ wire _288_;
+ wire [67:0] _289_;
+ wire [218:0] _290_;
+ wire [7:0] _291_;
+ wire _292_;
+ wire [63:0] _293_;
+ wire [63:0] _294_;
+ wire _295_;
+ wire _296_;
+ wire _297_;
+ wire _298_;
+ wire [71:0] _299_;
+ wire [71:0] _300_;
+ wire [71:0] _301_;
+ wire _302_;
+ wire _303_;
+ wire _304_;
+ wire _305_;
+ wire _306_;
+ wire _307_;
+ wire [31:0] _308_;
+ wire [31:0] _309_;
+ wire [95:0] _310_;
+ wire [95:0] _311_;
+ wire [72:0] _312_;
+ wire [49:0] _313_;
+ wire [7:0] _314_;
+ wire [7:0] _315_;
+ wire [7:0] _316_;
+ wire [7:0] _317_;
+ wire [7:0] _318_;
+ wire [7:0] _319_;
+ wire [7:0] _320_;
+ wire [7:0] _321_;
+ wire [7:0] _322_;
+ wire [7:0] _323_;
+ wire [7:0] _324_;
+ wire [7:0] _325_;
+ wire [7:0] _326_;
+ wire [7:0] _327_;
+ wire [7:0] _328_;
+ wire [7:0] _329_;
+ wire [7:0] _330_;
+ wire [7:0] _331_;
+ wire [7:0] _332_;
+ wire [7:0] _333_;
+ wire [7:0] _334_;
+ wire [7:0] _335_;
+ wire [7:0] _336_;
+ wire [7:0] _337_;
+ wire [7:0] _338_;
+ wire [7:0] _339_;
+ wire [7:0] _340_;
+ wire [7:0] _341_;
+ wire [7:0] _342_;
+ wire [7:0] _343_;
+ wire [7:0] _344_;
+ wire [7:0] _345_;
+ wire [7:0] _346_;
+ wire [7:0] _347_;
+ wire [7:0] _348_;
+ wire [7:0] _349_;
+ wire [7:0] _350_;
+ wire [7:0] _351_;
+ wire [7:0] _352_;
+ wire [7:0] _353_;
+ wire [7:0] _354_;
+ wire [7:0] _355_;
+ wire [7:0] _356_;
+ wire [7:0] _357_;
+ wire [7:0] _358_;
+ wire [7:0] _359_;
+ wire [7:0] _360_;
+ wire [7:0] _361_;
+ wire [7:0] _362_;
+ wire [7:0] _363_;
+ wire [7:0] _364_;
+ wire [7:0] _365_;
+ wire [7:0] _366_;
+ wire [7:0] _367_;
+ wire [7:0] _368_;
+ wire [7:0] _369_;
+ wire [7:0] _370_;
+ wire [7:0] _371_;
+ wire [7:0] _372_;
+ wire [7:0] _373_;
+ wire [7:0] _374_;
+ wire [7:0] _375_;
+ wire [7:0] _376_;
+ wire [7:0] _377_;
+ wire [7:0] _378_;
+ wire [7:0] _379_;
+ wire [7:0] _380_;
+ wire [7:0] _381_;
+ wire [7:0] _382_;
+ wire [7:0] _383_;
+ wire [7:0] _384_;
+ wire [7:0] _385_;
+ wire [7:0] _386_;
+ wire [7:0] _387_;
+ wire [7:0] _388_;
+ wire [7:0] _389_;
+ wire [7:0] _390_;
+ wire [7:0] _391_;
+ wire [7:0] _392_;
+ wire [7:0] _393_;
+ wire [7:0] _394_;
+ wire [7:0] _395_;
+ wire [7:0] _396_;
+ wire [7:0] _397_;
+ wire [7:0] _398_;
+ wire [7:0] _399_;
+ wire [7:0] _400_;
+ wire [7:0] _401_;
+ wire [7:0] _402_;
+ wire [7:0] _403_;
+ wire [7:0] _404_;
+ wire [7:0] _405_;
+ wire [7:0] _406_;
+ wire [7:0] _407_;
+ wire [7:0] _408_;
+ wire [7:0] _409_;
+ wire [7:0] _410_;
+ wire [7:0] _411_;
+ wire [7:0] _412_;
+ wire [7:0] _413_;
+ wire [7:0] _414_;
+ wire [7:0] _415_;
+ wire [7:0] _416_;
+ wire [7:0] _417_;
+ wire [7:0] _418_;
+ wire [7:0] _419_;
+ wire [7:0] _420_;
+ wire [7:0] _421_;
+ wire [7:0] _422_;
+ wire [7:0] _423_;
+ wire [7:0] _424_;
+ wire [7:0] _425_;
+ input clk;
+ input [67:0] d_in;
+ output [142:0] d_out;
+ input dc_stall;
+ output [8:0] e_out;
+ input [325:0] l_in;
+ output [79:0] l_out;
+ output [9:0] log_out;
+ wire [63:0] lsu_sum;
+ input [70:0] m_in;
+ output [144:0] m_out;
+ reg [485:0] r;
+ input rst;
+ assign _362_ = _011_[0] ? d_in[16:9] : d_in[8:1];
+ assign _363_ = _011_[0] ? d_in[48:41] : d_in[40:33];
+ assign _364_ = _013_[0] ? d_in[16:9] : d_in[8:1];
+ assign _365_ = _013_[0] ? d_in[48:41] : d_in[40:33];
+ assign _366_ = _015_[0] ? d_in[16:9] : d_in[8:1];
+ assign _367_ = _015_[0] ? d_in[48:41] : d_in[40:33];
+ assign _368_ = _017_[0] ? d_in[16:9] : d_in[8:1];
+ assign _369_ = _017_[0] ? d_in[48:41] : d_in[40:33];
+ assign _370_ = _019_[0] ? d_in[16:9] : d_in[8:1];
+ assign _371_ = _019_[0] ? d_in[48:41] : d_in[40:33];
+ assign _372_ = _021_[0] ? d_in[16:9] : d_in[8:1];
+ assign _373_ = _021_[0] ? d_in[48:41] : d_in[40:33];
+ assign _374_ = _023_[0] ? d_in[16:9] : d_in[8:1];
+ assign _375_ = _023_[0] ? d_in[48:41] : d_in[40:33];
+ assign _376_ = _025_[0] ? d_in[16:9] : d_in[8:1];
+ assign _377_ = _025_[0] ? d_in[48:41] : d_in[40:33];
+ assign _378_ = _118_[0] ? l_in[246:239] : l_in[238:231];
+ assign _379_ = _118_[0] ? l_in[278:271] : l_in[270:263];
+ assign _380_ = _120_[0] ? l_in[246:239] : l_in[238:231];
+ assign _381_ = _120_[0] ? l_in[278:271] : l_in[270:263];
+ assign _382_ = _122_[0] ? l_in[246:239] : l_in[238:231];
+ assign _383_ = _122_[0] ? l_in[278:271] : l_in[270:263];
+ assign _384_ = _124_[0] ? l_in[246:239] : l_in[238:231];
+ assign _385_ = _124_[0] ? l_in[278:271] : l_in[270:263];
+ assign _386_ = _126_[0] ? l_in[246:239] : l_in[238:231];
+ assign _387_ = _126_[0] ? l_in[278:271] : l_in[270:263];
+ assign _388_ = _128_[0] ? l_in[246:239] : l_in[238:231];
+ assign _389_ = _128_[0] ? l_in[278:271] : l_in[270:263];
+ assign _390_ = _130_[0] ? l_in[246:239] : l_in[238:231];
+ assign _391_ = _130_[0] ? l_in[278:271] : l_in[270:263];
+ assign _392_ = _132_[0] ? l_in[246:239] : l_in[238:231];
+ assign _393_ = _132_[0] ? l_in[278:271] : l_in[270:263];
+ assign _394_ = _011_[0] ? d_in[32:25] : d_in[24:17];
+ assign _395_ = _011_[0] ? d_in[64:57] : d_in[56:49];
+ assign _396_ = _013_[0] ? d_in[32:25] : d_in[24:17];
+ assign _397_ = _013_[0] ? d_in[64:57] : d_in[56:49];
+ assign _398_ = _015_[0] ? d_in[32:25] : d_in[24:17];
+ assign _399_ = _015_[0] ? d_in[64:57] : d_in[56:49];
+ assign _400_ = _017_[0] ? d_in[32:25] : d_in[24:17];
+ assign _401_ = _017_[0] ? d_in[64:57] : d_in[56:49];
+ assign _402_ = _019_[0] ? d_in[32:25] : d_in[24:17];
+ assign _403_ = _019_[0] ? d_in[64:57] : d_in[56:49];
+ assign _404_ = _021_[0] ? d_in[32:25] : d_in[24:17];
+ assign _405_ = _021_[0] ? d_in[64:57] : d_in[56:49];
+ assign _406_ = _023_[0] ? d_in[32:25] : d_in[24:17];
+ assign _407_ = _023_[0] ? d_in[64:57] : d_in[56:49];
+ assign _408_ = _025_[0] ? d_in[32:25] : d_in[24:17];
+ assign _409_ = _025_[0] ? d_in[64:57] : d_in[56:49];
+ assign _410_ = _118_[0] ? l_in[262:255] : l_in[254:247];
+ assign _411_ = _118_[0] ? l_in[294:287] : l_in[286:279];
+ assign _412_ = _120_[0] ? l_in[262:255] : l_in[254:247];
+ assign _413_ = _120_[0] ? l_in[294:287] : l_in[286:279];
+ assign _414_ = _122_[0] ? l_in[262:255] : l_in[254:247];
+ assign _415_ = _122_[0] ? l_in[294:287] : l_in[286:279];
+ assign _416_ = _124_[0] ? l_in[262:255] : l_in[254:247];
+ assign _417_ = _124_[0] ? l_in[294:287] : l_in[286:279];
+ assign _418_ = _126_[0] ? l_in[262:255] : l_in[254:247];
+ assign _419_ = _126_[0] ? l_in[294:287] : l_in[286:279];
+ assign _420_ = _128_[0] ? l_in[262:255] : l_in[254:247];
+ assign _421_ = _128_[0] ? l_in[294:287] : l_in[286:279];
+ assign _422_ = _130_[0] ? l_in[262:255] : l_in[254:247];
+ assign _423_ = _130_[0] ? l_in[294:287] : l_in[286:279];
+ assign _424_ = _132_[0] ? l_in[262:255] : l_in[254:247];
+ assign _425_ = _132_[0] ? l_in[294:287] : l_in[286:279];
+ assign _314_ = _011_[1] ? _394_ : _362_;
+ assign _315_ = _011_[1] ? _395_ : _363_;
+ assign _317_ = _013_[1] ? _396_ : _364_;
+ assign _318_ = _013_[1] ? _397_ : _365_;
+ assign _320_ = _015_[1] ? _398_ : _366_;
+ assign _321_ = _015_[1] ? _399_ : _367_;
+ assign _323_ = _017_[1] ? _400_ : _368_;
+ assign _324_ = _017_[1] ? _401_ : _369_;
+ assign _326_ = _019_[1] ? _402_ : _370_;
+ assign _327_ = _019_[1] ? _403_ : _371_;
+ assign _329_ = _021_[1] ? _404_ : _372_;
+ assign _330_ = _021_[1] ? _405_ : _373_;
+ assign _332_ = _023_[1] ? _406_ : _374_;
+ assign _333_ = _023_[1] ? _407_ : _375_;
+ assign _335_ = _025_[1] ? _408_ : _376_;
+ assign _336_ = _025_[1] ? _409_ : _377_;
+ assign _338_ = _118_[1] ? _410_ : _378_;
+ assign _339_ = _118_[1] ? _411_ : _379_;
+ assign _341_ = _120_[1] ? _412_ : _380_;
+ assign _342_ = _120_[1] ? _413_ : _381_;
+ assign _344_ = _122_[1] ? _414_ : _382_;
+ assign _345_ = _122_[1] ? _415_ : _383_;
+ assign _347_ = _124_[1] ? _416_ : _384_;
+ assign _348_ = _124_[1] ? _417_ : _385_;
+ assign _350_ = _126_[1] ? _418_ : _386_;
+ assign _351_ = _126_[1] ? _419_ : _387_;
+ assign _353_ = _128_[1] ? _420_ : _388_;
+ assign _354_ = _128_[1] ? _421_ : _389_;
+ assign _356_ = _130_[1] ? _422_ : _390_;
+ assign _357_ = _130_[1] ? _423_ : _391_;
+ assign _359_ = _132_[1] ? _424_ : _392_;
+ assign _360_ = _132_[1] ? _425_ : _393_;
+ assign _000_ = l_in[166:103] + l_in[230:167];
+ assign lsu_sum = l_in[0] ? _000_ : 64'h0000000000000000;
+ assign _001_ = rst ? r[224:0] : { _313_[28:0], _206_, _133_, _289_ };
+ assign _002_ = rst ? 3'h0 : _313_[31:29];
+ assign _003_ = rst ? r[407:228] : { _312_[65:0], _311_, _313_[49:32] };
+ assign _004_ = rst ? 1'h0 : _312_[66];
+ assign _005_ = rst ? r[410:409] : _312_[68:67];
+ assign _006_ = rst ? 1'h0 : _312_[69];
+ assign _007_ = rst ? r[485:412] : { r[485:415], _312_[72:70] };
+ always @(posedge clk)
+ r <= { _007_, _006_, _005_, _004_, _003_, _002_, _001_ };
+ assign _008_ = r[205:203] - 3'h1;
+ assign _009_ = r[207] ? _008_ : 3'h0;
+ assign _010_ = 3'h0 ^ _009_;
+ assign _011_ = { 1'h0, _010_ } + { 1'h0, r[6:4] };
+ assign _012_ = 3'h1 ^ _009_;
+ assign _013_ = { 1'h0, _012_ } + { 1'h0, r[6:4] };
+ assign _014_ = 3'h2 ^ _009_;
+ assign _015_ = { 1'h0, _014_ } + { 1'h0, r[6:4] };
+ assign _016_ = 3'h3 ^ _009_;
+ assign _017_ = { 1'h0, _016_ } + { 1'h0, r[6:4] };
+ assign _018_ = 3'h4 ^ _009_;
+ assign _019_ = { 1'h0, _018_ } + { 1'h0, r[6:4] };
+ assign _020_ = 3'h5 ^ _009_;
+ assign _021_ = { 1'h0, _020_ } + { 1'h0, r[6:4] };
+ assign _022_ = 3'h6 ^ _009_;
+ assign _023_ = { 1'h0, _022_ } + { 1'h0, r[6:4] };
+ assign _024_ = 3'h7 ^ _009_;
+ assign _025_ = { 1'h0, _024_ } + { 1'h0, r[6:4] };
+ assign _026_ = r[228] & r[207];
+ assign _027_ = r[206] & r[195];
+ assign _028_ = r[205] & r[163];
+ assign _029_ = _027_ | _028_;
+ assign _030_ = r[204] & r[147];
+ assign _031_ = _029_ | _030_;
+ assign _032_ = r[203] & r[139];
+ assign _033_ = _031_ | _032_;
+ assign _034_ = r[206] & _337_[7];
+ assign _035_ = r[205] & _325_[7];
+ assign _036_ = _034_ | _035_;
+ assign _037_ = r[204] & _319_[7];
+ assign _038_ = _036_ | _037_;
+ assign _039_ = r[203] & _316_[7];
+ assign _040_ = _038_ | _039_;
+ assign _041_ = _026_ ? _033_ : _040_;
+ assign _042_ = $signed(32'd0) < $signed({ 28'h0000000, r[206:203] });
+ assign _043_ = ~ _011_[3];
+ assign _044_ = r[228] ? { 1'h1, _043_ } : 2'h2;
+ assign _045_ = _041_ & r[208];
+ assign _046_ = _042_ ? _044_ : { 1'h0, _045_ };
+ assign _047_ = _046_ == 2'h3;
+ assign _048_ = _046_ == 2'h2;
+ assign _049_ = _046_ == 2'h1;
+ function [7:0] \14974 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \14974 = b[7:0];
+ 3'b?1?:
+ \14974 = b[15:8];
+ 3'b1??:
+ \14974 = b[23:16];
+ default:
+ \14974 = a;
+ endcase
+ endfunction
+ assign _050_ = \14974 (8'h00, { 8'hff, _316_, r[139:132] }, { _049_, _048_, _047_ });
+ assign _051_ = $signed(32'd1) < $signed({ 28'h0000000, r[206:203] });
+ assign _052_ = ~ _013_[3];
+ assign _053_ = r[228] ? { 1'h1, _052_ } : 2'h2;
+ assign _054_ = _041_ & r[208];
+ assign _055_ = _051_ ? _053_ : { 1'h0, _054_ };
+ assign _056_ = _055_ == 2'h3;
+ assign _057_ = _055_ == 2'h2;
+ assign _058_ = _055_ == 2'h1;
+ function [7:0] \15008 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15008 = b[7:0];
+ 3'b?1?:
+ \15008 = b[15:8];
+ 3'b1??:
+ \15008 = b[23:16];
+ default:
+ \15008 = a;
+ endcase
+ endfunction
+ assign _059_ = \15008 (8'h00, { 8'hff, _319_, r[147:140] }, { _058_, _057_, _056_ });
+ assign _060_ = $signed(32'd2) < $signed({ 28'h0000000, r[206:203] });
+ assign _061_ = ~ _015_[3];
+ assign _062_ = r[228] ? { 1'h1, _061_ } : 2'h2;
+ assign _063_ = _041_ & r[208];
+ assign _064_ = _060_ ? _062_ : { 1'h0, _063_ };
+ assign _065_ = _064_ == 2'h3;
+ assign _066_ = _064_ == 2'h2;
+ assign _067_ = _064_ == 2'h1;
+ function [7:0] \15042 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15042 = b[7:0];
+ 3'b?1?:
+ \15042 = b[15:8];
+ 3'b1??:
+ \15042 = b[23:16];
+ default:
+ \15042 = a;
+ endcase
+ endfunction
+ assign _068_ = \15042 (8'h00, { 8'hff, _322_, r[155:148] }, { _067_, _066_, _065_ });
+ assign _069_ = $signed(32'd3) < $signed({ 28'h0000000, r[206:203] });
+ assign _070_ = ~ _017_[3];
+ assign _071_ = r[228] ? { 1'h1, _070_ } : 2'h2;
+ assign _072_ = _041_ & r[208];
+ assign _073_ = _069_ ? _071_ : { 1'h0, _072_ };
+ assign _074_ = _073_ == 2'h3;
+ assign _075_ = _073_ == 2'h2;
+ assign _076_ = _073_ == 2'h1;
+ function [7:0] \15076 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15076 = b[7:0];
+ 3'b?1?:
+ \15076 = b[15:8];
+ 3'b1??:
+ \15076 = b[23:16];
+ default:
+ \15076 = a;
+ endcase
+ endfunction
+ assign _077_ = \15076 (8'h00, { 8'hff, _325_, r[163:156] }, { _076_, _075_, _074_ });
+ assign _078_ = $signed(32'd4) < $signed({ 28'h0000000, r[206:203] });
+ assign _079_ = ~ _019_[3];
+ assign _080_ = r[228] ? { 1'h1, _079_ } : 2'h2;
+ assign _081_ = _041_ & r[208];
+ assign _082_ = _078_ ? _080_ : { 1'h0, _081_ };
+ assign _083_ = _082_ == 2'h3;
+ assign _084_ = _082_ == 2'h2;
+ assign _085_ = _082_ == 2'h1;
+ function [7:0] \15110 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15110 = b[7:0];
+ 3'b?1?:
+ \15110 = b[15:8];
+ 3'b1??:
+ \15110 = b[23:16];
+ default:
+ \15110 = a;
+ endcase
+ endfunction
+ assign _086_ = \15110 (8'h00, { 8'hff, _328_, r[171:164] }, { _085_, _084_, _083_ });
+ assign _087_ = $signed(32'd5) < $signed({ 28'h0000000, r[206:203] });
+ assign _088_ = ~ _021_[3];
+ assign _089_ = r[228] ? { 1'h1, _088_ } : 2'h2;
+ assign _090_ = _041_ & r[208];
+ assign _091_ = _087_ ? _089_ : { 1'h0, _090_ };
+ assign _092_ = _091_ == 2'h3;
+ assign _093_ = _091_ == 2'h2;
+ assign _094_ = _091_ == 2'h1;
+ function [7:0] \15144 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15144 = b[7:0];
+ 3'b?1?:
+ \15144 = b[15:8];
+ 3'b1??:
+ \15144 = b[23:16];
+ default:
+ \15144 = a;
+ endcase
+ endfunction
+ assign _095_ = \15144 (8'h00, { 8'hff, _331_, r[179:172] }, { _094_, _093_, _092_ });
+ assign _096_ = $signed(32'd6) < $signed({ 28'h0000000, r[206:203] });
+ assign _097_ = ~ _023_[3];
+ assign _098_ = r[228] ? { 1'h1, _097_ } : 2'h2;
+ assign _099_ = _041_ & r[208];
+ assign _100_ = _096_ ? _098_ : { 1'h0, _099_ };
+ assign _101_ = _100_ == 2'h3;
+ assign _102_ = _100_ == 2'h2;
+ assign _103_ = _100_ == 2'h1;
+ function [7:0] \15178 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15178 = b[7:0];
+ 3'b?1?:
+ \15178 = b[15:8];
+ 3'b1??:
+ \15178 = b[23:16];
+ default:
+ \15178 = a;
+ endcase
+ endfunction
+ assign _104_ = \15178 (8'h00, { 8'hff, _334_, r[187:180] }, { _103_, _102_, _101_ });
+ assign _105_ = $signed(32'd7) < $signed({ 28'h0000000, r[206:203] });
+ assign _106_ = ~ _025_[3];
+ assign _107_ = r[228] ? { 1'h1, _106_ } : 2'h2;
+ assign _108_ = _041_ & r[208];
+ assign _109_ = _105_ ? _107_ : { 1'h0, _108_ };
+ assign _110_ = _109_ == 2'h3;
+ assign _111_ = _109_ == 2'h2;
+ assign _112_ = _109_ == 2'h1;
+ function [7:0] \15211 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \15211 = b[7:0];
+ 3'b?1?:
+ \15211 = b[15:8];
+ 3'b1??:
+ \15211 = b[23:16];
+ default:
+ \15211 = a;
+ endcase
+ endfunction
+ assign _113_ = \15211 (8'h00, { 8'hff, _337_, r[195:188] }, { _112_, _111_, _110_ });
+ assign _114_ = l_in[0] | 1'h0;
+ assign _115_ = l_in[304:302] - 3'h1;
+ assign _116_ = l_in[307] ? _115_ : 3'h0;
+ assign _117_ = 3'h0 - lsu_sum[2:0];
+ assign _118_ = _117_ ^ _116_;
+ assign _119_ = 3'h1 - lsu_sum[2:0];
+ assign _120_ = _119_ ^ _116_;
+ assign _121_ = 3'h2 - lsu_sum[2:0];
+ assign _122_ = _121_ ^ _116_;
+ assign _123_ = 3'h3 - lsu_sum[2:0];
+ assign _124_ = _123_ ^ _116_;
+ assign _125_ = 3'h4 - lsu_sum[2:0];
+ assign _126_ = _125_ ^ _116_;
+ assign _127_ = 3'h5 - lsu_sum[2:0];
+ assign _128_ = _127_ ^ _116_;
+ assign _129_ = 3'h6 - lsu_sum[2:0];
+ assign _130_ = _129_ ^ _116_;
+ assign _131_ = 3'h7 - lsu_sum[2:0];
+ assign _132_ = _131_ ^ _116_;
+ assign _133_ = _114_ ? { _361_, _358_, _355_, _352_, _349_, _346_, _343_, _340_ } : r[131:68];
+ assign _134_ = r[67:7] + 61'h0000000000000001;
+ assign _135_ = r[409] & d_in[0];
+ assign _136_ = r[410] & m_in[0];
+ assign _137_ = _135_ | _136_;
+ assign _138_ = ~ _137_;
+ assign _139_ = r[408] & _138_;
+ assign _140_ = r[227:225] != 3'h0;
+ assign _141_ = ~ _139_;
+ assign _142_ = _140_ & _141_;
+ assign _143_ = _142_ ? 1'h1 : 1'h0;
+ assign _144_ = r[227:225] == 3'h2;
+ assign _145_ = r[228] | _144_;
+ assign _146_ = _145_ ? r[245:238] : r[237:230];
+ assign _147_ = _145_ ? _134_[60:29] : r[67:36];
+ assign _148_ = r[413] ? 32'd0 : _147_;
+ assign _149_ = _145_ ? { _134_[28:0], 3'h0 } : r[35:4];
+ assign _150_ = r[227:225] == 3'h0;
+ assign _151_ = r[245:238] != 8'h00;
+ assign _152_ = _151_ ? 3'h2 : 3'h3;
+ assign _153_ = r[227:225] == 3'h1;
+ assign _154_ = r[227:225] == 3'h2;
+ assign _155_ = ~ r[0];
+ assign _156_ = d_in[67] ? r[227:225] : 3'h4;
+ assign _157_ = d_in[67] ? 1'h1 : 1'h0;
+ assign _158_ = d_in[67] ? 1'h0 : 1'h1;
+ assign _159_ = d_in[67] ? _155_ : 1'h0;
+ assign _160_ = d_in[67] ? d_in[67] : 1'h0;
+ assign _161_ = d_in[66] ? _156_ : r[227:225];
+ assign _162_ = d_in[66] ? _157_ : 1'h0;
+ assign _163_ = d_in[66] ? _158_ : 1'h0;
+ assign _164_ = d_in[66] ? _159_ : 1'h0;
+ assign _165_ = d_in[66] ? _160_ : 1'h0;
+ assign _166_ = ~ r[229];
+ assign _167_ = _180_ ? { _337_, _334_, _331_, _328_, _325_, _322_, _319_, _316_ } : r[195:132];
+ assign _168_ = ~ r[414];
+ assign _169_ = r[0] & _168_;
+ assign _170_ = r[412] ? 3'h7 : _161_;
+ assign _171_ = r[412] ? r[209] : 1'h0;
+ assign _172_ = r[412] ? r[411] : r[209];
+ assign _173_ = _166_ & r[0];
+ assign _174_ = _166_ ? _161_ : _170_;
+ assign _175_ = _166_ ? 2'h3 : r[229:228];
+ assign _176_ = _166_ ? _139_ : 1'h0;
+ assign _177_ = _166_ ? 1'h0 : _171_;
+ assign _178_ = _166_ ? 1'h0 : _169_;
+ assign _179_ = _166_ ? r[411] : _172_;
+ assign _180_ = d_in[0] & _173_;
+ assign _181_ = d_in[0] ? { _175_, _174_ } : { r[229:228], _161_ };
+ assign _182_ = d_in[0] ? _176_ : _139_;
+ assign _183_ = d_in[0] ? _177_ : 1'h0;
+ assign _184_ = d_in[0] ? _178_ : 1'h0;
+ assign _185_ = d_in[0] ? _179_ : r[411];
+ assign _186_ = ~ r[412];
+ assign _187_ = r[229] & _186_;
+ assign _188_ = r[227:225] == 3'h3;
+ assign _189_ = ~ r[342];
+ assign _190_ = ~ r[229];
+ assign _191_ = _190_ ? 3'h2 : 3'h3;
+ assign _192_ = _194_ ? _191_ : r[227:225];
+ assign _193_ = _189_ ? 1'h1 : 1'h0;
+ assign _194_ = m_in[0] & _189_;
+ assign _195_ = m_in[0] ? _193_ : 1'h0;
+ assign _196_ = ~ r[0];
+ assign _197_ = m_in[1] ? 1'h1 : 1'h0;
+ assign _198_ = m_in[1] ? { m_in[3], m_in[6] } : 2'h0;
+ assign _199_ = m_in[1] ? _196_ : 1'h0;
+ assign _200_ = m_in[1] ? m_in[5] : 1'h0;
+ assign _201_ = m_in[1] ? m_in[2] : 1'h0;
+ assign _202_ = r[227:225] == 3'h4;
+ assign _203_ = r[227:225] == 3'h5;
+ assign _204_ = r[227:225] == 3'h6;
+ assign _205_ = r[227:225] == 3'h7;
+ function [63:0] \15511 ;
+ input [63:0] a;
+ input [511:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15511 = b[63:0];
+ 8'b??????1?:
+ \15511 = b[127:64];
+ 8'b?????1??:
+ \15511 = b[191:128];
+ 8'b????1???:
+ \15511 = b[255:192];
+ 8'b???1????:
+ \15511 = b[319:256];
+ 8'b??1?????:
+ \15511 = b[383:320];
+ 8'b?1??????:
+ \15511 = b[447:384];
+ 8'b1???????:
+ \15511 = b[511:448];
+ default:
+ \15511 = a;
+ endcase
+ endfunction
+ assign _206_ = \15511 (64'hxxxxxxxxxxxxxxxx, { r[195:132], r[195:132], r[195:132], r[195:132], _167_, r[195:132], r[195:132], r[195:132] }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [2:0] \15515 ;
+ input [2:0] a;
+ input [23:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15515 = b[2:0];
+ 8'b??????1?:
+ \15515 = b[5:3];
+ 8'b?????1??:
+ \15515 = b[8:6];
+ 8'b????1???:
+ \15515 = b[11:9];
+ 8'b???1????:
+ \15515 = b[14:12];
+ 8'b??1?????:
+ \15515 = b[17:15];
+ 8'b?1??????:
+ \15515 = b[20:18];
+ 8'b1???????:
+ \15515 = b[23:21];
+ default:
+ \15515 = a;
+ endcase
+ endfunction
+ assign _207_ = \15515 (3'hx, { r[227:225], r[227:225], r[227:225], _192_, _181_[2:0], 3'h3, _152_, r[227:225] }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15519 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15519 = b[0:0];
+ 8'b??????1?:
+ \15519 = b[1:1];
+ 8'b?????1??:
+ \15519 = b[2:2];
+ 8'b????1???:
+ \15519 = b[3:3];
+ 8'b???1????:
+ \15519 = b[4:4];
+ 8'b??1?????:
+ \15519 = b[5:5];
+ 8'b?1??????:
+ \15519 = b[6:6];
+ 8'b1???????:
+ \15519 = b[7:7];
+ default:
+ \15519 = a;
+ endcase
+ endfunction
+ assign _208_ = \15519 (1'hx, { r[228], r[228], r[228], r[228], _181_[3], r[228], r[228], r[228] }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15523 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15523 = b[0:0];
+ 8'b??????1?:
+ \15523 = b[1:1];
+ 8'b?????1??:
+ \15523 = b[2:2];
+ 8'b????1???:
+ \15523 = b[3:3];
+ 8'b???1????:
+ \15523 = b[4:4];
+ 8'b??1?????:
+ \15523 = b[5:5];
+ 8'b?1??????:
+ \15523 = b[6:6];
+ 8'b1???????:
+ \15523 = b[7:7];
+ default:
+ \15523 = a;
+ endcase
+ endfunction
+ assign _209_ = \15523 (1'hx, { r[229], r[229], r[229], r[229], _181_[4], 1'h0, r[229], r[229] }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15525 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15525 = b[0:0];
+ 8'b??????1?:
+ \15525 = b[1:1];
+ 8'b?????1??:
+ \15525 = b[2:2];
+ 8'b????1???:
+ \15525 = b[3:3];
+ 8'b???1????:
+ \15525 = b[4:4];
+ 8'b??1?????:
+ \15525 = b[5:5];
+ 8'b?1??????:
+ \15525 = b[6:6];
+ 8'b1???????:
+ \15525 = b[7:7];
+ default:
+ \15525 = a;
+ endcase
+ endfunction
+ assign _210_ = \15525 (1'hx, { _139_, _139_, _139_, _139_, _182_, _139_, _139_, _139_ }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15528 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15528 = b[0:0];
+ 8'b??????1?:
+ \15528 = b[1:1];
+ 8'b?????1??:
+ \15528 = b[2:2];
+ 8'b????1???:
+ \15528 = b[3:3];
+ 8'b???1????:
+ \15528 = b[4:4];
+ 8'b??1?????:
+ \15528 = b[5:5];
+ 8'b?1??????:
+ \15528 = b[6:6];
+ 8'b1???????:
+ \15528 = b[7:7];
+ default:
+ \15528 = a;
+ endcase
+ endfunction
+ assign _211_ = \15528 (1'hx, { r[409], r[409], r[409], r[409], _187_, r[409], r[409], r[409] }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15530 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15530 = b[0:0];
+ 8'b??????1?:
+ \15530 = b[1:1];
+ 8'b?????1??:
+ \15530 = b[2:2];
+ 8'b????1???:
+ \15530 = b[3:3];
+ 8'b???1????:
+ \15530 = b[4:4];
+ 8'b??1?????:
+ \15530 = b[5:5];
+ 8'b?1??????:
+ \15530 = b[6:6];
+ 8'b1???????:
+ \15530 = b[7:7];
+ default:
+ \15530 = a;
+ endcase
+ endfunction
+ assign _212_ = \15530 (1'hx, { 4'h0, _183_, 3'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15541 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15541 = b[0:0];
+ 8'b??????1?:
+ \15541 = b[1:1];
+ 8'b?????1??:
+ \15541 = b[2:2];
+ 8'b????1???:
+ \15541 = b[3:3];
+ 8'b???1????:
+ \15541 = b[4:4];
+ 8'b??1?????:
+ \15541 = b[5:5];
+ 8'b?1??????:
+ \15541 = b[6:6];
+ 8'b1???????:
+ \15541 = b[7:7];
+ default:
+ \15541 = a;
+ endcase
+ endfunction
+ assign _213_ = \15541 (1'hx, { 3'h0, _195_, 4'h6 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15545 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15545 = b[0:0];
+ 8'b??????1?:
+ \15545 = b[1:1];
+ 8'b?????1??:
+ \15545 = b[2:2];
+ 8'b????1???:
+ \15545 = b[3:3];
+ 8'b???1????:
+ \15545 = b[4:4];
+ 8'b??1?????:
+ \15545 = b[5:5];
+ 8'b?1??????:
+ \15545 = b[6:6];
+ 8'b1???????:
+ \15545 = b[7:7];
+ default:
+ \15545 = a;
+ endcase
+ endfunction
+ assign _214_ = \15545 (1'hx, { 4'h0, _184_, 3'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15548 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15548 = b[0:0];
+ 8'b??????1?:
+ \15548 = b[1:1];
+ 8'b?????1??:
+ \15548 = b[2:2];
+ 8'b????1???:
+ \15548 = b[3:3];
+ 8'b???1????:
+ \15548 = b[4:4];
+ 8'b??1?????:
+ \15548 = b[5:5];
+ 8'b?1??????:
+ \15548 = b[6:6];
+ 8'b1???????:
+ \15548 = b[7:7];
+ default:
+ \15548 = a;
+ endcase
+ endfunction
+ assign _215_ = \15548 (1'hx, { r[411], r[411], r[411], r[411], _185_, r[411], r[411], r[411] }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15551 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15551 = b[0:0];
+ 8'b??????1?:
+ \15551 = b[1:1];
+ 8'b?????1??:
+ \15551 = b[2:2];
+ 8'b????1???:
+ \15551 = b[3:3];
+ 8'b???1????:
+ \15551 = b[4:4];
+ 8'b??1?????:
+ \15551 = b[5:5];
+ 8'b?1??????:
+ \15551 = b[6:6];
+ 8'b1???????:
+ \15551 = b[7:7];
+ default:
+ \15551 = a;
+ endcase
+ endfunction
+ assign _216_ = \15551 (1'hx, { r[343], 2'h0, _197_, _162_, 3'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15555 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15555 = b[0:0];
+ 8'b??????1?:
+ \15555 = b[1:1];
+ 8'b?????1??:
+ \15555 = b[2:2];
+ 8'b????1???:
+ \15555 = b[3:3];
+ 8'b???1????:
+ \15555 = b[4:4];
+ 8'b??1?????:
+ \15555 = b[5:5];
+ 8'b?1??????:
+ \15555 = b[6:6];
+ 8'b1???????:
+ \15555 = b[7:7];
+ default:
+ \15555 = a;
+ endcase
+ endfunction
+ assign _217_ = \15555 (1'hx, { 4'h0, _163_, 3'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [1:0] \15559 ;
+ input [1:0] a;
+ input [15:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15559 = b[1:0];
+ 8'b??????1?:
+ \15559 = b[3:2];
+ 8'b?????1??:
+ \15559 = b[5:4];
+ 8'b????1???:
+ \15559 = b[7:6];
+ 8'b???1????:
+ \15559 = b[9:8];
+ 8'b??1?????:
+ \15559 = b[11:10];
+ 8'b?1??????:
+ \15559 = b[13:12];
+ 8'b1???????:
+ \15559 = b[15:14];
+ default:
+ \15559 = a;
+ endcase
+ endfunction
+ assign _218_ = \15559 (2'hx, { 6'h00, _198_, 8'h00 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15562 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15562 = b[0:0];
+ 8'b??????1?:
+ \15562 = b[1:1];
+ 8'b?????1??:
+ \15562 = b[2:2];
+ 8'b????1???:
+ \15562 = b[3:3];
+ 8'b???1????:
+ \15562 = b[4:4];
+ 8'b??1?????:
+ \15562 = b[5:5];
+ 8'b?1??????:
+ \15562 = b[6:6];
+ 8'b1???????:
+ \15562 = b[7:7];
+ default:
+ \15562 = a;
+ endcase
+ endfunction
+ assign _219_ = \15562 (1'hx, { 3'h0, _199_, _164_, 3'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15565 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15565 = b[0:0];
+ 8'b??????1?:
+ \15565 = b[1:1];
+ 8'b?????1??:
+ \15565 = b[2:2];
+ 8'b????1???:
+ \15565 = b[3:3];
+ 8'b???1????:
+ \15565 = b[4:4];
+ 8'b??1?????:
+ \15565 = b[5:5];
+ 8'b?1??????:
+ \15565 = b[6:6];
+ 8'b1???????:
+ \15565 = b[7:7];
+ default:
+ \15565 = a;
+ endcase
+ endfunction
+ assign _220_ = \15565 (1'hx, { 3'h0, _200_, 4'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15568 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15568 = b[0:0];
+ 8'b??????1?:
+ \15568 = b[1:1];
+ 8'b?????1??:
+ \15568 = b[2:2];
+ 8'b????1???:
+ \15568 = b[3:3];
+ 8'b???1????:
+ \15568 = b[4:4];
+ 8'b??1?????:
+ \15568 = b[5:5];
+ 8'b?1??????:
+ \15568 = b[6:6];
+ 8'b1???????:
+ \15568 = b[7:7];
+ default:
+ \15568 = a;
+ endcase
+ endfunction
+ assign _221_ = \15568 (1'hx, { 4'h0, _165_, 3'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15571 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15571 = b[0:0];
+ 8'b??????1?:
+ \15571 = b[1:1];
+ 8'b?????1??:
+ \15571 = b[2:2];
+ 8'b????1???:
+ \15571 = b[3:3];
+ 8'b???1????:
+ \15571 = b[4:4];
+ 8'b??1?????:
+ \15571 = b[5:5];
+ 8'b?1??????:
+ \15571 = b[6:6];
+ 8'b1???????:
+ \15571 = b[7:7];
+ default:
+ \15571 = a;
+ endcase
+ endfunction
+ assign _222_ = \15571 (1'hx, { 3'h0, _201_, 4'h0 }, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ function [0:0] \15585 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \15585 = b[0:0];
+ 8'b??????1?:
+ \15585 = b[1:1];
+ 8'b?????1??:
+ \15585 = b[2:2];
+ 8'b????1???:
+ \15585 = b[3:3];
+ 8'b???1????:
+ \15585 = b[4:4];
+ 8'b??1?????:
+ \15585 = b[5:5];
+ 8'b?1??????:
+ \15585 = b[6:6];
+ 8'b1???????:
+ \15585 = b[7:7];
+ default:
+ \15585 = a;
+ endcase
+ endfunction
+ assign _223_ = \15585 (1'hx, 8'h40, { _205_, _204_, _203_, _202_, _188_, _154_, _153_, _150_ });
+ assign _224_ = _143_ | _216_;
+ assign _225_ = _224_ ? 3'h0 : _207_;
+ assign _226_ = _224_ ? 1'h0 : _210_;
+ assign _227_ = l_in[324] ? 32'd0 : lsu_sum[63:32];
+ assign _228_ = lsu_sum[31:28] == 4'hc;
+ assign _229_ = ~ l_in[322];
+ assign _230_ = _228_ & _229_;
+ assign _231_ = _230_ ? 1'h1 : l_in[306];
+ assign _232_ = l_in[305:302] == 4'h1;
+ assign _233_ = l_in[305:302] == 4'h2;
+ assign _234_ = l_in[305:302] == 4'h4;
+ assign _235_ = l_in[305:302] == 4'h8;
+ function [7:0] \15663 ;
+ input [7:0] a;
+ input [31:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \15663 = b[7:0];
+ 4'b??1?:
+ \15663 = b[15:8];
+ 4'b?1??:
+ \15663 = b[23:16];
+ 4'b1???:
+ \15663 = b[31:24];
+ default:
+ \15663 = a;
+ endcase
+ endfunction
+ assign _236_ = \15663 (8'h00, 32'd4279173889, { _235_, _234_, _233_, _232_ });
+ assign _237_ = { 8'h00, _236_ } << { 28'h0000000, lsu_sum[2:0] };
+ assign _238_ = l_in[304:302] - 3'h1;
+ assign _239_ = _238_ & lsu_sum[2:0];
+ assign _240_ = | _239_;
+ assign _241_ = l_in[320] & _240_;
+ assign _242_ = l_in[6:1] == 6'h20;
+ assign _243_ = l_in[6:1] == 6'h1f;
+ assign _244_ = l_in[6:1] == 6'h14;
+ assign _245_ = l_in[6:1] == 6'h22;
+ assign _246_ = l_in[6:1] == 6'h21;
+ assign _247_ = l_in[6:1] == 6'h3a;
+ assign _248_ = ~ l_in[86];
+ assign _249_ = ~ l_in[82];
+ assign _250_ = _248_ & _249_;
+ assign _251_ = ~ l_in[87];
+ assign _252_ = _251_ ? { 32'h00000000, r[341:310] } : r[309:246];
+ assign _253_ = _250_ ? _252_ : m_in[70:7];
+ assign _254_ = l_in[6:1] == 6'h26;
+ assign _255_ = ~ l_in[86];
+ assign _256_ = ~ l_in[82];
+ assign _257_ = _255_ & _256_;
+ assign _258_ = ~ l_in[87];
+ assign _259_ = _258_ ? r[309:246] : l_in[294:231];
+ assign _260_ = _258_ ? l_in[262:231] : r[341:310];
+ assign _261_ = _257_ ? 3'h7 : 3'h5;
+ assign _262_ = _257_ ? { _260_, _259_ } : r[341:246];
+ assign _263_ = _257_ ? 1'h0 : 1'h1;
+ assign _264_ = _257_ ? 1'h0 : 1'h1;
+ assign _265_ = l_in[6:1] == 6'h2a;
+ assign _266_ = l_in[6:1] == 6'h3f;
+ function [0:0] \15755 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15755 = b[0:0];
+ 9'b???????1?:
+ \15755 = b[1:1];
+ 9'b??????1??:
+ \15755 = b[2:2];
+ 9'b?????1???:
+ \15755 = b[3:3];
+ 9'b????1????:
+ \15755 = b[4:4];
+ 9'b???1?????:
+ \15755 = b[5:5];
+ 9'b??1??????:
+ \15755 = b[6:6];
+ 9'b?1???????:
+ \15755 = b[7:7];
+ 9'b1????????:
+ \15755 = b[8:8];
+ default:
+ \15755 = a;
+ endcase
+ endfunction
+ assign _267_ = \15755 (1'h0, 9'h002, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15756 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15756 = b[0:0];
+ 9'b???????1?:
+ \15756 = b[1:1];
+ 9'b??????1??:
+ \15756 = b[2:2];
+ 9'b?????1???:
+ \15756 = b[3:3];
+ 9'b????1????:
+ \15756 = b[4:4];
+ 9'b???1?????:
+ \15756 = b[5:5];
+ 9'b??1??????:
+ \15756 = b[6:6];
+ 9'b?1???????:
+ \15756 = b[7:7];
+ 9'b1????????:
+ \15756 = b[8:8];
+ default:
+ \15756 = a;
+ endcase
+ endfunction
+ assign _268_ = \15756 (1'h0, 9'h020, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15757 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15757 = b[0:0];
+ 9'b???????1?:
+ \15757 = b[1:1];
+ 9'b??????1??:
+ \15757 = b[2:2];
+ 9'b?????1???:
+ \15757 = b[3:3];
+ 9'b????1????:
+ \15757 = b[4:4];
+ 9'b???1?????:
+ \15757 = b[5:5];
+ 9'b??1??????:
+ \15757 = b[6:6];
+ 9'b?1???????:
+ \15757 = b[7:7];
+ 9'b1????????:
+ \15757 = b[8:8];
+ default:
+ \15757 = a;
+ endcase
+ endfunction
+ assign _269_ = \15757 (1'h0, 9'h004, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15758 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15758 = b[0:0];
+ 9'b???????1?:
+ \15758 = b[1:1];
+ 9'b??????1??:
+ \15758 = b[2:2];
+ 9'b?????1???:
+ \15758 = b[3:3];
+ 9'b????1????:
+ \15758 = b[4:4];
+ 9'b???1?????:
+ \15758 = b[5:5];
+ 9'b??1??????:
+ \15758 = b[6:6];
+ 9'b?1???????:
+ \15758 = b[7:7];
+ 9'b1????????:
+ \15758 = b[8:8];
+ default:
+ \15758 = a;
+ endcase
+ endfunction
+ assign _270_ = \15758 (1'h0, 9'h040, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [2:0] \15759 ;
+ input [2:0] a;
+ input [26:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15759 = b[2:0];
+ 9'b???????1?:
+ \15759 = b[5:3];
+ 9'b??????1??:
+ \15759 = b[8:6];
+ 9'b?????1???:
+ \15759 = b[11:9];
+ 9'b????1????:
+ \15759 = b[14:12];
+ 9'b???1?????:
+ \15759 = b[17:15];
+ 9'b??1??????:
+ \15759 = b[20:18];
+ 9'b?1???????:
+ \15759 = b[23:21];
+ 9'b1????????:
+ \15759 = b[26:24];
+ default:
+ \15759 = a;
+ endcase
+ endfunction
+ assign _271_ = \15759 (_225_, { 3'h4, _261_, 6'h3d, _225_, _225_, _225_, _225_, _225_ }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [95:0] \15761 ;
+ input [95:0] a;
+ input [863:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15761 = b[95:0];
+ 9'b???????1?:
+ \15761 = b[191:96];
+ 9'b??????1??:
+ \15761 = b[287:192];
+ 9'b?????1???:
+ \15761 = b[383:288];
+ 9'b????1????:
+ \15761 = b[479:384];
+ 9'b???1?????:
+ \15761 = b[575:480];
+ 9'b??1??????:
+ \15761 = b[671:576];
+ 9'b?1???????:
+ \15761 = b[767:672];
+ 9'b1????????:
+ \15761 = b[863:768];
+ default:
+ \15761 = a;
+ endcase
+ endfunction
+ assign _272_ = \15761 (r[341:246], { r[341:246], _262_, r[341:246], r[341:246], r[341:246], r[341:246], r[341:246], r[341:246], r[341:246] }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15762 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15762 = b[0:0];
+ 9'b???????1?:
+ \15762 = b[1:1];
+ 9'b??????1??:
+ \15762 = b[2:2];
+ 9'b?????1???:
+ \15762 = b[3:3];
+ 9'b????1????:
+ \15762 = b[4:4];
+ 9'b???1?????:
+ \15762 = b[5:5];
+ 9'b??1??????:
+ \15762 = b[6:6];
+ 9'b?1???????:
+ \15762 = b[7:7];
+ 9'b1????????:
+ \15762 = b[8:8];
+ default:
+ \15762 = a;
+ endcase
+ endfunction
+ assign _273_ = \15762 (1'h0, 9'h100, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15763 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15763 = b[0:0];
+ 9'b???????1?:
+ \15763 = b[1:1];
+ 9'b??????1??:
+ \15763 = b[2:2];
+ 9'b?????1???:
+ \15763 = b[3:3];
+ 9'b????1????:
+ \15763 = b[4:4];
+ 9'b???1?????:
+ \15763 = b[5:5];
+ 9'b??1??????:
+ \15763 = b[6:6];
+ 9'b?1???????:
+ \15763 = b[7:7];
+ 9'b1????????:
+ \15763 = b[8:8];
+ default:
+ \15763 = a;
+ endcase
+ endfunction
+ assign _274_ = \15763 (_241_, { _241_, _241_, _241_, _241_, _241_, _241_, _231_, _241_, _241_ }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [63:0] \15765 ;
+ input [63:0] a;
+ input [575:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15765 = b[63:0];
+ 9'b???????1?:
+ \15765 = b[127:64];
+ 9'b??????1??:
+ \15765 = b[191:128];
+ 9'b?????1???:
+ \15765 = b[255:192];
+ 9'b????1????:
+ \15765 = b[319:256];
+ 9'b???1?????:
+ \15765 = b[383:320];
+ 9'b??1??????:
+ \15765 = b[447:384];
+ 9'b?1???????:
+ \15765 = b[511:448];
+ 9'b1????????:
+ \15765 = b[575:512];
+ default:
+ \15765 = a;
+ endcase
+ endfunction
+ assign _275_ = \15765 (r[407:344], { r[407:344], r[407:344], _253_, r[407:344], r[407:344], r[407:344], r[407:344], r[407:344], r[407:344] }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15766 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15766 = b[0:0];
+ 9'b???????1?:
+ \15766 = b[1:1];
+ 9'b??????1??:
+ \15766 = b[2:2];
+ 9'b?????1???:
+ \15766 = b[3:3];
+ 9'b????1????:
+ \15766 = b[4:4];
+ 9'b???1?????:
+ \15766 = b[5:5];
+ 9'b??1??????:
+ \15766 = b[6:6];
+ 9'b?1???????:
+ \15766 = b[7:7];
+ 9'b1????????:
+ \15766 = b[8:8];
+ default:
+ \15766 = a;
+ endcase
+ endfunction
+ assign _276_ = \15766 (1'h0, { 1'h1, _263_, 7'h20 }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15767 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15767 = b[0:0];
+ 9'b???????1?:
+ \15767 = b[1:1];
+ 9'b??????1??:
+ \15767 = b[2:2];
+ 9'b?????1???:
+ \15767 = b[3:3];
+ 9'b????1????:
+ \15767 = b[4:4];
+ 9'b???1?????:
+ \15767 = b[5:5];
+ 9'b??1??????:
+ \15767 = b[6:6];
+ 9'b?1???????:
+ \15767 = b[7:7];
+ 9'b1????????:
+ \15767 = b[8:8];
+ default:
+ \15767 = a;
+ endcase
+ endfunction
+ assign _277_ = \15767 (1'h0, { 7'h00, l_in[309], 1'h0 }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15771 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15771 = b[0:0];
+ 9'b???????1?:
+ \15771 = b[1:1];
+ 9'b??????1??:
+ \15771 = b[2:2];
+ 9'b?????1???:
+ \15771 = b[3:3];
+ 9'b????1????:
+ \15771 = b[4:4];
+ 9'b???1?????:
+ \15771 = b[5:5];
+ 9'b??1??????:
+ \15771 = b[6:6];
+ 9'b?1???????:
+ \15771 = b[7:7];
+ 9'b1????????:
+ \15771 = b[8:8];
+ default:
+ \15771 = a;
+ endcase
+ endfunction
+ assign _278_ = \15771 (_213_, { _213_, _213_, _213_, _213_, _213_, _213_, 3'h7 }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [63:0] \15772 ;
+ input [63:0] a;
+ input [575:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15772 = b[63:0];
+ 9'b???????1?:
+ \15772 = b[127:64];
+ 9'b??????1??:
+ \15772 = b[191:128];
+ 9'b?????1???:
+ \15772 = b[255:192];
+ 9'b????1????:
+ \15772 = b[319:256];
+ 9'b???1?????:
+ \15772 = b[383:320];
+ 9'b??1??????:
+ \15772 = b[447:384];
+ 9'b?1???????:
+ \15772 = b[511:448];
+ 9'b1????????:
+ \15772 = b[575:512];
+ default:
+ \15772 = a;
+ endcase
+ endfunction
+ assign _279_ = \15772 (l_in[230:167], { l_in[70:7], l_in[230:167], l_in[230:167], l_in[230:167], l_in[230:167], l_in[230:167], l_in[230:167], l_in[230:167], l_in[230:167] }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15775 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15775 = b[0:0];
+ 9'b???????1?:
+ \15775 = b[1:1];
+ 9'b??????1??:
+ \15775 = b[2:2];
+ 9'b?????1???:
+ \15775 = b[3:3];
+ 9'b????1????:
+ \15775 = b[4:4];
+ 9'b???1?????:
+ \15775 = b[5:5];
+ 9'b??1??????:
+ \15775 = b[6:6];
+ 9'b?1???????:
+ \15775 = b[7:7];
+ 9'b1????????:
+ \15775 = b[8:8];
+ default:
+ \15775 = a;
+ endcase
+ endfunction
+ assign _280_ = \15775 (_217_, { 1'h1, _217_, _217_, 1'h1, _217_, _217_, _217_, _217_, _217_ }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ function [0:0] \15777 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \15777 = b[0:0];
+ 9'b???????1?:
+ \15777 = b[1:1];
+ 9'b??????1??:
+ \15777 = b[2:2];
+ 9'b?????1???:
+ \15777 = b[3:3];
+ 9'b????1????:
+ \15777 = b[4:4];
+ 9'b???1?????:
+ \15777 = b[5:5];
+ 9'b??1??????:
+ \15777 = b[6:6];
+ 9'b?1???????:
+ \15777 = b[7:7];
+ 9'b1????????:
+ \15777 = b[8:8];
+ default:
+ \15777 = a;
+ endcase
+ endfunction
+ assign _281_ = \15777 (1'h0, { 1'h0, _264_, 7'h00 }, { _266_, _265_, _254_, _247_, _246_, _245_, _244_, _243_, _242_ });
+ assign _282_ = _237_[15:8] == 8'h00;
+ assign _283_ = _282_ ? 3'h3 : 3'h2;
+ assign _284_ = _274_ ? 3'h7 : _283_;
+ assign _285_ = _278_ ? _284_ : _271_;
+ assign _286_ = _278_ | _280_;
+ assign _287_ = _286_ | _281_;
+ assign _288_ = _287_ | 1'h0;
+ assign _289_ = l_in[0] ? { lsu_sum, _270_, _269_, _268_, _267_ } : { r[67:4], 1'h0, r[2:0] };
+ assign _290_ = l_in[0] ? { 1'h0, l_in[324], _277_, 1'h0, _276_, 1'h0, _288_, _275_, _274_, _273_, _272_, _237_, 2'h2, _285_, l_in[323:322], _231_, l_in[321:307], l_in[305:295] } : { r[414:412], _212_, r[410], _211_, _226_, r[407:230], _209_, _208_, _225_, r[224:196] };
+ assign _291_ = l_in[0] ? _237_[7:0] : _146_;
+ assign _292_ = l_in[0] ? _278_ : _213_;
+ assign _293_ = l_in[0] ? { _227_, lsu_sum[31:0] } : { _148_, _149_ };
+ assign _294_ = l_in[0] ? _279_ : { _148_, _149_ };
+ assign _295_ = l_in[0] ? _280_ : _217_;
+ assign _296_ = l_in[0] ? _281_ : 1'h0;
+ assign _297_ = ~ _290_[147];
+ assign _298_ = _292_ & _297_;
+ assign _299_ = _223_ ? { 64'hxxxxxxxxxxxxxxxx, r[202:196], 1'h1 } : { _113_, _104_, _095_, _086_, _077_, _068_, _059_, _050_, r[202:196], _214_ };
+ assign _300_ = _215_ ? { r[67:4], 2'h0, r[214:210], 1'h1 } : _299_;
+ assign _301_ = r[3] ? { r[407:344], r[202:196], 1'h1 } : _300_;
+ assign _302_ = r[221] & _143_;
+ assign _303_ = ~ r[342];
+ assign _304_ = _216_ & _303_;
+ assign _305_ = ~ m_in[4];
+ assign _306_ = ~ r[343];
+ assign _307_ = _305_ & _306_;
+ assign _308_ = l_in[0] ? _272_[95:64] : r[341:310];
+ assign _309_ = _307_ ? { 1'h0, _222_, 1'h0, _221_, _220_, 1'h0, _219_, 5'h00, _218_, 18'h00000 } : _308_;
+ assign _310_ = l_in[0] ? _272_ : r[341:246];
+ assign _311_ = _304_ ? { _309_, _293_ } : _310_;
+ assign _312_ = l_in[0] ? { 1'h0, l_in[324], _277_, 1'h0, _276_, 1'h0, _288_, _275_, _274_, _273_ } : { r[414:412], _212_, r[410], _211_, _226_, r[407:342] };
+ assign _313_ = l_in[0] ? { _237_, 2'h2, _285_, l_in[323:322], _231_, l_in[321:307], l_in[305:295] } : { r[245:230], _209_, _208_, _225_, r[224:196] };
+ assign _316_ = _011_[2] ? _315_ : _314_;
+ assign _319_ = _013_[2] ? _318_ : _317_;
+ assign _322_ = _015_[2] ? _321_ : _320_;
+ assign _325_ = _017_[2] ? _324_ : _323_;
+ assign _328_ = _019_[2] ? _327_ : _326_;
+ assign _331_ = _021_[2] ? _330_ : _329_;
+ assign _334_ = _023_[2] ? _333_ : _332_;
+ assign _337_ = _025_[2] ? _336_ : _335_;
+ assign _340_ = _118_[2] ? _339_ : _338_;
+ assign _343_ = _120_[2] ? _342_ : _341_;
+ assign _346_ = _122_[2] ? _345_ : _344_;
+ assign _349_ = _124_[2] ? _348_ : _347_;
+ assign _352_ = _126_[2] ? _351_ : _350_;
+ assign _355_ = _128_[2] ? _354_ : _353_;
+ assign _358_ = _130_[2] ? _357_ : _356_;
+ assign _361_ = _132_[2] ? _360_ : _359_;
+ assign e_out = { r[342], m_in[4:3], m_in[6:5], m_in[2], r[343], _216_, _139_ };
+ assign l_out = { d_in[65], _302_, r[219:215], _301_, _143_ };
+ assign d_out = { _291_, _133_, _293_, _290_[28:27], _290_[24], _290_[26], _289_[2], _289_[0], _298_ };
+ assign m_out = { l_in[294:231], _294_, l_in[86:82], l_in[91:87], r[224], r[0], _290_[146], _296_, l_in[78], _289_[1], _295_ };
+ assign log_out = 10'hzzz;
+endmodule
+
+module logic_analyzer_32_32(clk, rst, wb_in, io_in, wb_out, io_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [31:0] _03_;
+ wire _04_;
+ wire [31:0] _05_;
+ wire [31:0] _06_;
+ wire _07_;
+ wire [31:0] _08_;
+ wire [31:0] _09_;
+ wire _10_;
+ reg [31:0] _11_;
+ reg [31:0] _12_;
+ reg ack;
+ input clk;
+ input [31:0] io_in;
+ output [31:0] io_out;
+ wire re;
+ input rst;
+ input [68:0] wb_in;
+ output [33:0] wb_out;
+ wire we;
+ assign _00_ = wb_in[67] & wb_in[66];
+ assign we = _00_ & wb_in[68];
+ assign _01_ = wb_in[67] & wb_in[66];
+ assign _02_ = ~ wb_in[68];
+ assign re = _01_ & _02_;
+ assign _03_ = we ? wb_in[61:30] : _12_;
+ assign _04_ = we ? 1'h1 : 1'h0;
+ assign _05_ = re ? io_in : _11_;
+ assign _06_ = re ? _12_ : _03_;
+ assign _07_ = re ? 1'h1 : _04_;
+ assign _08_ = rst ? _11_ : _05_;
+ assign _09_ = rst ? 32'd0 : _06_;
+ assign _10_ = rst ? 1'h0 : _07_;
+ always @(posedge clk)
+ _11_ <= _08_;
+ always @(posedge clk)
+ _12_ <= _09_;
+ always @(posedge clk)
+ ack <= _10_;
+ assign wb_out = { 1'h0, ack, _11_ };
+ assign io_out = _12_;
+endmodule
+
+module logical(rs, rb, op, invert_in, invert_out, datalen, result);
+ wire [1:0] _0000_;
+ wire [1:0] _0001_;
+ wire [1:0] _0002_;
+ wire [1:0] _0003_;
+ wire [1:0] _0004_;
+ wire [1:0] _0005_;
+ wire [1:0] _0006_;
+ wire [1:0] _0007_;
+ wire [1:0] _0008_;
+ wire [1:0] _0009_;
+ wire [1:0] _0010_;
+ wire [1:0] _0011_;
+ wire [1:0] _0012_;
+ wire [1:0] _0013_;
+ wire [1:0] _0014_;
+ wire [1:0] _0015_;
+ wire [1:0] _0016_;
+ wire [1:0] _0017_;
+ wire [1:0] _0018_;
+ wire [1:0] _0019_;
+ wire [1:0] _0020_;
+ wire [1:0] _0021_;
+ wire [1:0] _0022_;
+ wire [1:0] _0023_;
+ wire [1:0] _0024_;
+ wire [1:0] _0025_;
+ wire [1:0] _0026_;
+ wire [1:0] _0027_;
+ wire [1:0] _0028_;
+ wire [1:0] _0029_;
+ wire [1:0] _0030_;
+ wire [1:0] _0031_;
+ wire [2:0] _0032_;
+ wire [2:0] _0033_;
+ wire [2:0] _0034_;
+ wire [2:0] _0035_;
+ wire [2:0] _0036_;
+ wire [2:0] _0037_;
+ wire [2:0] _0038_;
+ wire [2:0] _0039_;
+ wire [2:0] _0040_;
+ wire [2:0] _0041_;
+ wire [2:0] _0042_;
+ wire [2:0] _0043_;
+ wire [2:0] _0044_;
+ wire [2:0] _0045_;
+ wire [2:0] _0046_;
+ wire [2:0] _0047_;
+ wire [3:0] _0048_;
+ wire [3:0] _0049_;
+ wire [3:0] _0050_;
+ wire [3:0] _0051_;
+ wire [3:0] _0052_;
+ wire [3:0] _0053_;
+ wire [3:0] _0054_;
+ wire [3:0] _0055_;
+ wire [5:0] _0056_;
+ wire [5:0] _0057_;
+ wire [5:0] _0058_;
+ wire [5:0] _0059_;
+ wire [5:0] _0060_;
+ wire [5:0] _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire [6:0] _0064_;
+ wire [5:0] _0065_;
+ wire _0066_;
+ wire [5:0] _0067_;
+ wire [3:0] _0068_;
+ wire [2:0] _0069_;
+ wire [3:0] _0070_;
+ wire [3:0] _0071_;
+ wire [3:0] _0072_;
+ wire [3:0] _0073_;
+ wire [1:0] _0074_;
+ wire [3:0] _0075_;
+ wire [3:0] _0076_;
+ wire [3:0] _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire [63:0] _0101_;
+ wire [63:0] _0102_;
+ wire [63:0] _0103_;
+ wire _0104_;
+ wire [63:0] _0105_;
+ wire _0106_;
+ wire [63:0] _0107_;
+ wire [63:0] _0108_;
+ wire [63:0] _0109_;
+ wire [63:0] _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire [7:0] _0119_;
+ wire _0120_;
+ wire [7:0] _0121_;
+ wire _0122_;
+ wire [7:0] _0123_;
+ wire _0124_;
+ wire [7:0] _0125_;
+ wire _0126_;
+ wire [7:0] _0127_;
+ wire _0128_;
+ wire [7:0] _0129_;
+ wire _0130_;
+ wire [7:0] _0131_;
+ wire _0132_;
+ wire [7:0] _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire [63:0] _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire [15:0] _0908_;
+ wire _0909_;
+ wire [7:0] _0910_;
+ wire [7:0] _0911_;
+ wire [7:0] _0912_;
+ wire [15:0] _0913_;
+ wire [31:0] _0914_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire _0938_;
+ wire _0939_;
+ wire _0940_;
+ wire _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire _0955_;
+ wire _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire _0960_;
+ wire _0961_;
+ wire _0962_;
+ wire _0963_;
+ wire _0964_;
+ wire _0965_;
+ wire _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire _0972_;
+ wire _0973_;
+ wire _0974_;
+ wire _0975_;
+ wire _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire _0997_;
+ wire _0998_;
+ wire _0999_;
+ wire _1000_;
+ wire _1001_;
+ wire _1002_;
+ wire _1003_;
+ wire _1004_;
+ wire _1005_;
+ wire _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1015_;
+ wire _1016_;
+ wire _1017_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire _1021_;
+ wire _1022_;
+ wire _1023_;
+ wire _1024_;
+ wire _1025_;
+ wire _1026_;
+ wire _1027_;
+ wire _1028_;
+ wire _1029_;
+ wire _1030_;
+ wire _1031_;
+ wire _1032_;
+ wire _1033_;
+ wire _1034_;
+ wire _1035_;
+ wire _1036_;
+ wire _1037_;
+ wire _1038_;
+ wire _1039_;
+ wire _1040_;
+ wire _1041_;
+ wire _1042_;
+ wire _1043_;
+ wire _1044_;
+ wire _1045_;
+ wire _1046_;
+ wire _1047_;
+ wire _1048_;
+ wire _1049_;
+ wire _1050_;
+ wire _1051_;
+ wire _1052_;
+ wire _1053_;
+ wire _1054_;
+ wire _1055_;
+ wire _1056_;
+ wire _1057_;
+ wire _1058_;
+ wire _1059_;
+ wire _1060_;
+ wire _1061_;
+ wire _1062_;
+ wire _1063_;
+ wire _1064_;
+ wire _1065_;
+ wire _1066_;
+ wire _1067_;
+ wire _1068_;
+ wire _1069_;
+ wire _1070_;
+ wire _1071_;
+ wire _1072_;
+ wire _1073_;
+ wire _1074_;
+ wire _1075_;
+ wire _1076_;
+ wire _1077_;
+ wire _1078_;
+ wire _1079_;
+ wire _1080_;
+ wire _1081_;
+ wire _1082_;
+ wire _1083_;
+ wire _1084_;
+ wire _1085_;
+ wire _1086_;
+ wire _1087_;
+ wire _1088_;
+ wire _1089_;
+ wire _1090_;
+ wire _1091_;
+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire _1095_;
+ wire _1096_;
+ wire _1097_;
+ wire _1098_;
+ wire _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire _1109_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire _1114_;
+ wire _1115_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1126_;
+ wire _1127_;
+ wire _1128_;
+ wire _1129_;
+ wire _1130_;
+ wire _1131_;
+ wire _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1140_;
+ wire _1141_;
+ wire _1142_;
+ wire _1143_;
+ wire _1144_;
+ wire _1145_;
+ wire _1146_;
+ wire _1147_;
+ wire _1148_;
+ wire _1149_;
+ wire _1150_;
+ wire _1151_;
+ wire _1152_;
+ wire _1153_;
+ wire _1154_;
+ wire _1155_;
+ wire _1156_;
+ wire _1157_;
+ wire _1158_;
+ wire _1159_;
+ wire _1160_;
+ wire _1161_;
+ wire _1162_;
+ wire _1163_;
+ wire _1164_;
+ wire _1165_;
+ wire _1166_;
+ wire _1167_;
+ wire _1168_;
+ wire _1169_;
+ wire _1170_;
+ wire _1171_;
+ wire _1172_;
+ wire _1173_;
+ wire _1174_;
+ wire _1175_;
+ wire _1176_;
+ wire _1177_;
+ wire _1178_;
+ wire _1179_;
+ wire _1180_;
+ wire _1181_;
+ wire _1182_;
+ wire _1183_;
+ wire _1184_;
+ wire _1185_;
+ wire _1186_;
+ wire _1187_;
+ wire _1188_;
+ wire _1189_;
+ wire _1190_;
+ wire _1191_;
+ wire _1192_;
+ wire _1193_;
+ wire _1194_;
+ wire _1195_;
+ wire _1196_;
+ wire _1197_;
+ wire _1198_;
+ wire _1199_;
+ wire _1200_;
+ wire _1201_;
+ wire _1202_;
+ wire _1203_;
+ wire _1204_;
+ wire _1205_;
+ wire _1206_;
+ wire _1207_;
+ wire _1208_;
+ wire _1209_;
+ wire _1210_;
+ wire _1211_;
+ wire _1212_;
+ wire _1213_;
+ wire _1214_;
+ wire _1215_;
+ wire _1216_;
+ wire _1217_;
+ wire _1218_;
+ wire _1219_;
+ wire _1220_;
+ wire _1221_;
+ wire _1222_;
+ wire _1223_;
+ wire _1224_;
+ wire _1225_;
+ wire _1226_;
+ wire _1227_;
+ wire _1228_;
+ wire _1229_;
+ wire _1230_;
+ wire _1231_;
+ wire _1232_;
+ wire _1233_;
+ wire _1234_;
+ wire _1235_;
+ wire _1236_;
+ wire _1237_;
+ wire _1238_;
+ wire _1239_;
+ wire _1240_;
+ wire _1241_;
+ wire _1242_;
+ wire _1243_;
+ wire _1244_;
+ wire _1245_;
+ wire _1246_;
+ wire _1247_;
+ wire _1248_;
+ wire _1249_;
+ wire _1250_;
+ wire _1251_;
+ wire _1252_;
+ wire _1253_;
+ wire _1254_;
+ wire _1255_;
+ wire _1256_;
+ wire _1257_;
+ wire _1258_;
+ wire _1259_;
+ wire _1260_;
+ wire _1261_;
+ wire _1262_;
+ wire _1263_;
+ wire _1264_;
+ wire _1265_;
+ wire _1266_;
+ wire _1267_;
+ wire _1268_;
+ wire _1269_;
+ wire _1270_;
+ wire _1271_;
+ wire _1272_;
+ wire _1273_;
+ wire _1274_;
+ wire _1275_;
+ wire _1276_;
+ wire _1277_;
+ wire _1278_;
+ wire _1279_;
+ wire _1280_;
+ wire _1281_;
+ wire _1282_;
+ wire _1283_;
+ wire _1284_;
+ wire _1285_;
+ wire _1286_;
+ wire _1287_;
+ wire _1288_;
+ wire _1289_;
+ wire _1290_;
+ wire _1291_;
+ wire _1292_;
+ wire _1293_;
+ wire _1294_;
+ wire _1295_;
+ wire _1296_;
+ wire _1297_;
+ wire _1298_;
+ wire _1299_;
+ wire _1300_;
+ wire _1301_;
+ wire _1302_;
+ wire _1303_;
+ wire _1304_;
+ wire _1305_;
+ wire _1306_;
+ wire _1307_;
+ wire _1308_;
+ wire _1309_;
+ wire _1310_;
+ wire _1311_;
+ wire _1312_;
+ wire _1313_;
+ wire _1314_;
+ wire _1315_;
+ wire _1316_;
+ wire _1317_;
+ wire _1318_;
+ wire _1319_;
+ wire _1320_;
+ wire _1321_;
+ wire _1322_;
+ wire _1323_;
+ wire _1324_;
+ wire _1325_;
+ wire _1326_;
+ wire _1327_;
+ wire _1328_;
+ wire _1329_;
+ wire _1330_;
+ wire _1331_;
+ wire _1332_;
+ wire _1333_;
+ wire _1334_;
+ wire _1335_;
+ wire _1336_;
+ wire _1337_;
+ wire _1338_;
+ wire _1339_;
+ wire _1340_;
+ wire _1341_;
+ wire _1342_;
+ wire _1343_;
+ wire _1344_;
+ wire _1345_;
+ wire _1346_;
+ wire _1347_;
+ wire _1348_;
+ wire _1349_;
+ wire _1350_;
+ wire _1351_;
+ wire _1352_;
+ wire _1353_;
+ wire _1354_;
+ wire _1355_;
+ wire _1356_;
+ wire _1357_;
+ wire _1358_;
+ wire _1359_;
+ wire _1360_;
+ wire _1361_;
+ wire _1362_;
+ wire _1363_;
+ wire _1364_;
+ wire _1365_;
+ wire _1366_;
+ wire _1367_;
+ wire _1368_;
+ wire _1369_;
+ wire _1370_;
+ wire _1371_;
+ wire _1372_;
+ wire _1373_;
+ wire _1374_;
+ wire _1375_;
+ wire _1376_;
+ wire _1377_;
+ wire _1378_;
+ wire _1379_;
+ wire _1380_;
+ wire _1381_;
+ wire _1382_;
+ wire _1383_;
+ wire _1384_;
+ wire _1385_;
+ wire _1386_;
+ wire _1387_;
+ wire _1388_;
+ wire _1389_;
+ wire _1390_;
+ wire _1391_;
+ wire _1392_;
+ wire _1393_;
+ wire _1394_;
+ wire _1395_;
+ wire _1396_;
+ wire _1397_;
+ wire _1398_;
+ wire _1399_;
+ wire _1400_;
+ wire _1401_;
+ wire _1402_;
+ wire _1403_;
+ wire _1404_;
+ wire _1405_;
+ wire _1406_;
+ wire _1407_;
+ wire _1408_;
+ wire _1409_;
+ wire _1410_;
+ wire _1411_;
+ wire _1412_;
+ wire _1413_;
+ wire _1414_;
+ wire _1415_;
+ wire _1416_;
+ wire _1417_;
+ wire _1418_;
+ input [3:0] datalen;
+ input invert_in;
+ input invert_out;
+ input [5:0] op;
+ wire par0;
+ wire par1;
+ input [63:0] rb;
+ output [63:0] result;
+ input [63:0] rs;
+ assign _1083_ = rs[0] ? rb[1] : rb[0];
+ assign _1084_ = rs[0] ? rb[5] : rb[4];
+ assign _1085_ = rs[0] ? rb[9] : rb[8];
+ assign _1086_ = rs[0] ? rb[13] : rb[12];
+ assign _1087_ = rs[0] ? rb[17] : rb[16];
+ assign _1088_ = rs[0] ? rb[21] : rb[20];
+ assign _1089_ = rs[0] ? rb[25] : rb[24];
+ assign _1090_ = rs[0] ? rb[29] : rb[28];
+ assign _1091_ = rs[0] ? rb[33] : rb[32];
+ assign _1092_ = rs[0] ? rb[37] : rb[36];
+ assign _1093_ = rs[0] ? rb[41] : rb[40];
+ assign _1094_ = rs[0] ? rb[45] : rb[44];
+ assign _1095_ = rs[0] ? rb[49] : rb[48];
+ assign _1096_ = rs[0] ? rb[53] : rb[52];
+ assign _1097_ = rs[0] ? rb[57] : rb[56];
+ assign _1098_ = rs[0] ? rb[61] : rb[60];
+ assign _1099_ = rs[2] ? _0916_ : _0915_;
+ assign _1100_ = rs[2] ? _0920_ : _0919_;
+ assign _1101_ = rs[2] ? _0924_ : _0923_;
+ assign _1102_ = rs[2] ? _0928_ : _0927_;
+ assign _1103_ = rs[4] ? _0932_ : _0931_;
+ assign _1104_ = rs[8] ? rb[1] : rb[0];
+ assign _1105_ = rs[8] ? rb[5] : rb[4];
+ assign _1106_ = rs[8] ? rb[9] : rb[8];
+ assign _1107_ = rs[8] ? rb[13] : rb[12];
+ assign _1108_ = rs[8] ? rb[17] : rb[16];
+ assign _1109_ = rs[8] ? rb[21] : rb[20];
+ assign _1110_ = rs[8] ? rb[25] : rb[24];
+ assign _1111_ = rs[8] ? rb[29] : rb[28];
+ assign _1112_ = rs[8] ? rb[33] : rb[32];
+ assign _1113_ = rs[8] ? rb[37] : rb[36];
+ assign _1114_ = rs[8] ? rb[41] : rb[40];
+ assign _1115_ = rs[8] ? rb[45] : rb[44];
+ assign _1116_ = rs[8] ? rb[49] : rb[48];
+ assign _1117_ = rs[8] ? rb[53] : rb[52];
+ assign _1118_ = rs[8] ? rb[57] : rb[56];
+ assign _1119_ = rs[8] ? rb[61] : rb[60];
+ assign _1120_ = rs[10] ? _0937_ : _0936_;
+ assign _1121_ = rs[10] ? _0941_ : _0940_;
+ assign _1122_ = rs[10] ? _0945_ : _0944_;
+ assign _1123_ = rs[10] ? _0949_ : _0948_;
+ assign _1124_ = rs[12] ? _0953_ : _0952_;
+ assign _1125_ = rs[16] ? rb[1] : rb[0];
+ assign _1126_ = rs[16] ? rb[5] : rb[4];
+ assign _1127_ = rs[16] ? rb[9] : rb[8];
+ assign _1128_ = rs[16] ? rb[13] : rb[12];
+ assign _1129_ = rs[16] ? rb[17] : rb[16];
+ assign _1130_ = rs[16] ? rb[21] : rb[20];
+ assign _1131_ = rs[16] ? rb[25] : rb[24];
+ assign _1132_ = rs[16] ? rb[29] : rb[28];
+ assign _1133_ = rs[16] ? rb[33] : rb[32];
+ assign _1134_ = rs[16] ? rb[37] : rb[36];
+ assign _1135_ = rs[16] ? rb[41] : rb[40];
+ assign _1136_ = rs[16] ? rb[45] : rb[44];
+ assign _1137_ = rs[16] ? rb[49] : rb[48];
+ assign _1138_ = rs[16] ? rb[53] : rb[52];
+ assign _1139_ = rs[16] ? rb[57] : rb[56];
+ assign _1140_ = rs[16] ? rb[61] : rb[60];
+ assign _1141_ = rs[18] ? _0958_ : _0957_;
+ assign _1142_ = rs[18] ? _0962_ : _0961_;
+ assign _1143_ = rs[18] ? _0966_ : _0965_;
+ assign _1144_ = rs[18] ? _0970_ : _0969_;
+ assign _1145_ = rs[20] ? _0974_ : _0973_;
+ assign _1146_ = rs[24] ? rb[1] : rb[0];
+ assign _1147_ = rs[24] ? rb[5] : rb[4];
+ assign _1148_ = rs[24] ? rb[9] : rb[8];
+ assign _1149_ = rs[24] ? rb[13] : rb[12];
+ assign _1150_ = rs[24] ? rb[17] : rb[16];
+ assign _1151_ = rs[24] ? rb[21] : rb[20];
+ assign _1152_ = rs[24] ? rb[25] : rb[24];
+ assign _1153_ = rs[24] ? rb[29] : rb[28];
+ assign _1154_ = rs[24] ? rb[33] : rb[32];
+ assign _1155_ = rs[24] ? rb[37] : rb[36];
+ assign _1156_ = rs[24] ? rb[41] : rb[40];
+ assign _1157_ = rs[24] ? rb[45] : rb[44];
+ assign _1158_ = rs[24] ? rb[49] : rb[48];
+ assign _1159_ = rs[24] ? rb[53] : rb[52];
+ assign _1160_ = rs[24] ? rb[57] : rb[56];
+ assign _1161_ = rs[24] ? rb[61] : rb[60];
+ assign _1162_ = rs[26] ? _0979_ : _0978_;
+ assign _1163_ = rs[26] ? _0983_ : _0982_;
+ assign _1164_ = rs[26] ? _0987_ : _0986_;
+ assign _1165_ = rs[26] ? _0991_ : _0990_;
+ assign _1166_ = rs[28] ? _0995_ : _0994_;
+ assign _1167_ = rs[32] ? rb[1] : rb[0];
+ assign _1168_ = rs[32] ? rb[5] : rb[4];
+ assign _1169_ = rs[32] ? rb[9] : rb[8];
+ assign _1170_ = rs[32] ? rb[13] : rb[12];
+ assign _1171_ = rs[32] ? rb[17] : rb[16];
+ assign _1172_ = rs[32] ? rb[21] : rb[20];
+ assign _1173_ = rs[32] ? rb[25] : rb[24];
+ assign _1174_ = rs[32] ? rb[29] : rb[28];
+ assign _1175_ = rs[32] ? rb[33] : rb[32];
+ assign _1176_ = rs[32] ? rb[37] : rb[36];
+ assign _1177_ = rs[32] ? rb[41] : rb[40];
+ assign _1178_ = rs[32] ? rb[45] : rb[44];
+ assign _1179_ = rs[32] ? rb[49] : rb[48];
+ assign _1180_ = rs[32] ? rb[53] : rb[52];
+ assign _1181_ = rs[32] ? rb[57] : rb[56];
+ assign _1182_ = rs[32] ? rb[61] : rb[60];
+ assign _1183_ = rs[34] ? _1000_ : _0999_;
+ assign _1184_ = rs[34] ? _1004_ : _1003_;
+ assign _1185_ = rs[34] ? _1008_ : _1007_;
+ assign _1186_ = rs[34] ? _1012_ : _1011_;
+ assign _1187_ = rs[36] ? _1016_ : _1015_;
+ assign _1188_ = rs[40] ? rb[1] : rb[0];
+ assign _1189_ = rs[40] ? rb[5] : rb[4];
+ assign _1190_ = rs[40] ? rb[9] : rb[8];
+ assign _1191_ = rs[40] ? rb[13] : rb[12];
+ assign _1192_ = rs[40] ? rb[17] : rb[16];
+ assign _1193_ = rs[40] ? rb[21] : rb[20];
+ assign _1194_ = rs[40] ? rb[25] : rb[24];
+ assign _1195_ = rs[40] ? rb[29] : rb[28];
+ assign _1196_ = rs[40] ? rb[33] : rb[32];
+ assign _1197_ = rs[40] ? rb[37] : rb[36];
+ assign _1198_ = rs[40] ? rb[41] : rb[40];
+ assign _1199_ = rs[40] ? rb[45] : rb[44];
+ assign _1200_ = rs[40] ? rb[49] : rb[48];
+ assign _1201_ = rs[40] ? rb[53] : rb[52];
+ assign _1202_ = rs[40] ? rb[57] : rb[56];
+ assign _1203_ = rs[40] ? rb[61] : rb[60];
+ assign _1204_ = rs[42] ? _1021_ : _1020_;
+ assign _1205_ = rs[42] ? _1025_ : _1024_;
+ assign _1206_ = rs[42] ? _1029_ : _1028_;
+ assign _1207_ = rs[42] ? _1033_ : _1032_;
+ assign _1208_ = rs[44] ? _1037_ : _1036_;
+ assign _1209_ = rs[48] ? rb[1] : rb[0];
+ assign _1210_ = rs[48] ? rb[5] : rb[4];
+ assign _1211_ = rs[48] ? rb[9] : rb[8];
+ assign _1212_ = rs[48] ? rb[13] : rb[12];
+ assign _1213_ = rs[48] ? rb[17] : rb[16];
+ assign _1214_ = rs[48] ? rb[21] : rb[20];
+ assign _1215_ = rs[48] ? rb[25] : rb[24];
+ assign _1216_ = rs[48] ? rb[29] : rb[28];
+ assign _1217_ = rs[48] ? rb[33] : rb[32];
+ assign _1218_ = rs[48] ? rb[37] : rb[36];
+ assign _1219_ = rs[48] ? rb[41] : rb[40];
+ assign _1220_ = rs[48] ? rb[45] : rb[44];
+ assign _1221_ = rs[48] ? rb[49] : rb[48];
+ assign _1222_ = rs[48] ? rb[53] : rb[52];
+ assign _1223_ = rs[48] ? rb[57] : rb[56];
+ assign _1224_ = rs[48] ? rb[61] : rb[60];
+ assign _1225_ = rs[50] ? _1042_ : _1041_;
+ assign _1226_ = rs[50] ? _1046_ : _1045_;
+ assign _1227_ = rs[50] ? _1050_ : _1049_;
+ assign _1228_ = rs[50] ? _1054_ : _1053_;
+ assign _1229_ = rs[52] ? _1058_ : _1057_;
+ assign _1230_ = rs[56] ? rb[1] : rb[0];
+ assign _1231_ = rs[56] ? rb[5] : rb[4];
+ assign _1232_ = rs[56] ? rb[9] : rb[8];
+ assign _1233_ = rs[56] ? rb[13] : rb[12];
+ assign _1234_ = rs[56] ? rb[17] : rb[16];
+ assign _1235_ = rs[56] ? rb[21] : rb[20];
+ assign _1236_ = rs[56] ? rb[25] : rb[24];
+ assign _1237_ = rs[56] ? rb[29] : rb[28];
+ assign _1238_ = rs[56] ? rb[33] : rb[32];
+ assign _1239_ = rs[56] ? rb[37] : rb[36];
+ assign _1240_ = rs[56] ? rb[41] : rb[40];
+ assign _1241_ = rs[56] ? rb[45] : rb[44];
+ assign _1242_ = rs[56] ? rb[49] : rb[48];
+ assign _1243_ = rs[56] ? rb[53] : rb[52];
+ assign _1244_ = rs[56] ? rb[57] : rb[56];
+ assign _1245_ = rs[56] ? rb[61] : rb[60];
+ assign _1246_ = rs[58] ? _1063_ : _1062_;
+ assign _1247_ = rs[58] ? _1067_ : _1066_;
+ assign _1248_ = rs[58] ? _1071_ : _1070_;
+ assign _1249_ = rs[58] ? _1075_ : _1074_;
+ assign _1250_ = rs[60] ? _1079_ : _1078_;
+ assign _1251_ = rs[0] ? rb[3] : rb[2];
+ assign _1252_ = rs[0] ? rb[7] : rb[6];
+ assign _1253_ = rs[0] ? rb[11] : rb[10];
+ assign _1254_ = rs[0] ? rb[15] : rb[14];
+ assign _1255_ = rs[0] ? rb[19] : rb[18];
+ assign _1256_ = rs[0] ? rb[23] : rb[22];
+ assign _1257_ = rs[0] ? rb[27] : rb[26];
+ assign _1258_ = rs[0] ? rb[31] : rb[30];
+ assign _1259_ = rs[0] ? rb[35] : rb[34];
+ assign _1260_ = rs[0] ? rb[39] : rb[38];
+ assign _1261_ = rs[0] ? rb[43] : rb[42];
+ assign _1262_ = rs[0] ? rb[47] : rb[46];
+ assign _1263_ = rs[0] ? rb[51] : rb[50];
+ assign _1264_ = rs[0] ? rb[55] : rb[54];
+ assign _1265_ = rs[0] ? rb[59] : rb[58];
+ assign _1266_ = rs[0] ? rb[63] : rb[62];
+ assign _1267_ = rs[2] ? _0918_ : _0917_;
+ assign _1268_ = rs[2] ? _0922_ : _0921_;
+ assign _1269_ = rs[2] ? _0926_ : _0925_;
+ assign _1270_ = rs[2] ? _0930_ : _0929_;
+ assign _1271_ = rs[4] ? _0934_ : _0933_;
+ assign _1272_ = rs[8] ? rb[3] : rb[2];
+ assign _1273_ = rs[8] ? rb[7] : rb[6];
+ assign _1274_ = rs[8] ? rb[11] : rb[10];
+ assign _1275_ = rs[8] ? rb[15] : rb[14];
+ assign _1276_ = rs[8] ? rb[19] : rb[18];
+ assign _1277_ = rs[8] ? rb[23] : rb[22];
+ assign _1278_ = rs[8] ? rb[27] : rb[26];
+ assign _1279_ = rs[8] ? rb[31] : rb[30];
+ assign _1280_ = rs[8] ? rb[35] : rb[34];
+ assign _1281_ = rs[8] ? rb[39] : rb[38];
+ assign _1282_ = rs[8] ? rb[43] : rb[42];
+ assign _1283_ = rs[8] ? rb[47] : rb[46];
+ assign _1284_ = rs[8] ? rb[51] : rb[50];
+ assign _1285_ = rs[8] ? rb[55] : rb[54];
+ assign _1286_ = rs[8] ? rb[59] : rb[58];
+ assign _1287_ = rs[8] ? rb[63] : rb[62];
+ assign _1288_ = rs[10] ? _0939_ : _0938_;
+ assign _1289_ = rs[10] ? _0943_ : _0942_;
+ assign _1290_ = rs[10] ? _0947_ : _0946_;
+ assign _1291_ = rs[10] ? _0951_ : _0950_;
+ assign _1292_ = rs[12] ? _0955_ : _0954_;
+ assign _1293_ = rs[16] ? rb[3] : rb[2];
+ assign _1294_ = rs[16] ? rb[7] : rb[6];
+ assign _1295_ = rs[16] ? rb[11] : rb[10];
+ assign _1296_ = rs[16] ? rb[15] : rb[14];
+ assign _1297_ = rs[16] ? rb[19] : rb[18];
+ assign _1298_ = rs[16] ? rb[23] : rb[22];
+ assign _1299_ = rs[16] ? rb[27] : rb[26];
+ assign _1300_ = rs[16] ? rb[31] : rb[30];
+ assign _1301_ = rs[16] ? rb[35] : rb[34];
+ assign _1302_ = rs[16] ? rb[39] : rb[38];
+ assign _1303_ = rs[16] ? rb[43] : rb[42];
+ assign _1304_ = rs[16] ? rb[47] : rb[46];
+ assign _1305_ = rs[16] ? rb[51] : rb[50];
+ assign _1306_ = rs[16] ? rb[55] : rb[54];
+ assign _1307_ = rs[16] ? rb[59] : rb[58];
+ assign _1308_ = rs[16] ? rb[63] : rb[62];
+ assign _1309_ = rs[18] ? _0960_ : _0959_;
+ assign _1310_ = rs[18] ? _0964_ : _0963_;
+ assign _1311_ = rs[18] ? _0968_ : _0967_;
+ assign _1312_ = rs[18] ? _0972_ : _0971_;
+ assign _1313_ = rs[20] ? _0976_ : _0975_;
+ assign _1314_ = rs[24] ? rb[3] : rb[2];
+ assign _1315_ = rs[24] ? rb[7] : rb[6];
+ assign _1316_ = rs[24] ? rb[11] : rb[10];
+ assign _1317_ = rs[24] ? rb[15] : rb[14];
+ assign _1318_ = rs[24] ? rb[19] : rb[18];
+ assign _1319_ = rs[24] ? rb[23] : rb[22];
+ assign _1320_ = rs[24] ? rb[27] : rb[26];
+ assign _1321_ = rs[24] ? rb[31] : rb[30];
+ assign _1322_ = rs[24] ? rb[35] : rb[34];
+ assign _1323_ = rs[24] ? rb[39] : rb[38];
+ assign _1324_ = rs[24] ? rb[43] : rb[42];
+ assign _1325_ = rs[24] ? rb[47] : rb[46];
+ assign _1326_ = rs[24] ? rb[51] : rb[50];
+ assign _1327_ = rs[24] ? rb[55] : rb[54];
+ assign _1328_ = rs[24] ? rb[59] : rb[58];
+ assign _1329_ = rs[24] ? rb[63] : rb[62];
+ assign _1330_ = rs[26] ? _0981_ : _0980_;
+ assign _1331_ = rs[26] ? _0985_ : _0984_;
+ assign _1332_ = rs[26] ? _0989_ : _0988_;
+ assign _1333_ = rs[26] ? _0993_ : _0992_;
+ assign _1334_ = rs[28] ? _0997_ : _0996_;
+ assign _1335_ = rs[32] ? rb[3] : rb[2];
+ assign _1336_ = rs[32] ? rb[7] : rb[6];
+ assign _1337_ = rs[32] ? rb[11] : rb[10];
+ assign _1338_ = rs[32] ? rb[15] : rb[14];
+ assign _1339_ = rs[32] ? rb[19] : rb[18];
+ assign _1340_ = rs[32] ? rb[23] : rb[22];
+ assign _1341_ = rs[32] ? rb[27] : rb[26];
+ assign _1342_ = rs[32] ? rb[31] : rb[30];
+ assign _1343_ = rs[32] ? rb[35] : rb[34];
+ assign _1344_ = rs[32] ? rb[39] : rb[38];
+ assign _1345_ = rs[32] ? rb[43] : rb[42];
+ assign _1346_ = rs[32] ? rb[47] : rb[46];
+ assign _1347_ = rs[32] ? rb[51] : rb[50];
+ assign _1348_ = rs[32] ? rb[55] : rb[54];
+ assign _1349_ = rs[32] ? rb[59] : rb[58];
+ assign _1350_ = rs[32] ? rb[63] : rb[62];
+ assign _1351_ = rs[34] ? _1002_ : _1001_;
+ assign _1352_ = rs[34] ? _1006_ : _1005_;
+ assign _1353_ = rs[34] ? _1010_ : _1009_;
+ assign _1354_ = rs[34] ? _1014_ : _1013_;
+ assign _1355_ = rs[36] ? _1018_ : _1017_;
+ assign _1356_ = rs[40] ? rb[3] : rb[2];
+ assign _1357_ = rs[40] ? rb[7] : rb[6];
+ assign _1358_ = rs[40] ? rb[11] : rb[10];
+ assign _1359_ = rs[40] ? rb[15] : rb[14];
+ assign _1360_ = rs[40] ? rb[19] : rb[18];
+ assign _1361_ = rs[40] ? rb[23] : rb[22];
+ assign _1362_ = rs[40] ? rb[27] : rb[26];
+ assign _1363_ = rs[40] ? rb[31] : rb[30];
+ assign _1364_ = rs[40] ? rb[35] : rb[34];
+ assign _1365_ = rs[40] ? rb[39] : rb[38];
+ assign _1366_ = rs[40] ? rb[43] : rb[42];
+ assign _1367_ = rs[40] ? rb[47] : rb[46];
+ assign _1368_ = rs[40] ? rb[51] : rb[50];
+ assign _1369_ = rs[40] ? rb[55] : rb[54];
+ assign _1370_ = rs[40] ? rb[59] : rb[58];
+ assign _1371_ = rs[40] ? rb[63] : rb[62];
+ assign _1372_ = rs[42] ? _1023_ : _1022_;
+ assign _1373_ = rs[42] ? _1027_ : _1026_;
+ assign _1374_ = rs[42] ? _1031_ : _1030_;
+ assign _1375_ = rs[42] ? _1035_ : _1034_;
+ assign _1376_ = rs[44] ? _1039_ : _1038_;
+ assign _1377_ = rs[48] ? rb[3] : rb[2];
+ assign _1378_ = rs[48] ? rb[7] : rb[6];
+ assign _1379_ = rs[48] ? rb[11] : rb[10];
+ assign _1380_ = rs[48] ? rb[15] : rb[14];
+ assign _1381_ = rs[48] ? rb[19] : rb[18];
+ assign _1382_ = rs[48] ? rb[23] : rb[22];
+ assign _1383_ = rs[48] ? rb[27] : rb[26];
+ assign _1384_ = rs[48] ? rb[31] : rb[30];
+ assign _1385_ = rs[48] ? rb[35] : rb[34];
+ assign _1386_ = rs[48] ? rb[39] : rb[38];
+ assign _1387_ = rs[48] ? rb[43] : rb[42];
+ assign _1388_ = rs[48] ? rb[47] : rb[46];
+ assign _1389_ = rs[48] ? rb[51] : rb[50];
+ assign _1390_ = rs[48] ? rb[55] : rb[54];
+ assign _1391_ = rs[48] ? rb[59] : rb[58];
+ assign _1392_ = rs[48] ? rb[63] : rb[62];
+ assign _1393_ = rs[50] ? _1044_ : _1043_;
+ assign _1394_ = rs[50] ? _1048_ : _1047_;
+ assign _1395_ = rs[50] ? _1052_ : _1051_;
+ assign _1396_ = rs[50] ? _1056_ : _1055_;
+ assign _1397_ = rs[52] ? _1060_ : _1059_;
+ assign _1398_ = rs[56] ? rb[3] : rb[2];
+ assign _1399_ = rs[56] ? rb[7] : rb[6];
+ assign _1400_ = rs[56] ? rb[11] : rb[10];
+ assign _1401_ = rs[56] ? rb[15] : rb[14];
+ assign _1402_ = rs[56] ? rb[19] : rb[18];
+ assign _1403_ = rs[56] ? rb[23] : rb[22];
+ assign _1404_ = rs[56] ? rb[27] : rb[26];
+ assign _1405_ = rs[56] ? rb[31] : rb[30];
+ assign _1406_ = rs[56] ? rb[35] : rb[34];
+ assign _1407_ = rs[56] ? rb[39] : rb[38];
+ assign _1408_ = rs[56] ? rb[43] : rb[42];
+ assign _1409_ = rs[56] ? rb[47] : rb[46];
+ assign _1410_ = rs[56] ? rb[51] : rb[50];
+ assign _1411_ = rs[56] ? rb[55] : rb[54];
+ assign _1412_ = rs[56] ? rb[59] : rb[58];
+ assign _1413_ = rs[56] ? rb[63] : rb[62];
+ assign _1414_ = rs[58] ? _1065_ : _1064_;
+ assign _1415_ = rs[58] ? _1069_ : _1068_;
+ assign _1416_ = rs[58] ? _1073_ : _1072_;
+ assign _1417_ = rs[58] ? _1077_ : _1076_;
+ assign _1418_ = rs[60] ? _1081_ : _1080_;
+ assign _0915_ = rs[1] ? _1251_ : _1083_;
+ assign _0916_ = rs[1] ? _1252_ : _1084_;
+ assign _0917_ = rs[1] ? _1253_ : _1085_;
+ assign _0918_ = rs[1] ? _1254_ : _1086_;
+ assign _0919_ = rs[1] ? _1255_ : _1087_;
+ assign _0920_ = rs[1] ? _1256_ : _1088_;
+ assign _0921_ = rs[1] ? _1257_ : _1089_;
+ assign _0922_ = rs[1] ? _1258_ : _1090_;
+ assign _0923_ = rs[1] ? _1259_ : _1091_;
+ assign _0924_ = rs[1] ? _1260_ : _1092_;
+ assign _0925_ = rs[1] ? _1261_ : _1093_;
+ assign _0926_ = rs[1] ? _1262_ : _1094_;
+ assign _0927_ = rs[1] ? _1263_ : _1095_;
+ assign _0928_ = rs[1] ? _1264_ : _1096_;
+ assign _0929_ = rs[1] ? _1265_ : _1097_;
+ assign _0930_ = rs[1] ? _1266_ : _1098_;
+ assign _0931_ = rs[3] ? _1267_ : _1099_;
+ assign _0932_ = rs[3] ? _1268_ : _1100_;
+ assign _0933_ = rs[3] ? _1269_ : _1101_;
+ assign _0934_ = rs[3] ? _1270_ : _1102_;
+ assign _0935_ = rs[5] ? _1271_ : _1103_;
+ assign _0936_ = rs[9] ? _1272_ : _1104_;
+ assign _0937_ = rs[9] ? _1273_ : _1105_;
+ assign _0938_ = rs[9] ? _1274_ : _1106_;
+ assign _0939_ = rs[9] ? _1275_ : _1107_;
+ assign _0940_ = rs[9] ? _1276_ : _1108_;
+ assign _0941_ = rs[9] ? _1277_ : _1109_;
+ assign _0942_ = rs[9] ? _1278_ : _1110_;
+ assign _0943_ = rs[9] ? _1279_ : _1111_;
+ assign _0944_ = rs[9] ? _1280_ : _1112_;
+ assign _0945_ = rs[9] ? _1281_ : _1113_;
+ assign _0946_ = rs[9] ? _1282_ : _1114_;
+ assign _0947_ = rs[9] ? _1283_ : _1115_;
+ assign _0948_ = rs[9] ? _1284_ : _1116_;
+ assign _0949_ = rs[9] ? _1285_ : _1117_;
+ assign _0950_ = rs[9] ? _1286_ : _1118_;
+ assign _0951_ = rs[9] ? _1287_ : _1119_;
+ assign _0952_ = rs[11] ? _1288_ : _1120_;
+ assign _0953_ = rs[11] ? _1289_ : _1121_;
+ assign _0954_ = rs[11] ? _1290_ : _1122_;
+ assign _0955_ = rs[11] ? _1291_ : _1123_;
+ assign _0956_ = rs[13] ? _1292_ : _1124_;
+ assign _0957_ = rs[17] ? _1293_ : _1125_;
+ assign _0958_ = rs[17] ? _1294_ : _1126_;
+ assign _0959_ = rs[17] ? _1295_ : _1127_;
+ assign _0960_ = rs[17] ? _1296_ : _1128_;
+ assign _0961_ = rs[17] ? _1297_ : _1129_;
+ assign _0962_ = rs[17] ? _1298_ : _1130_;
+ assign _0963_ = rs[17] ? _1299_ : _1131_;
+ assign _0964_ = rs[17] ? _1300_ : _1132_;
+ assign _0965_ = rs[17] ? _1301_ : _1133_;
+ assign _0966_ = rs[17] ? _1302_ : _1134_;
+ assign _0967_ = rs[17] ? _1303_ : _1135_;
+ assign _0968_ = rs[17] ? _1304_ : _1136_;
+ assign _0969_ = rs[17] ? _1305_ : _1137_;
+ assign _0970_ = rs[17] ? _1306_ : _1138_;
+ assign _0971_ = rs[17] ? _1307_ : _1139_;
+ assign _0972_ = rs[17] ? _1308_ : _1140_;
+ assign _0973_ = rs[19] ? _1309_ : _1141_;
+ assign _0974_ = rs[19] ? _1310_ : _1142_;
+ assign _0975_ = rs[19] ? _1311_ : _1143_;
+ assign _0976_ = rs[19] ? _1312_ : _1144_;
+ assign _0977_ = rs[21] ? _1313_ : _1145_;
+ assign _0978_ = rs[25] ? _1314_ : _1146_;
+ assign _0979_ = rs[25] ? _1315_ : _1147_;
+ assign _0980_ = rs[25] ? _1316_ : _1148_;
+ assign _0981_ = rs[25] ? _1317_ : _1149_;
+ assign _0982_ = rs[25] ? _1318_ : _1150_;
+ assign _0983_ = rs[25] ? _1319_ : _1151_;
+ assign _0984_ = rs[25] ? _1320_ : _1152_;
+ assign _0985_ = rs[25] ? _1321_ : _1153_;
+ assign _0986_ = rs[25] ? _1322_ : _1154_;
+ assign _0987_ = rs[25] ? _1323_ : _1155_;
+ assign _0988_ = rs[25] ? _1324_ : _1156_;
+ assign _0989_ = rs[25] ? _1325_ : _1157_;
+ assign _0990_ = rs[25] ? _1326_ : _1158_;
+ assign _0991_ = rs[25] ? _1327_ : _1159_;
+ assign _0992_ = rs[25] ? _1328_ : _1160_;
+ assign _0993_ = rs[25] ? _1329_ : _1161_;
+ assign _0994_ = rs[27] ? _1330_ : _1162_;
+ assign _0995_ = rs[27] ? _1331_ : _1163_;
+ assign _0996_ = rs[27] ? _1332_ : _1164_;
+ assign _0997_ = rs[27] ? _1333_ : _1165_;
+ assign _0998_ = rs[29] ? _1334_ : _1166_;
+ assign _0999_ = rs[33] ? _1335_ : _1167_;
+ assign _1000_ = rs[33] ? _1336_ : _1168_;
+ assign _1001_ = rs[33] ? _1337_ : _1169_;
+ assign _1002_ = rs[33] ? _1338_ : _1170_;
+ assign _1003_ = rs[33] ? _1339_ : _1171_;
+ assign _1004_ = rs[33] ? _1340_ : _1172_;
+ assign _1005_ = rs[33] ? _1341_ : _1173_;
+ assign _1006_ = rs[33] ? _1342_ : _1174_;
+ assign _1007_ = rs[33] ? _1343_ : _1175_;
+ assign _1008_ = rs[33] ? _1344_ : _1176_;
+ assign _1009_ = rs[33] ? _1345_ : _1177_;
+ assign _1010_ = rs[33] ? _1346_ : _1178_;
+ assign _1011_ = rs[33] ? _1347_ : _1179_;
+ assign _1012_ = rs[33] ? _1348_ : _1180_;
+ assign _1013_ = rs[33] ? _1349_ : _1181_;
+ assign _1014_ = rs[33] ? _1350_ : _1182_;
+ assign _1015_ = rs[35] ? _1351_ : _1183_;
+ assign _1016_ = rs[35] ? _1352_ : _1184_;
+ assign _1017_ = rs[35] ? _1353_ : _1185_;
+ assign _1018_ = rs[35] ? _1354_ : _1186_;
+ assign _1019_ = rs[37] ? _1355_ : _1187_;
+ assign _1020_ = rs[41] ? _1356_ : _1188_;
+ assign _1021_ = rs[41] ? _1357_ : _1189_;
+ assign _1022_ = rs[41] ? _1358_ : _1190_;
+ assign _1023_ = rs[41] ? _1359_ : _1191_;
+ assign _1024_ = rs[41] ? _1360_ : _1192_;
+ assign _1025_ = rs[41] ? _1361_ : _1193_;
+ assign _1026_ = rs[41] ? _1362_ : _1194_;
+ assign _1027_ = rs[41] ? _1363_ : _1195_;
+ assign _1028_ = rs[41] ? _1364_ : _1196_;
+ assign _1029_ = rs[41] ? _1365_ : _1197_;
+ assign _1030_ = rs[41] ? _1366_ : _1198_;
+ assign _1031_ = rs[41] ? _1367_ : _1199_;
+ assign _1032_ = rs[41] ? _1368_ : _1200_;
+ assign _1033_ = rs[41] ? _1369_ : _1201_;
+ assign _1034_ = rs[41] ? _1370_ : _1202_;
+ assign _1035_ = rs[41] ? _1371_ : _1203_;
+ assign _1036_ = rs[43] ? _1372_ : _1204_;
+ assign _1037_ = rs[43] ? _1373_ : _1205_;
+ assign _1038_ = rs[43] ? _1374_ : _1206_;
+ assign _1039_ = rs[43] ? _1375_ : _1207_;
+ assign _1040_ = rs[45] ? _1376_ : _1208_;
+ assign _1041_ = rs[49] ? _1377_ : _1209_;
+ assign _1042_ = rs[49] ? _1378_ : _1210_;
+ assign _1043_ = rs[49] ? _1379_ : _1211_;
+ assign _1044_ = rs[49] ? _1380_ : _1212_;
+ assign _1045_ = rs[49] ? _1381_ : _1213_;
+ assign _1046_ = rs[49] ? _1382_ : _1214_;
+ assign _1047_ = rs[49] ? _1383_ : _1215_;
+ assign _1048_ = rs[49] ? _1384_ : _1216_;
+ assign _1049_ = rs[49] ? _1385_ : _1217_;
+ assign _1050_ = rs[49] ? _1386_ : _1218_;
+ assign _1051_ = rs[49] ? _1387_ : _1219_;
+ assign _1052_ = rs[49] ? _1388_ : _1220_;
+ assign _1053_ = rs[49] ? _1389_ : _1221_;
+ assign _1054_ = rs[49] ? _1390_ : _1222_;
+ assign _1055_ = rs[49] ? _1391_ : _1223_;
+ assign _1056_ = rs[49] ? _1392_ : _1224_;
+ assign _1057_ = rs[51] ? _1393_ : _1225_;
+ assign _1058_ = rs[51] ? _1394_ : _1226_;
+ assign _1059_ = rs[51] ? _1395_ : _1227_;
+ assign _1060_ = rs[51] ? _1396_ : _1228_;
+ assign _1061_ = rs[53] ? _1397_ : _1229_;
+ assign _1062_ = rs[57] ? _1398_ : _1230_;
+ assign _1063_ = rs[57] ? _1399_ : _1231_;
+ assign _1064_ = rs[57] ? _1400_ : _1232_;
+ assign _1065_ = rs[57] ? _1401_ : _1233_;
+ assign _1066_ = rs[57] ? _1402_ : _1234_;
+ assign _1067_ = rs[57] ? _1403_ : _1235_;
+ assign _1068_ = rs[57] ? _1404_ : _1236_;
+ assign _1069_ = rs[57] ? _1405_ : _1237_;
+ assign _1070_ = rs[57] ? _1406_ : _1238_;
+ assign _1071_ = rs[57] ? _1407_ : _1239_;
+ assign _1072_ = rs[57] ? _1408_ : _1240_;
+ assign _1073_ = rs[57] ? _1409_ : _1241_;
+ assign _1074_ = rs[57] ? _1410_ : _1242_;
+ assign _1075_ = rs[57] ? _1411_ : _1243_;
+ assign _1076_ = rs[57] ? _1412_ : _1244_;
+ assign _1077_ = rs[57] ? _1413_ : _1245_;
+ assign _1078_ = rs[59] ? _1414_ : _1246_;
+ assign _1079_ = rs[59] ? _1415_ : _1247_;
+ assign _1080_ = rs[59] ? _1416_ : _1248_;
+ assign _1081_ = rs[59] ? _1417_ : _1249_;
+ assign _1082_ = rs[61] ? _1418_ : _1250_;
+ assign _0000_ = { 1'h0, rs[0] } + { 1'h0, rs[1] };
+ assign _0001_ = { 1'h0, rs[2] } + { 1'h0, rs[3] };
+ assign _0002_ = { 1'h0, rs[4] } + { 1'h0, rs[5] };
+ assign _0003_ = { 1'h0, rs[6] } + { 1'h0, rs[7] };
+ assign _0004_ = { 1'h0, rs[8] } + { 1'h0, rs[9] };
+ assign _0005_ = { 1'h0, rs[10] } + { 1'h0, rs[11] };
+ assign _0006_ = { 1'h0, rs[12] } + { 1'h0, rs[13] };
+ assign _0007_ = { 1'h0, rs[14] } + { 1'h0, rs[15] };
+ assign _0008_ = { 1'h0, rs[16] } + { 1'h0, rs[17] };
+ assign _0009_ = { 1'h0, rs[18] } + { 1'h0, rs[19] };
+ assign _0010_ = { 1'h0, rs[20] } + { 1'h0, rs[21] };
+ assign _0011_ = { 1'h0, rs[22] } + { 1'h0, rs[23] };
+ assign _0012_ = { 1'h0, rs[24] } + { 1'h0, rs[25] };
+ assign _0013_ = { 1'h0, rs[26] } + { 1'h0, rs[27] };
+ assign _0014_ = { 1'h0, rs[28] } + { 1'h0, rs[29] };
+ assign _0015_ = { 1'h0, rs[30] } + { 1'h0, rs[31] };
+ assign _0016_ = { 1'h0, rs[32] } + { 1'h0, rs[33] };
+ assign _0017_ = { 1'h0, rs[34] } + { 1'h0, rs[35] };
+ assign _0018_ = { 1'h0, rs[36] } + { 1'h0, rs[37] };
+ assign _0019_ = { 1'h0, rs[38] } + { 1'h0, rs[39] };
+ assign _0020_ = { 1'h0, rs[40] } + { 1'h0, rs[41] };
+ assign _0021_ = { 1'h0, rs[42] } + { 1'h0, rs[43] };
+ assign _0022_ = { 1'h0, rs[44] } + { 1'h0, rs[45] };
+ assign _0023_ = { 1'h0, rs[46] } + { 1'h0, rs[47] };
+ assign _0024_ = { 1'h0, rs[48] } + { 1'h0, rs[49] };
+ assign _0025_ = { 1'h0, rs[50] } + { 1'h0, rs[51] };
+ assign _0026_ = { 1'h0, rs[52] } + { 1'h0, rs[53] };
+ assign _0027_ = { 1'h0, rs[54] } + { 1'h0, rs[55] };
+ assign _0028_ = { 1'h0, rs[56] } + { 1'h0, rs[57] };
+ assign _0029_ = { 1'h0, rs[58] } + { 1'h0, rs[59] };
+ assign _0030_ = { 1'h0, rs[60] } + { 1'h0, rs[61] };
+ assign _0031_ = { 1'h0, rs[62] } + { 1'h0, rs[63] };
+ assign _0032_ = { 1'h0, _0000_ } + { 1'h0, _0001_ };
+ assign _0033_ = { 1'h0, _0002_ } + { 1'h0, _0003_ };
+ assign _0034_ = { 1'h0, _0004_ } + { 1'h0, _0005_ };
+ assign _0035_ = { 1'h0, _0006_ } + { 1'h0, _0007_ };
+ assign _0036_ = { 1'h0, _0008_ } + { 1'h0, _0009_ };
+ assign _0037_ = { 1'h0, _0010_ } + { 1'h0, _0011_ };
+ assign _0038_ = { 1'h0, _0012_ } + { 1'h0, _0013_ };
+ assign _0039_ = { 1'h0, _0014_ } + { 1'h0, _0015_ };
+ assign _0040_ = { 1'h0, _0016_ } + { 1'h0, _0017_ };
+ assign _0041_ = { 1'h0, _0018_ } + { 1'h0, _0019_ };
+ assign _0042_ = { 1'h0, _0020_ } + { 1'h0, _0021_ };
+ assign _0043_ = { 1'h0, _0022_ } + { 1'h0, _0023_ };
+ assign _0044_ = { 1'h0, _0024_ } + { 1'h0, _0025_ };
+ assign _0045_ = { 1'h0, _0026_ } + { 1'h0, _0027_ };
+ assign _0046_ = { 1'h0, _0028_ } + { 1'h0, _0029_ };
+ assign _0047_ = { 1'h0, _0030_ } + { 1'h0, _0031_ };
+ assign _0048_ = { 1'h0, _0032_ } + { 1'h0, _0033_ };
+ assign _0049_ = { 1'h0, _0034_ } + { 1'h0, _0035_ };
+ assign _0050_ = { 1'h0, _0036_ } + { 1'h0, _0037_ };
+ assign _0051_ = { 1'h0, _0038_ } + { 1'h0, _0039_ };
+ assign _0052_ = { 1'h0, _0040_ } + { 1'h0, _0041_ };
+ assign _0053_ = { 1'h0, _0042_ } + { 1'h0, _0043_ };
+ assign _0054_ = { 1'h0, _0044_ } + { 1'h0, _0045_ };
+ assign _0055_ = { 1'h0, _0046_ } + { 1'h0, _0047_ };
+ assign _0056_ = { 2'h0, _0048_ } + { 2'h0, _0049_ };
+ assign _0057_ = _0056_ + { 2'h0, _0050_ };
+ assign _0058_ = _0057_ + { 2'h0, _0051_ };
+ assign _0059_ = { 2'h0, _0052_ } + { 2'h0, _0053_ };
+ assign _0060_ = _0059_ + { 2'h0, _0054_ };
+ assign _0061_ = _0060_ + { 2'h0, _0055_ };
+ assign _0062_ = datalen[3:2] == 2'h0;
+ assign _0063_ = ~ datalen[3];
+ assign _0064_ = { 1'h0, _0058_ } + { 1'h0, _0061_ };
+ assign _0065_ = _0063_ ? _0058_ : _0064_[5:0];
+ assign _0066_ = _0063_ ? 1'h0 : _0064_[6];
+ assign _0067_ = _0063_ ? _0061_ : 6'h00;
+ assign _0068_ = _0062_ ? _0048_ : _0065_[3:0];
+ assign _0069_ = _0062_ ? 3'h0 : { _0066_, _0065_[5:4] };
+ assign _0070_ = _0062_ ? _0049_ : 4'h0;
+ assign _0071_ = _0062_ ? _0050_ : 4'h0;
+ assign _0072_ = _0062_ ? _0051_ : 4'h0;
+ assign _0073_ = _0062_ ? _0052_ : _0067_[3:0];
+ assign _0074_ = _0062_ ? 2'h0 : _0067_[5:4];
+ assign _0075_ = _0062_ ? _0053_ : 4'h0;
+ assign _0076_ = _0062_ ? _0054_ : 4'h0;
+ assign _0077_ = _0062_ ? _0055_ : 4'h0;
+ assign _0078_ = rs[0] ^ rs[8];
+ assign _0079_ = _0078_ ^ rs[16];
+ assign par0 = _0079_ ^ rs[24];
+ assign _0080_ = rs[32] ^ rs[40];
+ assign _0081_ = _0080_ ^ rs[48];
+ assign par1 = _0081_ ^ rs[56];
+ assign _0082_ = par0 ^ par1;
+ assign _0083_ = datalen[3] ? _0082_ : par0;
+ assign _0084_ = datalen[3] ? 1'h0 : par1;
+ assign _0085_ = rs[7:6] == 2'h0;
+ assign _0086_ = _0085_ ? _0935_ : 1'h0;
+ assign _0087_ = rs[15:14] == 2'h0;
+ assign _0088_ = _0087_ ? _0956_ : 1'h0;
+ assign _0089_ = rs[23:22] == 2'h0;
+ assign _0090_ = _0089_ ? _0977_ : 1'h0;
+ assign _0091_ = rs[31:30] == 2'h0;
+ assign _0092_ = _0091_ ? _0998_ : 1'h0;
+ assign _0093_ = rs[39:38] == 2'h0;
+ assign _0094_ = _0093_ ? _1019_ : 1'h0;
+ assign _0095_ = rs[47:46] == 2'h0;
+ assign _0096_ = _0095_ ? _1040_ : 1'h0;
+ assign _0097_ = rs[55:54] == 2'h0;
+ assign _0098_ = _0097_ ? _1061_ : 1'h0;
+ assign _0099_ = rs[63:62] == 2'h0;
+ assign _0100_ = _0099_ ? _1082_ : 1'h0;
+ assign _0101_ = ~ rb;
+ assign _0102_ = invert_in ? _0101_ : rb;
+ assign _0103_ = rs & _0102_;
+ assign _0104_ = op == 6'h03;
+ assign _0105_ = rs | _0102_;
+ assign _0106_ = op == 6'h2e;
+ assign _0107_ = rs ^ _0102_;
+ function [63:0] \22355 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \22355 = b[63:0];
+ 2'b1?:
+ \22355 = b[127:64];
+ default:
+ \22355 = a;
+ endcase
+ endfunction
+ assign _0108_ = \22355 (_0107_, { _0105_, _0103_ }, { _0106_, _0104_ });
+ assign _0109_ = ~ _0108_;
+ assign _0110_ = invert_out ? _0109_ : _0108_;
+ assign _0111_ = op == 6'h03;
+ assign _0112_ = op == 6'h2e;
+ assign _0113_ = _0111_ | _0112_;
+ assign _0114_ = op == 6'h3c;
+ assign _0115_ = _0113_ | _0114_;
+ assign _0116_ = op == 6'h2f;
+ assign _0117_ = op == 6'h30;
+ assign _0118_ = rs[7:0] == rb[7:0];
+ assign _0119_ = _0118_ ? 8'hff : 8'h00;
+ assign _0120_ = rs[15:8] == rb[15:8];
+ assign _0121_ = _0120_ ? 8'hff : 8'h00;
+ assign _0122_ = rs[23:16] == rb[23:16];
+ assign _0123_ = _0122_ ? 8'hff : 8'h00;
+ assign _0124_ = rs[31:24] == rb[31:24];
+ assign _0125_ = _0124_ ? 8'hff : 8'h00;
+ assign _0126_ = rs[39:32] == rb[39:32];
+ assign _0127_ = _0126_ ? 8'hff : 8'h00;
+ assign _0128_ = rs[47:40] == rb[47:40];
+ assign _0129_ = _0128_ ? 8'hff : 8'h00;
+ assign _0130_ = rs[55:48] == rb[55:48];
+ assign _0131_ = _0130_ ? 8'hff : 8'h00;
+ assign _0132_ = rs[63:56] == rb[63:56];
+ assign _0133_ = _0132_ ? 8'hff : 8'h00;
+ assign _0134_ = op == 6'h0a;
+ assign _0135_ = op == 6'h08;
+ assign _0136_ = ~ invert_in;
+ assign _0137_ = rs[50] & rs[55];
+ assign _0138_ = _0137_ & rs[47];
+ assign _0139_ = ~ rs[51];
+ assign _0140_ = _0138_ & _0139_;
+ assign _0141_ = rs[46] & rs[55];
+ assign _0142_ = ~ rs[47];
+ assign _0143_ = _0141_ & _0142_;
+ assign _0144_ = _0140_ | _0143_;
+ assign _0145_ = ~ rs[55];
+ assign _0146_ = rs[54] & _0145_;
+ assign _0147_ = _0144_ | _0146_;
+ assign _0148_ = rs[49] & rs[55];
+ assign _0149_ = _0148_ & rs[47];
+ assign _0150_ = ~ rs[51];
+ assign _0151_ = _0149_ & _0150_;
+ assign _0152_ = rs[45] & rs[55];
+ assign _0153_ = ~ rs[47];
+ assign _0154_ = _0152_ & _0153_;
+ assign _0155_ = _0151_ | _0154_;
+ assign _0156_ = ~ rs[55];
+ assign _0157_ = rs[53] & _0156_;
+ assign _0158_ = _0155_ | _0157_;
+ assign _0159_ = ~ rs[55];
+ assign _0160_ = rs[46] & _0159_;
+ assign _0161_ = _0160_ & rs[51];
+ assign _0162_ = ~ rs[47];
+ assign _0163_ = _0161_ & _0162_;
+ assign _0164_ = ~ rs[47];
+ assign _0165_ = rs[50] & _0164_;
+ assign _0166_ = ~ rs[51];
+ assign _0167_ = _0165_ & _0166_;
+ assign _0168_ = _0163_ | _0167_;
+ assign _0169_ = ~ rs[55];
+ assign _0170_ = rs[50] & _0169_;
+ assign _0171_ = ~ rs[51];
+ assign _0172_ = _0170_ & _0171_;
+ assign _0173_ = _0168_ | _0172_;
+ assign _0174_ = rs[51] & rs[47];
+ assign _0175_ = _0173_ | _0174_;
+ assign _0176_ = ~ rs[55];
+ assign _0177_ = rs[45] & _0176_;
+ assign _0178_ = _0177_ & rs[51];
+ assign _0179_ = ~ rs[47];
+ assign _0180_ = _0178_ & _0179_;
+ assign _0181_ = ~ rs[47];
+ assign _0182_ = rs[49] & _0181_;
+ assign _0183_ = ~ rs[51];
+ assign _0184_ = _0182_ & _0183_;
+ assign _0185_ = _0180_ | _0184_;
+ assign _0186_ = ~ rs[55];
+ assign _0187_ = rs[49] & _0186_;
+ assign _0188_ = ~ rs[51];
+ assign _0189_ = _0187_ & _0188_;
+ assign _0190_ = _0185_ | _0189_;
+ assign _0191_ = rs[55] & rs[47];
+ assign _0192_ = _0190_ | _0191_;
+ assign _0193_ = rs[55] | rs[51];
+ assign _0194_ = _0193_ | rs[47];
+ assign _0195_ = ~ rs[51];
+ assign _0196_ = _0195_ & rs[46];
+ assign _0197_ = ~ rs[47];
+ assign _0198_ = _0196_ & _0197_;
+ assign _0199_ = rs[51] & rs[47];
+ assign _0200_ = _0198_ | _0199_;
+ assign _0201_ = _0200_ | rs[55];
+ assign _0202_ = ~ rs[55];
+ assign _0203_ = _0202_ & rs[45];
+ assign _0204_ = ~ rs[47];
+ assign _0205_ = _0203_ & _0204_;
+ assign _0206_ = rs[55] & rs[47];
+ assign _0207_ = _0205_ | _0206_;
+ assign _0208_ = _0207_ | rs[51];
+ assign _0209_ = rs[38] & rs[43];
+ assign _0210_ = _0209_ & rs[35];
+ assign _0211_ = ~ rs[39];
+ assign _0212_ = _0210_ & _0211_;
+ assign _0213_ = rs[34] & rs[43];
+ assign _0214_ = ~ rs[35];
+ assign _0215_ = _0213_ & _0214_;
+ assign _0216_ = _0212_ | _0215_;
+ assign _0217_ = ~ rs[43];
+ assign _0218_ = rs[42] & _0217_;
+ assign _0219_ = _0216_ | _0218_;
+ assign _0220_ = rs[37] & rs[43];
+ assign _0221_ = _0220_ & rs[35];
+ assign _0222_ = ~ rs[39];
+ assign _0223_ = _0221_ & _0222_;
+ assign _0224_ = rs[33] & rs[43];
+ assign _0225_ = ~ rs[35];
+ assign _0226_ = _0224_ & _0225_;
+ assign _0227_ = _0223_ | _0226_;
+ assign _0228_ = ~ rs[43];
+ assign _0229_ = rs[41] & _0228_;
+ assign _0230_ = _0227_ | _0229_;
+ assign _0231_ = ~ rs[43];
+ assign _0232_ = rs[34] & _0231_;
+ assign _0233_ = _0232_ & rs[39];
+ assign _0234_ = ~ rs[35];
+ assign _0235_ = _0233_ & _0234_;
+ assign _0236_ = ~ rs[35];
+ assign _0237_ = rs[38] & _0236_;
+ assign _0238_ = ~ rs[39];
+ assign _0239_ = _0237_ & _0238_;
+ assign _0240_ = _0235_ | _0239_;
+ assign _0241_ = ~ rs[43];
+ assign _0242_ = rs[38] & _0241_;
+ assign _0243_ = ~ rs[39];
+ assign _0244_ = _0242_ & _0243_;
+ assign _0245_ = _0240_ | _0244_;
+ assign _0246_ = rs[39] & rs[35];
+ assign _0247_ = _0245_ | _0246_;
+ assign _0248_ = ~ rs[43];
+ assign _0249_ = rs[33] & _0248_;
+ assign _0250_ = _0249_ & rs[39];
+ assign _0251_ = ~ rs[35];
+ assign _0252_ = _0250_ & _0251_;
+ assign _0253_ = ~ rs[35];
+ assign _0254_ = rs[37] & _0253_;
+ assign _0255_ = ~ rs[39];
+ assign _0256_ = _0254_ & _0255_;
+ assign _0257_ = _0252_ | _0256_;
+ assign _0258_ = ~ rs[43];
+ assign _0259_ = rs[37] & _0258_;
+ assign _0260_ = ~ rs[39];
+ assign _0261_ = _0259_ & _0260_;
+ assign _0262_ = _0257_ | _0261_;
+ assign _0263_ = rs[43] & rs[35];
+ assign _0264_ = _0262_ | _0263_;
+ assign _0265_ = rs[43] | rs[39];
+ assign _0266_ = _0265_ | rs[35];
+ assign _0267_ = ~ rs[39];
+ assign _0268_ = _0267_ & rs[34];
+ assign _0269_ = ~ rs[35];
+ assign _0270_ = _0268_ & _0269_;
+ assign _0271_ = rs[39] & rs[35];
+ assign _0272_ = _0270_ | _0271_;
+ assign _0273_ = _0272_ | rs[43];
+ assign _0274_ = ~ rs[43];
+ assign _0275_ = _0274_ & rs[33];
+ assign _0276_ = ~ rs[35];
+ assign _0277_ = _0275_ & _0276_;
+ assign _0278_ = rs[43] & rs[35];
+ assign _0279_ = _0277_ | _0278_;
+ assign _0280_ = _0279_ | rs[39];
+ assign _0281_ = rs[18] & rs[23];
+ assign _0282_ = _0281_ & rs[15];
+ assign _0283_ = ~ rs[19];
+ assign _0284_ = _0282_ & _0283_;
+ assign _0285_ = rs[14] & rs[23];
+ assign _0286_ = ~ rs[15];
+ assign _0287_ = _0285_ & _0286_;
+ assign _0288_ = _0284_ | _0287_;
+ assign _0289_ = ~ rs[23];
+ assign _0290_ = rs[22] & _0289_;
+ assign _0291_ = _0288_ | _0290_;
+ assign _0292_ = rs[17] & rs[23];
+ assign _0293_ = _0292_ & rs[15];
+ assign _0294_ = ~ rs[19];
+ assign _0295_ = _0293_ & _0294_;
+ assign _0296_ = rs[13] & rs[23];
+ assign _0297_ = ~ rs[15];
+ assign _0298_ = _0296_ & _0297_;
+ assign _0299_ = _0295_ | _0298_;
+ assign _0300_ = ~ rs[23];
+ assign _0301_ = rs[21] & _0300_;
+ assign _0302_ = _0299_ | _0301_;
+ assign _0303_ = ~ rs[23];
+ assign _0304_ = rs[14] & _0303_;
+ assign _0305_ = _0304_ & rs[19];
+ assign _0306_ = ~ rs[15];
+ assign _0307_ = _0305_ & _0306_;
+ assign _0308_ = ~ rs[15];
+ assign _0309_ = rs[18] & _0308_;
+ assign _0310_ = ~ rs[19];
+ assign _0311_ = _0309_ & _0310_;
+ assign _0312_ = _0307_ | _0311_;
+ assign _0313_ = ~ rs[23];
+ assign _0314_ = rs[18] & _0313_;
+ assign _0315_ = ~ rs[19];
+ assign _0316_ = _0314_ & _0315_;
+ assign _0317_ = _0312_ | _0316_;
+ assign _0318_ = rs[19] & rs[15];
+ assign _0319_ = _0317_ | _0318_;
+ assign _0320_ = ~ rs[23];
+ assign _0321_ = rs[13] & _0320_;
+ assign _0322_ = _0321_ & rs[19];
+ assign _0323_ = ~ rs[15];
+ assign _0324_ = _0322_ & _0323_;
+ assign _0325_ = ~ rs[15];
+ assign _0326_ = rs[17] & _0325_;
+ assign _0327_ = ~ rs[19];
+ assign _0328_ = _0326_ & _0327_;
+ assign _0329_ = _0324_ | _0328_;
+ assign _0330_ = ~ rs[23];
+ assign _0331_ = rs[17] & _0330_;
+ assign _0332_ = ~ rs[19];
+ assign _0333_ = _0331_ & _0332_;
+ assign _0334_ = _0329_ | _0333_;
+ assign _0335_ = rs[23] & rs[15];
+ assign _0336_ = _0334_ | _0335_;
+ assign _0337_ = rs[23] | rs[19];
+ assign _0338_ = _0337_ | rs[15];
+ assign _0339_ = ~ rs[19];
+ assign _0340_ = _0339_ & rs[14];
+ assign _0341_ = ~ rs[15];
+ assign _0342_ = _0340_ & _0341_;
+ assign _0343_ = rs[19] & rs[15];
+ assign _0344_ = _0342_ | _0343_;
+ assign _0345_ = _0344_ | rs[23];
+ assign _0346_ = ~ rs[23];
+ assign _0347_ = _0346_ & rs[13];
+ assign _0348_ = ~ rs[15];
+ assign _0349_ = _0347_ & _0348_;
+ assign _0350_ = rs[23] & rs[15];
+ assign _0351_ = _0349_ | _0350_;
+ assign _0352_ = _0351_ | rs[19];
+ assign _0353_ = rs[6] & rs[11];
+ assign _0354_ = _0353_ & rs[3];
+ assign _0355_ = ~ rs[7];
+ assign _0356_ = _0354_ & _0355_;
+ assign _0357_ = rs[2] & rs[11];
+ assign _0358_ = ~ rs[3];
+ assign _0359_ = _0357_ & _0358_;
+ assign _0360_ = _0356_ | _0359_;
+ assign _0361_ = ~ rs[11];
+ assign _0362_ = rs[10] & _0361_;
+ assign _0363_ = _0360_ | _0362_;
+ assign _0364_ = rs[5] & rs[11];
+ assign _0365_ = _0364_ & rs[3];
+ assign _0366_ = ~ rs[7];
+ assign _0367_ = _0365_ & _0366_;
+ assign _0368_ = rs[1] & rs[11];
+ assign _0369_ = ~ rs[3];
+ assign _0370_ = _0368_ & _0369_;
+ assign _0371_ = _0367_ | _0370_;
+ assign _0372_ = ~ rs[11];
+ assign _0373_ = rs[9] & _0372_;
+ assign _0374_ = _0371_ | _0373_;
+ assign _0375_ = ~ rs[11];
+ assign _0376_ = rs[2] & _0375_;
+ assign _0377_ = _0376_ & rs[7];
+ assign _0378_ = ~ rs[3];
+ assign _0379_ = _0377_ & _0378_;
+ assign _0380_ = ~ rs[3];
+ assign _0381_ = rs[6] & _0380_;
+ assign _0382_ = ~ rs[7];
+ assign _0383_ = _0381_ & _0382_;
+ assign _0384_ = _0379_ | _0383_;
+ assign _0385_ = ~ rs[11];
+ assign _0386_ = rs[6] & _0385_;
+ assign _0387_ = ~ rs[7];
+ assign _0388_ = _0386_ & _0387_;
+ assign _0389_ = _0384_ | _0388_;
+ assign _0390_ = rs[7] & rs[3];
+ assign _0391_ = _0389_ | _0390_;
+ assign _0392_ = ~ rs[11];
+ assign _0393_ = rs[1] & _0392_;
+ assign _0394_ = _0393_ & rs[7];
+ assign _0395_ = ~ rs[3];
+ assign _0396_ = _0394_ & _0395_;
+ assign _0397_ = ~ rs[3];
+ assign _0398_ = rs[5] & _0397_;
+ assign _0399_ = ~ rs[7];
+ assign _0400_ = _0398_ & _0399_;
+ assign _0401_ = _0396_ | _0400_;
+ assign _0402_ = ~ rs[11];
+ assign _0403_ = rs[5] & _0402_;
+ assign _0404_ = ~ rs[7];
+ assign _0405_ = _0403_ & _0404_;
+ assign _0406_ = _0401_ | _0405_;
+ assign _0407_ = rs[11] & rs[3];
+ assign _0408_ = _0406_ | _0407_;
+ assign _0409_ = rs[11] | rs[7];
+ assign _0410_ = _0409_ | rs[3];
+ assign _0411_ = ~ rs[7];
+ assign _0412_ = _0411_ & rs[2];
+ assign _0413_ = ~ rs[3];
+ assign _0414_ = _0412_ & _0413_;
+ assign _0415_ = rs[7] & rs[3];
+ assign _0416_ = _0414_ | _0415_;
+ assign _0417_ = _0416_ | rs[11];
+ assign _0418_ = ~ rs[11];
+ assign _0419_ = _0418_ & rs[1];
+ assign _0420_ = ~ rs[3];
+ assign _0421_ = _0419_ & _0420_;
+ assign _0422_ = rs[11] & rs[3];
+ assign _0423_ = _0421_ | _0422_;
+ assign _0424_ = _0423_ | rs[7];
+ assign _0425_ = ~ rs[48];
+ assign _0426_ = _0425_ & rs[45];
+ assign _0427_ = _0426_ & rs[44];
+ assign _0428_ = rs[47] & rs[45];
+ assign _0429_ = _0428_ & rs[44];
+ assign _0430_ = _0429_ & rs[48];
+ assign _0431_ = _0427_ | _0430_;
+ assign _0432_ = rs[45] & rs[44];
+ assign _0433_ = ~ rs[43];
+ assign _0434_ = _0432_ & _0433_;
+ assign _0435_ = _0431_ | _0434_;
+ assign _0436_ = rs[51] & rs[48];
+ assign _0437_ = _0436_ & rs[43];
+ assign _0438_ = ~ rs[47];
+ assign _0439_ = _0437_ & _0438_;
+ assign _0440_ = ~ rs[44];
+ assign _0441_ = rs[51] & _0440_;
+ assign _0442_ = _0439_ | _0441_;
+ assign _0443_ = ~ rs[45];
+ assign _0444_ = rs[51] & _0443_;
+ assign _0445_ = _0442_ | _0444_;
+ assign _0446_ = rs[50] & rs[48];
+ assign _0447_ = _0446_ & rs[43];
+ assign _0448_ = ~ rs[47];
+ assign _0449_ = _0447_ & _0448_;
+ assign _0450_ = ~ rs[44];
+ assign _0451_ = rs[50] & _0450_;
+ assign _0452_ = _0449_ | _0451_;
+ assign _0453_ = ~ rs[45];
+ assign _0454_ = rs[50] & _0453_;
+ assign _0455_ = _0452_ | _0454_;
+ assign _0456_ = ~ rs[44];
+ assign _0457_ = rs[45] & _0456_;
+ assign _0458_ = _0457_ & rs[43];
+ assign _0459_ = rs[48] & rs[45];
+ assign _0460_ = _0459_ & rs[44];
+ assign _0461_ = _0460_ & rs[43];
+ assign _0462_ = _0458_ | _0461_;
+ assign _0463_ = ~ rs[47];
+ assign _0464_ = _0463_ & rs[45];
+ assign _0465_ = _0464_ & rs[44];
+ assign _0466_ = _0465_ & rs[43];
+ assign _0467_ = _0462_ | _0466_;
+ assign _0468_ = rs[51] & rs[47];
+ assign _0469_ = _0468_ & rs[45];
+ assign _0470_ = _0469_ & rs[44];
+ assign _0471_ = _0470_ & rs[43];
+ assign _0472_ = ~ rs[48];
+ assign _0473_ = _0471_ & _0472_;
+ assign _0474_ = ~ rs[43];
+ assign _0475_ = rs[48] & _0474_;
+ assign _0476_ = _0475_ & rs[45];
+ assign _0477_ = _0473_ | _0476_;
+ assign _0478_ = ~ rs[45];
+ assign _0479_ = rs[48] & _0478_;
+ assign _0480_ = _0477_ | _0479_;
+ assign _0481_ = rs[50] & rs[47];
+ assign _0482_ = _0481_ & rs[44];
+ assign _0483_ = _0482_ & rs[45];
+ assign _0484_ = _0483_ & rs[43];
+ assign _0485_ = ~ rs[48];
+ assign _0486_ = _0484_ & _0485_;
+ assign _0487_ = ~ rs[43];
+ assign _0488_ = rs[47] & _0487_;
+ assign _0489_ = _0488_ & rs[45];
+ assign _0490_ = _0486_ | _0489_;
+ assign _0491_ = ~ rs[45];
+ assign _0492_ = rs[47] & _0491_;
+ assign _0493_ = _0490_ | _0492_;
+ assign _0494_ = rs[47] & rs[45];
+ assign _0495_ = _0494_ & rs[44];
+ assign _0496_ = _0495_ & rs[43];
+ assign _0497_ = rs[48] & rs[45];
+ assign _0498_ = _0497_ & rs[44];
+ assign _0499_ = _0498_ & rs[43];
+ assign _0500_ = _0496_ | _0499_;
+ assign _0501_ = ~ rs[44];
+ assign _0502_ = rs[45] & _0501_;
+ assign _0503_ = ~ rs[43];
+ assign _0504_ = _0502_ & _0503_;
+ assign _0505_ = _0500_ | _0504_;
+ assign _0506_ = ~ rs[48];
+ assign _0507_ = rs[51] & _0506_;
+ assign _0508_ = ~ rs[47];
+ assign _0509_ = _0507_ & _0508_;
+ assign _0510_ = _0509_ & rs[44];
+ assign _0511_ = _0510_ & rs[45];
+ assign _0512_ = rs[48] & rs[45];
+ assign _0513_ = ~ rs[44];
+ assign _0514_ = _0512_ & _0513_;
+ assign _0515_ = _0514_ & rs[43];
+ assign _0516_ = _0511_ | _0515_;
+ assign _0517_ = rs[51] & rs[44];
+ assign _0518_ = ~ rs[43];
+ assign _0519_ = _0517_ & _0518_;
+ assign _0520_ = _0519_ & rs[45];
+ assign _0521_ = _0516_ | _0520_;
+ assign _0522_ = ~ rs[45];
+ assign _0523_ = rs[44] & _0522_;
+ assign _0524_ = _0521_ | _0523_;
+ assign _0525_ = ~ rs[48];
+ assign _0526_ = rs[50] & _0525_;
+ assign _0527_ = ~ rs[47];
+ assign _0528_ = _0526_ & _0527_;
+ assign _0529_ = _0528_ & rs[45];
+ assign _0530_ = _0529_ & rs[44];
+ assign _0531_ = rs[47] & rs[45];
+ assign _0532_ = ~ rs[44];
+ assign _0533_ = _0531_ & _0532_;
+ assign _0534_ = _0533_ & rs[43];
+ assign _0535_ = _0530_ | _0534_;
+ assign _0536_ = rs[50] & rs[45];
+ assign _0537_ = _0536_ & rs[44];
+ assign _0538_ = ~ rs[43];
+ assign _0539_ = _0537_ & _0538_;
+ assign _0540_ = _0535_ | _0539_;
+ assign _0541_ = ~ rs[45];
+ assign _0542_ = rs[43] & _0541_;
+ assign _0543_ = _0540_ | _0542_;
+ assign _0544_ = ~ rs[38];
+ assign _0545_ = _0544_ & rs[35];
+ assign _0546_ = _0545_ & rs[34];
+ assign _0547_ = rs[37] & rs[35];
+ assign _0548_ = _0547_ & rs[34];
+ assign _0549_ = _0548_ & rs[38];
+ assign _0550_ = _0546_ | _0549_;
+ assign _0551_ = rs[35] & rs[34];
+ assign _0552_ = ~ rs[33];
+ assign _0553_ = _0551_ & _0552_;
+ assign _0554_ = _0550_ | _0553_;
+ assign _0555_ = rs[41] & rs[38];
+ assign _0556_ = _0555_ & rs[33];
+ assign _0557_ = ~ rs[37];
+ assign _0558_ = _0556_ & _0557_;
+ assign _0559_ = ~ rs[34];
+ assign _0560_ = rs[41] & _0559_;
+ assign _0561_ = _0558_ | _0560_;
+ assign _0562_ = ~ rs[35];
+ assign _0563_ = rs[41] & _0562_;
+ assign _0564_ = _0561_ | _0563_;
+ assign _0565_ = rs[40] & rs[38];
+ assign _0566_ = _0565_ & rs[33];
+ assign _0567_ = ~ rs[37];
+ assign _0568_ = _0566_ & _0567_;
+ assign _0569_ = ~ rs[34];
+ assign _0570_ = rs[40] & _0569_;
+ assign _0571_ = _0568_ | _0570_;
+ assign _0572_ = ~ rs[35];
+ assign _0573_ = rs[40] & _0572_;
+ assign _0574_ = _0571_ | _0573_;
+ assign _0575_ = ~ rs[34];
+ assign _0576_ = rs[35] & _0575_;
+ assign _0577_ = _0576_ & rs[33];
+ assign _0578_ = rs[38] & rs[35];
+ assign _0579_ = _0578_ & rs[34];
+ assign _0580_ = _0579_ & rs[33];
+ assign _0581_ = _0577_ | _0580_;
+ assign _0582_ = ~ rs[37];
+ assign _0583_ = _0582_ & rs[35];
+ assign _0584_ = _0583_ & rs[34];
+ assign _0585_ = _0584_ & rs[33];
+ assign _0586_ = _0581_ | _0585_;
+ assign _0587_ = rs[41] & rs[37];
+ assign _0588_ = _0587_ & rs[35];
+ assign _0589_ = _0588_ & rs[34];
+ assign _0590_ = _0589_ & rs[33];
+ assign _0591_ = ~ rs[38];
+ assign _0592_ = _0590_ & _0591_;
+ assign _0593_ = ~ rs[33];
+ assign _0594_ = rs[38] & _0593_;
+ assign _0595_ = _0594_ & rs[35];
+ assign _0596_ = _0592_ | _0595_;
+ assign _0597_ = ~ rs[35];
+ assign _0598_ = rs[38] & _0597_;
+ assign _0599_ = _0596_ | _0598_;
+ assign _0600_ = rs[40] & rs[37];
+ assign _0601_ = _0600_ & rs[34];
+ assign _0602_ = _0601_ & rs[35];
+ assign _0603_ = _0602_ & rs[33];
+ assign _0604_ = ~ rs[38];
+ assign _0605_ = _0603_ & _0604_;
+ assign _0606_ = ~ rs[33];
+ assign _0607_ = rs[37] & _0606_;
+ assign _0608_ = _0607_ & rs[35];
+ assign _0609_ = _0605_ | _0608_;
+ assign _0610_ = ~ rs[35];
+ assign _0611_ = rs[37] & _0610_;
+ assign _0612_ = _0609_ | _0611_;
+ assign _0613_ = rs[37] & rs[35];
+ assign _0614_ = _0613_ & rs[34];
+ assign _0615_ = _0614_ & rs[33];
+ assign _0616_ = rs[38] & rs[35];
+ assign _0617_ = _0616_ & rs[34];
+ assign _0618_ = _0617_ & rs[33];
+ assign _0619_ = _0615_ | _0618_;
+ assign _0620_ = ~ rs[34];
+ assign _0621_ = rs[35] & _0620_;
+ assign _0622_ = ~ rs[33];
+ assign _0623_ = _0621_ & _0622_;
+ assign _0624_ = _0619_ | _0623_;
+ assign _0625_ = ~ rs[38];
+ assign _0626_ = rs[41] & _0625_;
+ assign _0627_ = ~ rs[37];
+ assign _0628_ = _0626_ & _0627_;
+ assign _0629_ = _0628_ & rs[34];
+ assign _0630_ = _0629_ & rs[35];
+ assign _0631_ = rs[38] & rs[35];
+ assign _0632_ = ~ rs[34];
+ assign _0633_ = _0631_ & _0632_;
+ assign _0634_ = _0633_ & rs[33];
+ assign _0635_ = _0630_ | _0634_;
+ assign _0636_ = rs[41] & rs[34];
+ assign _0637_ = ~ rs[33];
+ assign _0638_ = _0636_ & _0637_;
+ assign _0639_ = _0638_ & rs[35];
+ assign _0640_ = _0635_ | _0639_;
+ assign _0641_ = ~ rs[35];
+ assign _0642_ = rs[34] & _0641_;
+ assign _0643_ = _0640_ | _0642_;
+ assign _0644_ = ~ rs[38];
+ assign _0645_ = rs[40] & _0644_;
+ assign _0646_ = ~ rs[37];
+ assign _0647_ = _0645_ & _0646_;
+ assign _0648_ = _0647_ & rs[35];
+ assign _0649_ = _0648_ & rs[34];
+ assign _0650_ = rs[37] & rs[35];
+ assign _0651_ = ~ rs[34];
+ assign _0652_ = _0650_ & _0651_;
+ assign _0653_ = _0652_ & rs[33];
+ assign _0654_ = _0649_ | _0653_;
+ assign _0655_ = rs[40] & rs[35];
+ assign _0656_ = _0655_ & rs[34];
+ assign _0657_ = ~ rs[33];
+ assign _0658_ = _0656_ & _0657_;
+ assign _0659_ = _0654_ | _0658_;
+ assign _0660_ = ~ rs[35];
+ assign _0661_ = rs[33] & _0660_;
+ assign _0662_ = _0659_ | _0661_;
+ assign _0663_ = ~ rs[16];
+ assign _0664_ = _0663_ & rs[13];
+ assign _0665_ = _0664_ & rs[12];
+ assign _0666_ = rs[15] & rs[13];
+ assign _0667_ = _0666_ & rs[12];
+ assign _0668_ = _0667_ & rs[16];
+ assign _0669_ = _0665_ | _0668_;
+ assign _0670_ = rs[13] & rs[12];
+ assign _0671_ = ~ rs[11];
+ assign _0672_ = _0670_ & _0671_;
+ assign _0673_ = _0669_ | _0672_;
+ assign _0674_ = rs[19] & rs[16];
+ assign _0675_ = _0674_ & rs[11];
+ assign _0676_ = ~ rs[15];
+ assign _0677_ = _0675_ & _0676_;
+ assign _0678_ = ~ rs[12];
+ assign _0679_ = rs[19] & _0678_;
+ assign _0680_ = _0677_ | _0679_;
+ assign _0681_ = ~ rs[13];
+ assign _0682_ = rs[19] & _0681_;
+ assign _0683_ = _0680_ | _0682_;
+ assign _0684_ = rs[18] & rs[16];
+ assign _0685_ = _0684_ & rs[11];
+ assign _0686_ = ~ rs[15];
+ assign _0687_ = _0685_ & _0686_;
+ assign _0688_ = ~ rs[12];
+ assign _0689_ = rs[18] & _0688_;
+ assign _0690_ = _0687_ | _0689_;
+ assign _0691_ = ~ rs[13];
+ assign _0692_ = rs[18] & _0691_;
+ assign _0693_ = _0690_ | _0692_;
+ assign _0694_ = ~ rs[12];
+ assign _0695_ = rs[13] & _0694_;
+ assign _0696_ = _0695_ & rs[11];
+ assign _0697_ = rs[16] & rs[13];
+ assign _0698_ = _0697_ & rs[12];
+ assign _0699_ = _0698_ & rs[11];
+ assign _0700_ = _0696_ | _0699_;
+ assign _0701_ = ~ rs[15];
+ assign _0702_ = _0701_ & rs[13];
+ assign _0703_ = _0702_ & rs[12];
+ assign _0704_ = _0703_ & rs[11];
+ assign _0705_ = _0700_ | _0704_;
+ assign _0706_ = rs[19] & rs[15];
+ assign _0707_ = _0706_ & rs[13];
+ assign _0708_ = _0707_ & rs[12];
+ assign _0709_ = _0708_ & rs[11];
+ assign _0710_ = ~ rs[16];
+ assign _0711_ = _0709_ & _0710_;
+ assign _0712_ = ~ rs[11];
+ assign _0713_ = rs[16] & _0712_;
+ assign _0714_ = _0713_ & rs[13];
+ assign _0715_ = _0711_ | _0714_;
+ assign _0716_ = ~ rs[13];
+ assign _0717_ = rs[16] & _0716_;
+ assign _0718_ = _0715_ | _0717_;
+ assign _0719_ = rs[18] & rs[15];
+ assign _0720_ = _0719_ & rs[12];
+ assign _0721_ = _0720_ & rs[13];
+ assign _0722_ = _0721_ & rs[11];
+ assign _0723_ = ~ rs[16];
+ assign _0724_ = _0722_ & _0723_;
+ assign _0725_ = ~ rs[11];
+ assign _0726_ = rs[15] & _0725_;
+ assign _0727_ = _0726_ & rs[13];
+ assign _0728_ = _0724_ | _0727_;
+ assign _0729_ = ~ rs[13];
+ assign _0730_ = rs[15] & _0729_;
+ assign _0731_ = _0728_ | _0730_;
+ assign _0732_ = rs[15] & rs[13];
+ assign _0733_ = _0732_ & rs[12];
+ assign _0734_ = _0733_ & rs[11];
+ assign _0735_ = rs[16] & rs[13];
+ assign _0736_ = _0735_ & rs[12];
+ assign _0737_ = _0736_ & rs[11];
+ assign _0738_ = _0734_ | _0737_;
+ assign _0739_ = ~ rs[12];
+ assign _0740_ = rs[13] & _0739_;
+ assign _0741_ = ~ rs[11];
+ assign _0742_ = _0740_ & _0741_;
+ assign _0743_ = _0738_ | _0742_;
+ assign _0744_ = ~ rs[16];
+ assign _0745_ = rs[19] & _0744_;
+ assign _0746_ = ~ rs[15];
+ assign _0747_ = _0745_ & _0746_;
+ assign _0748_ = _0747_ & rs[12];
+ assign _0749_ = _0748_ & rs[13];
+ assign _0750_ = rs[16] & rs[13];
+ assign _0751_ = ~ rs[12];
+ assign _0752_ = _0750_ & _0751_;
+ assign _0753_ = _0752_ & rs[11];
+ assign _0754_ = _0749_ | _0753_;
+ assign _0755_ = rs[19] & rs[12];
+ assign _0756_ = ~ rs[11];
+ assign _0757_ = _0755_ & _0756_;
+ assign _0758_ = _0757_ & rs[13];
+ assign _0759_ = _0754_ | _0758_;
+ assign _0760_ = ~ rs[13];
+ assign _0761_ = rs[12] & _0760_;
+ assign _0762_ = _0759_ | _0761_;
+ assign _0763_ = ~ rs[16];
+ assign _0764_ = rs[18] & _0763_;
+ assign _0765_ = ~ rs[15];
+ assign _0766_ = _0764_ & _0765_;
+ assign _0767_ = _0766_ & rs[13];
+ assign _0768_ = _0767_ & rs[12];
+ assign _0769_ = rs[15] & rs[13];
+ assign _0770_ = ~ rs[12];
+ assign _0771_ = _0769_ & _0770_;
+ assign _0772_ = _0771_ & rs[11];
+ assign _0773_ = _0768_ | _0772_;
+ assign _0774_ = rs[18] & rs[13];
+ assign _0775_ = _0774_ & rs[12];
+ assign _0776_ = ~ rs[11];
+ assign _0777_ = _0775_ & _0776_;
+ assign _0778_ = _0773_ | _0777_;
+ assign _0779_ = ~ rs[13];
+ assign _0780_ = rs[11] & _0779_;
+ assign _0781_ = _0778_ | _0780_;
+ assign _0782_ = ~ rs[6];
+ assign _0783_ = _0782_ & rs[3];
+ assign _0784_ = _0783_ & rs[2];
+ assign _0785_ = rs[5] & rs[3];
+ assign _0786_ = _0785_ & rs[2];
+ assign _0787_ = _0786_ & rs[6];
+ assign _0788_ = _0784_ | _0787_;
+ assign _0789_ = rs[3] & rs[2];
+ assign _0790_ = ~ rs[1];
+ assign _0791_ = _0789_ & _0790_;
+ assign _0792_ = _0788_ | _0791_;
+ assign _0793_ = rs[9] & rs[6];
+ assign _0794_ = _0793_ & rs[1];
+ assign _0795_ = ~ rs[5];
+ assign _0796_ = _0794_ & _0795_;
+ assign _0797_ = ~ rs[2];
+ assign _0798_ = rs[9] & _0797_;
+ assign _0799_ = _0796_ | _0798_;
+ assign _0800_ = ~ rs[3];
+ assign _0801_ = rs[9] & _0800_;
+ assign _0802_ = _0799_ | _0801_;
+ assign _0803_ = rs[8] & rs[6];
+ assign _0804_ = _0803_ & rs[1];
+ assign _0805_ = ~ rs[5];
+ assign _0806_ = _0804_ & _0805_;
+ assign _0807_ = ~ rs[2];
+ assign _0808_ = rs[8] & _0807_;
+ assign _0809_ = _0806_ | _0808_;
+ assign _0810_ = ~ rs[3];
+ assign _0811_ = rs[8] & _0810_;
+ assign _0812_ = _0809_ | _0811_;
+ assign _0813_ = ~ rs[2];
+ assign _0814_ = rs[3] & _0813_;
+ assign _0815_ = _0814_ & rs[1];
+ assign _0816_ = rs[6] & rs[3];
+ assign _0817_ = _0816_ & rs[2];
+ assign _0818_ = _0817_ & rs[1];
+ assign _0819_ = _0815_ | _0818_;
+ assign _0820_ = ~ rs[5];
+ assign _0821_ = _0820_ & rs[3];
+ assign _0822_ = _0821_ & rs[2];
+ assign _0823_ = _0822_ & rs[1];
+ assign _0824_ = _0819_ | _0823_;
+ assign _0825_ = rs[9] & rs[5];
+ assign _0826_ = _0825_ & rs[3];
+ assign _0827_ = _0826_ & rs[2];
+ assign _0828_ = _0827_ & rs[1];
+ assign _0829_ = ~ rs[6];
+ assign _0830_ = _0828_ & _0829_;
+ assign _0831_ = ~ rs[1];
+ assign _0832_ = rs[6] & _0831_;
+ assign _0833_ = _0832_ & rs[3];
+ assign _0834_ = _0830_ | _0833_;
+ assign _0835_ = ~ rs[3];
+ assign _0836_ = rs[6] & _0835_;
+ assign _0837_ = _0834_ | _0836_;
+ assign _0838_ = rs[8] & rs[5];
+ assign _0839_ = _0838_ & rs[2];
+ assign _0840_ = _0839_ & rs[3];
+ assign _0841_ = _0840_ & rs[1];
+ assign _0842_ = ~ rs[6];
+ assign _0843_ = _0841_ & _0842_;
+ assign _0844_ = ~ rs[1];
+ assign _0845_ = rs[5] & _0844_;
+ assign _0846_ = _0845_ & rs[3];
+ assign _0847_ = _0843_ | _0846_;
+ assign _0848_ = ~ rs[3];
+ assign _0849_ = rs[5] & _0848_;
+ assign _0850_ = _0847_ | _0849_;
+ assign _0851_ = rs[5] & rs[3];
+ assign _0852_ = _0851_ & rs[2];
+ assign _0853_ = _0852_ & rs[1];
+ assign _0854_ = rs[6] & rs[3];
+ assign _0855_ = _0854_ & rs[2];
+ assign _0856_ = _0855_ & rs[1];
+ assign _0857_ = _0853_ | _0856_;
+ assign _0858_ = ~ rs[2];
+ assign _0859_ = rs[3] & _0858_;
+ assign _0860_ = ~ rs[1];
+ assign _0861_ = _0859_ & _0860_;
+ assign _0862_ = _0857_ | _0861_;
+ assign _0863_ = ~ rs[6];
+ assign _0864_ = rs[9] & _0863_;
+ assign _0865_ = ~ rs[5];
+ assign _0866_ = _0864_ & _0865_;
+ assign _0867_ = _0866_ & rs[2];
+ assign _0868_ = _0867_ & rs[3];
+ assign _0869_ = rs[6] & rs[3];
+ assign _0870_ = ~ rs[2];
+ assign _0871_ = _0869_ & _0870_;
+ assign _0872_ = _0871_ & rs[1];
+ assign _0873_ = _0868_ | _0872_;
+ assign _0874_ = rs[9] & rs[2];
+ assign _0875_ = ~ rs[1];
+ assign _0876_ = _0874_ & _0875_;
+ assign _0877_ = _0876_ & rs[3];
+ assign _0878_ = _0873_ | _0877_;
+ assign _0879_ = ~ rs[3];
+ assign _0880_ = rs[2] & _0879_;
+ assign _0881_ = _0878_ | _0880_;
+ assign _0882_ = ~ rs[6];
+ assign _0883_ = rs[8] & _0882_;
+ assign _0884_ = ~ rs[5];
+ assign _0885_ = _0883_ & _0884_;
+ assign _0886_ = _0885_ & rs[3];
+ assign _0887_ = _0886_ & rs[2];
+ assign _0888_ = rs[5] & rs[3];
+ assign _0889_ = ~ rs[2];
+ assign _0890_ = _0888_ & _0889_;
+ assign _0891_ = _0890_ & rs[1];
+ assign _0892_ = _0887_ | _0891_;
+ assign _0893_ = rs[8] & rs[3];
+ assign _0894_ = _0893_ & rs[2];
+ assign _0895_ = ~ rs[1];
+ assign _0896_ = _0894_ & _0895_;
+ assign _0897_ = _0892_ | _0896_;
+ assign _0898_ = ~ rs[3];
+ assign _0899_ = rs[1] & _0898_;
+ assign _0900_ = _0897_ | _0899_;
+ assign _0901_ = _0136_ ? { 12'h000, _0147_, _0158_, rs[52], _0175_, _0192_, rs[48], _0194_, _0201_, _0208_, rs[44], _0219_, _0230_, rs[40], _0247_, _0264_, rs[36], _0266_, _0273_, _0280_, rs[32], 12'h000, _0291_, _0302_, rs[20], _0319_, _0336_, rs[16], _0338_, _0345_, _0352_, rs[12], _0363_, _0374_, rs[8], _0391_, _0408_, rs[4], _0410_, _0417_, _0424_, rs[0] } : { 8'h00, _0435_, _0445_, _0455_, rs[49], _0467_, _0480_, _0493_, rs[46], _0505_, _0524_, _0543_, rs[42], _0554_, _0564_, _0574_, rs[39], _0586_, _0599_, _0612_, rs[36], _0624_, _0643_, _0662_, rs[32], 8'h00, _0673_, _0683_, _0693_, rs[17], _0705_, _0718_, _0731_, rs[14], _0743_, _0762_, _0781_, rs[10], _0792_, _0802_, _0812_, rs[7], _0824_, _0837_, _0850_, rs[4], _0862_, _0881_, _0900_, rs[0] };
+ assign _0902_ = op == 6'h3d;
+ assign _0903_ = datalen[0] & rs[7];
+ assign _0904_ = datalen[1] & rs[15];
+ assign _0905_ = _0903_ | _0904_;
+ assign _0906_ = datalen[2] & rs[31];
+ assign _0907_ = _0905_ | _0906_;
+ assign _0908_ = datalen[2] ? rs[31:16] : { _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_ };
+ assign _0909_ = datalen[2] | datalen[1];
+ assign _0910_ = _0909_ ? rs[15:8] : { _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_ };
+ function [7:0] \23747 ;
+ input [7:0] a;
+ input [47:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \23747 = b[7:0];
+ 6'b????1?:
+ \23747 = b[15:8];
+ 6'b???1??:
+ \23747 = b[23:16];
+ 6'b??1???:
+ \23747 = b[31:24];
+ 6'b?1????:
+ \23747 = b[39:32];
+ 6'b1?????:
+ \23747 = b[47:40];
+ default:
+ \23747 = a;
+ endcase
+ endfunction
+ assign _0911_ = \23747 (rs[7:0], { _0901_[7:0], _0100_, _0098_, _0096_, _0094_, _0092_, _0090_, _0088_, _0086_, _0119_, 7'h00, _0083_, 1'h0, _0069_, _0068_, _0110_[7:0] }, { _0902_, _0135_, _0134_, _0117_, _0116_, _0115_ });
+ function [7:0] \23754 ;
+ input [7:0] a;
+ input [47:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \23754 = b[7:0];
+ 6'b????1?:
+ \23754 = b[15:8];
+ 6'b???1??:
+ \23754 = b[23:16];
+ 6'b??1???:
+ \23754 = b[31:24];
+ 6'b?1????:
+ \23754 = b[39:32];
+ 6'b1?????:
+ \23754 = b[47:40];
+ default:
+ \23754 = a;
+ endcase
+ endfunction
+ assign _0912_ = \23754 (_0910_, { _0901_[15:8], 8'h00, _0121_, 12'h000, _0070_, _0110_[15:8] }, { _0902_, _0135_, _0134_, _0117_, _0116_, _0115_ });
+ function [15:0] \23761 ;
+ input [15:0] a;
+ input [95:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \23761 = b[15:0];
+ 6'b????1?:
+ \23761 = b[31:16];
+ 6'b???1??:
+ \23761 = b[47:32];
+ 6'b??1???:
+ \23761 = b[63:48];
+ 6'b?1????:
+ \23761 = b[79:64];
+ 6'b1?????:
+ \23761 = b[95:80];
+ default:
+ \23761 = a;
+ endcase
+ endfunction
+ assign _0913_ = \23761 (_0908_, { _0901_[31:16], 16'h0000, _0125_, _0123_, 20'h00000, _0072_, 4'h0, _0071_, _0110_[31:16] }, { _0902_, _0135_, _0134_, _0117_, _0116_, _0115_ });
+ function [31:0] \23768 ;
+ input [31:0] a;
+ input [191:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \23768 = b[31:0];
+ 6'b????1?:
+ \23768 = b[63:32];
+ 6'b???1??:
+ \23768 = b[95:64];
+ 6'b??1???:
+ \23768 = b[127:96];
+ 6'b?1????:
+ \23768 = b[159:128];
+ 6'b1?????:
+ \23768 = b[191:160];
+ default:
+ \23768 = a;
+ endcase
+ endfunction
+ assign _0914_ = \23768 ({ _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_, _0907_ }, { _0901_[63:32], 32'h00000000, _0133_, _0131_, _0129_, _0127_, 31'h00000000, _0084_, 4'h0, _0077_, 4'h0, _0076_, 4'h0, _0075_, 2'h0, _0074_, _0073_, _0110_[63:32] }, { _0902_, _0135_, _0134_, _0117_, _0116_, _0115_ });
+ assign result = { _0914_, _0913_, _0912_, _0911_ };
+endmodule
+
+module main_bram_64_10_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, addr, di, sel, re, we, \do );
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
+ wire _0_;
+ reg [63:0] _1_;
+ input [9:0] addr;
+ input clk;
+ input [63:0] di;
+ output [63:0] \do ;
+ wire [63:0] obuf;
+ input re;
+ input [7:0] sel;
+ wire [7:0] sel_qual;
+ input we;
+ assign sel_qual = we ? sel : 8'h00;
+ assign _0_ = re | we;
+ always @(posedge clk)
+ _1_ <= obuf;
+ RAM_512x64 memory_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .A(addr[8:0]),
+ .CLK(clk),
+ .Di(di),
+ .Do(obuf),
+ .EN(_0_),
+ .WE(sel_qual)
+ );
+ assign \do = _1_;
+endmodule
+
+module mc_32_64_8_2_6fe71f186fa9a2db88063728b6660dc449d010db(clk, rst, wb_cyc, wb_stb, wb_we, wb_addr, wb_wr_data, wb_sel, ib_data, ib_pty, wb_ack, wb_err, wb_stall, wb_rd_data, oib_clk, ob_data, ob_pty, err, \int );
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire _0007_;
+ wire _0008_;
+ wire _0009_;
+ wire _0010_;
+ wire _0011_;
+ wire _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire _0015_;
+ wire _0016_;
+ wire _0017_;
+ wire _0018_;
+ wire _0019_;
+ wire _0020_;
+ wire _0021_;
+ wire _0022_;
+ wire _0023_;
+ wire _0024_;
+ wire _0025_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0038_;
+ wire _0039_;
+ wire _0040_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0126_;
+ wire _0127_;
+ wire _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0908_;
+ wire _0909_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire _0913_;
+ wire _0914_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire _0938_;
+ wire _0939_;
+ wire _0940_;
+ wire _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire _0955_;
+ wire _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire _0960_;
+ wire _0961_;
+ wire _0962_;
+ wire _0963_;
+ wire _0964_;
+ wire _0965_;
+ wire _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire _0972_;
+ wire _0973_;
+ wire _0974_;
+ wire _0975_;
+ wire _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire _0997_;
+ wire _0998_;
+ wire _0999_;
+ wire _1000_;
+ wire _1001_;
+ wire _1002_;
+ wire _1003_;
+ wire _1004_;
+ wire _1005_;
+ wire _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1015_;
+ wire _1016_;
+ wire _1017_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire _1021_;
+ wire _1022_;
+ wire _1023_;
+ wire _1024_;
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+ wire _1026_;
+ wire _1027_;
+ wire _1028_;
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+ wire _1032_;
+ wire _1033_;
+ wire _1034_;
+ wire _1035_;
+ wire _1036_;
+ wire _1037_;
+ wire _1038_;
+ wire _1039_;
+ wire _1040_;
+ wire _1041_;
+ wire _1042_;
+ wire _1043_;
+ wire _1044_;
+ wire _1045_;
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+ wire _1057_;
+ wire _1058_;
+ wire _1059_;
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+ wire _1061_;
+ wire _1062_;
+ wire _1063_;
+ wire _1064_;
+ wire _1065_;
+ wire _1066_;
+ wire _1067_;
+ wire _1068_;
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+ wire _1070_;
+ wire _1071_;
+ wire _1072_;
+ wire _1073_;
+ wire _1074_;
+ wire _1075_;
+ wire _1076_;
+ wire _1077_;
+ wire _1078_;
+ wire _1079_;
+ wire _1080_;
+ wire _1081_;
+ wire _1082_;
+ wire _1083_;
+ wire _1084_;
+ wire _1085_;
+ wire _1086_;
+ wire _1087_;
+ wire _1088_;
+ wire _1089_;
+ wire _1090_;
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+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire _1095_;
+ wire _1096_;
+ wire _1097_;
+ wire _1098_;
+ wire _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire _1109_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire _1114_;
+ wire _1115_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1126_;
+ wire _1127_;
+ wire _1128_;
+ wire _1129_;
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+ wire _1131_;
+ wire _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1140_;
+ wire _1141_;
+ wire _1142_;
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+ wire _1163_;
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+ wire _1170_;
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+ wire _1177_;
+ wire _1178_;
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+ wire _1182_;
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+ wire _1184_;
+ wire _1185_;
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+ wire _1189_;
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+ wire _1192_;
+ wire _1193_;
+ wire _1194_;
+ wire _1195_;
+ wire _1196_;
+ wire _1197_;
+ wire _1198_;
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+ wire _1228_;
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+ wire _1517_;
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+ wire [63:0] _1520_;
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+ wire _1618_;
+ wire _1619_;
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+ wire _1817_;
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+ wire _1828_;
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+ wire _1857_;
+ wire _1858_;
+ wire _1859_;
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+ wire _1862_;
+ wire _1863_;
+ wire _1864_;
+ wire _1865_;
+ wire _1866_;
+ wire _1867_;
+ wire _1868_;
+ wire _1869_;
+ wire _1870_;
+ wire _1871_;
+ wire _1872_;
+ wire _1873_;
+ wire _1874_;
+ wire _1875_;
+ wire _1876_;
+ wire _1877_;
+ wire _1878_;
+ wire _1879_;
+ wire _1880_;
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+ wire _1887_;
+ wire _1888_;
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+ wire _1890_;
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+ wire _1904_;
+ wire _1905_;
+ wire _1906_;
+ wire _1907_;
+ wire _1908_;
+ wire _1909_;
+ wire _1910_;
+ wire _1911_;
+ wire _1912_;
+ wire _1913_;
+ wire _1914_;
+ wire _1915_;
+ wire _1916_;
+ wire _1917_;
+ wire _1918_;
+ wire _1919_;
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+ wire _1921_;
+ wire _1922_;
+ wire _1923_;
+ wire _1924_;
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+ wire _1926_;
+ wire _1927_;
+ wire _1928_;
+ wire _1929_;
+ wire _1930_;
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+ wire _1937_;
+ wire _1938_;
+ wire _1939_;
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+ wire _1941_;
+ wire _1942_;
+ wire _1943_;
+ wire _1944_;
+ wire _1945_;
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+ wire _1948_;
+ wire _1949_;
+ wire _1950_;
+ wire _1951_;
+ wire _1952_;
+ wire _1953_;
+ wire _1954_;
+ wire _1955_;
+ wire _1956_;
+ wire _1957_;
+ wire _1958_;
+ wire _1959_;
+ wire _1960_;
+ wire _1961_;
+ wire _1962_;
+ wire _1963_;
+ wire _1964_;
+ wire _1965_;
+ wire _1966_;
+ wire _1967_;
+ wire _1968_;
+ wire _1969_;
+ wire _1970_;
+ wire _1971_;
+ wire _1972_;
+ wire _1973_;
+ wire _1974_;
+ wire _1975_;
+ wire _1976_;
+ wire _1977_;
+ wire _1978_;
+ wire _1979_;
+ wire _1980_;
+ wire _1981_;
+ wire _1982_;
+ wire _1983_;
+ wire _1984_;
+ wire _1985_;
+ wire _1986_;
+ wire _1987_;
+ wire _1988_;
+ wire _1989_;
+ wire _1990_;
+ wire _1991_;
+ wire _1992_;
+ wire _1993_;
+ wire _1994_;
+ wire _1995_;
+ wire _1996_;
+ wire _1997_;
+ wire _1998_;
+ wire _1999_;
+ wire _2000_;
+ wire _2001_;
+ wire _2002_;
+ wire _2003_;
+ wire _2004_;
+ wire _2005_;
+ wire _2006_;
+ wire _2007_;
+ wire _2008_;
+ wire _2009_;
+ wire _2010_;
+ wire _2011_;
+ wire _2012_;
+ wire _2013_;
+ wire _2014_;
+ wire _2015_;
+ wire _2016_;
+ wire _2017_;
+ wire _2018_;
+ wire _2019_;
+ wire _2020_;
+ wire _2021_;
+ wire _2022_;
+ wire _2023_;
+ wire _2024_;
+ wire _2025_;
+ wire _2026_;
+ wire bad_header;
+ wire cache_inv;
+ input clk;
+ reg [63:0] config_q;
+ wire config_write;
+ output err;
+ wire good_header;
+ input [7:0] ib_data;
+ input ib_pty;
+ wire icapture_d;
+ reg icapture_q;
+ wire idata_clear;
+ wire [2:0] idata_cnt_d;
+ reg [2:0] idata_cnt_q;
+ wire [7:0] idata_d;
+ reg [7:0] idata_q;
+ wire idle_header;
+ output \int ;
+ wire int_req;
+ wire int_req_complete;
+ wire ipty_d;
+ reg ipty_q;
+ wire iseq_err;
+ wire iseq_idle;
+ reg [3:0] iseq_q;
+ wire ld_rd_data;
+ wire link_req_i;
+ wire link_rsp_i;
+ wire [63:0] local_rd_data;
+ wire oaddr_last;
+ wire [7:0] oaddr_mux;
+ wire ob_complete;
+ output [7:0] ob_data;
+ output ob_pty;
+ wire oclk_advance;
+ wire [15:0] oclk_cnt_d;
+ reg [15:0] oclk_cnt_q;
+ wire oclk_d;
+ wire oclk_last_d;
+ reg oclk_last_q;
+ wire oclk_match;
+ reg oclk_q;
+ wire [15:0] oclk_toggle;
+ wire odata_clear;
+ wire [2:0] odata_cnt_d;
+ reg [2:0] odata_cnt_q;
+ wire [7:0] odata_d;
+ wire odata_last;
+ wire odata_ld_addr;
+ wire odata_ld_data;
+ wire odata_ld_header;
+ wire odata_ld_sel;
+ wire [7:0] odata_mux;
+ reg [7:0] odata_q;
+ output oib_clk;
+ wire opty_d;
+ reg opty_q;
+ wire oseq_err;
+ wire oseq_hold;
+ reg [3:0] oseq_q;
+ wire pty_err;
+ wire rd8_rsp;
+ wire [63:0] rd_data_load;
+ wire rd_err;
+ wire rd_rsp_complete;
+ wire rd_rsp_data_done;
+ input rst;
+ wire save_header;
+ wire sync_ack;
+ output wb_ack;
+ input [31:0] wb_addr;
+ input wb_cyc;
+ output wb_err;
+ reg [106:0] wb_in_q;
+ wire wb_local;
+ wire wb_local_rd;
+ wire wb_local_wr;
+ reg [65:0] wb_out_q;
+ output [63:0] wb_rd_data;
+ wire wb_remote_rd;
+ wire wb_remote_wr;
+ wire wb_req;
+ input [7:0] wb_sel;
+ output wb_stall;
+ input wb_stb;
+ input wb_we;
+ input [63:0] wb_wr_data;
+ wire wbseq_err;
+ reg [3:0] wbseq_q;
+ wire wr8_rsp;
+ wire wr_err;
+ wire wr_rsp_complete;
+ assign _1402_ = oclk_cnt_q == oclk_toggle;
+ assign oclk_match = _1402_ ? 1'h1 : 1'h0;
+ assign _1403_ = 16'h0000 | 16'h0000;
+ assign _1404_ = ~ config_write;
+ assign _1405_ = config_q[0] & _1404_;
+ assign _1406_ = ~ oclk_match;
+ assign _1407_ = _1405_ & _1406_;
+ assign _1408_ = oclk_cnt_q + 16'h0001;
+ assign _1409_ = _1407_ ? _1408_ : 16'h0000;
+ assign oclk_cnt_d = _1403_ | _1409_;
+ assign oclk_advance = oclk_match & oclk_q;
+ assign _1410_ = oclk_q ^ oclk_match;
+ assign oclk_d = _1410_ & config_q[0];
+ assign oclk_last_d = oclk_q & config_q[0];
+ assign _1411_ = ~ oclk_last_q;
+ assign _1412_ = _1411_ & oclk_q;
+ assign _1413_ = _1412_ & config_q[0];
+ assign _1414_ = config_q[9] == 1'h0;
+ assign _1415_ = ~ oclk_q;
+ assign _1416_ = oclk_last_q & _1415_;
+ assign _1417_ = _1416_ & config_q[0];
+ function [0:0] \1068 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \1068 = b[0:0];
+ default:
+ \1068 = a;
+ endcase
+ endfunction
+ assign icapture_d = \1068 (_1417_, _1413_, _1414_);
+ assign _1418_ = oclk_advance & odata_ld_addr;
+ assign _1419_ = odata_cnt_q + 3'h1;
+ assign _1420_ = _1418_ ? _1419_ : 3'h0;
+ assign _1421_ = 3'h0 | _1420_;
+ assign _1422_ = oclk_advance & odata_ld_data;
+ assign _1423_ = odata_cnt_q + 3'h1;
+ assign _1424_ = _1422_ ? _1423_ : 3'h0;
+ assign _1425_ = _1421_ | _1424_;
+ assign _1426_ = ~ odata_clear;
+ assign _1427_ = odata_ld_addr | odata_ld_data;
+ assign _1428_ = oclk_advance & _1427_;
+ assign _1429_ = ~ _1428_;
+ assign _1430_ = _1426_ & _1429_;
+ assign _1431_ = _1430_ ? odata_cnt_q : 3'h0;
+ assign odata_cnt_d = _1425_ | _1431_;
+ assign _1432_ = odata_cnt_q == 3'h4;
+ assign oaddr_last = _1432_ ? 1'h1 : 1'h0;
+ assign _1433_ = odata_cnt_q == 3'h7;
+ assign odata_last = _1433_ ? 1'h1 : 1'h0;
+ assign _1434_ = odata_cnt_q == 3'h0;
+ assign _1435_ = odata_cnt_q == 3'h1;
+ assign _1436_ = odata_cnt_q == 3'h2;
+ function [7:0] \1166 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \1166 = b[7:0];
+ 3'b?1?:
+ \1166 = b[15:8];
+ 3'b1??:
+ \1166 = b[23:16];
+ default:
+ \1166 = a;
+ endcase
+ endfunction
+ assign oaddr_mux = \1166 (wb_in_q[31:24], wb_in_q[23:0], { _1436_, _1435_, _1434_ });
+ assign _1437_ = odata_cnt_q == 3'h0;
+ assign _1438_ = odata_cnt_q == 3'h1;
+ assign _1439_ = odata_cnt_q == 3'h2;
+ assign _1440_ = odata_cnt_q == 3'h3;
+ assign _1441_ = odata_cnt_q == 3'h4;
+ assign _1442_ = odata_cnt_q == 3'h5;
+ assign _1443_ = odata_cnt_q == 3'h6;
+ function [7:0] \1190 ;
+ input [7:0] a;
+ input [55:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \1190 = b[7:0];
+ 7'b?????1?:
+ \1190 = b[15:8];
+ 7'b????1??:
+ \1190 = b[23:16];
+ 7'b???1???:
+ \1190 = b[31:24];
+ 7'b??1????:
+ \1190 = b[39:32];
+ 7'b?1?????:
+ \1190 = b[47:40];
+ 7'b1??????:
+ \1190 = b[55:48];
+ default:
+ \1190 = a;
+ endcase
+ endfunction
+ assign odata_mux = \1190 (wb_in_q[95:88], wb_in_q[87:32], { _1443_, _1442_, _1441_, _1440_, _1439_, _1438_, _1437_ });
+ assign _1444_ = odata_clear & oclk_advance;
+ assign _1445_ = _1444_ ? config_q[47:40] : 8'h00;
+ assign _1446_ = odata_ld_header ? { _1531_, _1533_, _1534_, _1535_, 2'h0, _1536_, wb_remote_wr } : 8'h00;
+ assign _1447_ = _1445_ | _1446_;
+ assign _1448_ = odata_ld_addr & oclk_advance;
+ assign _1449_ = _1448_ ? oaddr_mux : 8'h00;
+ assign _1450_ = _1447_ | _1449_;
+ assign _1451_ = odata_ld_sel ? wb_in_q[103:96] : 8'h00;
+ assign _1452_ = _1450_ | _1451_;
+ assign _1453_ = odata_ld_data & oclk_advance;
+ assign _1454_ = _1453_ ? odata_mux : 8'h00;
+ assign _1455_ = _1452_ | _1454_;
+ assign _1456_ = ~ odata_ld_header;
+ assign _1457_ = ~ odata_ld_sel;
+ assign _1458_ = _1456_ & _1457_;
+ assign _1459_ = odata_ld_addr & oclk_advance;
+ assign _1460_ = ~ _1459_;
+ assign _1461_ = _1458_ & _1460_;
+ assign _1462_ = ~ odata_ld_sel;
+ assign _1463_ = _1461_ & _1462_;
+ assign _1464_ = odata_ld_data & oclk_advance;
+ assign _1465_ = ~ _1464_;
+ assign _1466_ = _1463_ & _1465_;
+ assign _1467_ = odata_clear & oclk_advance;
+ assign _1468_ = ~ _1467_;
+ assign _1469_ = _1466_ & _1468_;
+ assign _1470_ = _1469_ ? odata_q : 8'h00;
+ assign odata_d = _1455_ | _1470_;
+ assign _1471_ = odata_d[7] ^ odata_d[6];
+ assign _1472_ = _1471_ ^ odata_d[5];
+ assign _1473_ = _1472_ ^ odata_d[4];
+ assign _1474_ = _1473_ ^ odata_d[3];
+ assign _1475_ = _1474_ ^ odata_d[2];
+ assign _1476_ = _1475_ ^ odata_d[1];
+ assign _1477_ = _1476_ ^ odata_d[0];
+ assign opty_d = ~ _1477_;
+ assign _1478_ = icapture_d == 1'h1;
+ function [7:0] \1287 ;
+ input [7:0] a;
+ input [7:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \1287 = b[7:0];
+ default:
+ \1287 = a;
+ endcase
+ endfunction
+ assign idata_d = \1287 (idata_q, ib_data, _1478_);
+ assign _1479_ = icapture_d == 1'h1;
+ function [0:0] \1290 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \1290 = b[0:0];
+ default:
+ \1290 = a;
+ endcase
+ endfunction
+ assign ipty_d = \1290 (ipty_q, ib_pty, _1479_);
+ assign _1480_ = idata_q == config_q[47:40];
+ assign idle_header = _1480_ ? 1'h1 : 1'h0;
+ assign _1481_ = iseq_idle & icapture_q;
+ assign _1482_ = ~ idle_header;
+ assign _1483_ = _1481_ & _1482_;
+ assign _1484_ = ~ good_header;
+ assign bad_header = _1483_ & _1484_;
+ assign _1485_ = idata_q[0] ^ idata_q[1];
+ assign _1486_ = _1485_ ^ idata_q[2];
+ assign _1487_ = _1486_ ^ idata_q[3];
+ assign _1488_ = _1487_ ^ idata_q[4];
+ assign _1489_ = _1488_ ^ idata_q[5];
+ assign _1490_ = _1489_ ^ idata_q[6];
+ assign _1491_ = _1490_ ^ idata_q[7];
+ assign _1492_ = _1491_ ^ ipty_q;
+ assign _1493_ = ~ _1492_;
+ assign pty_err = icapture_q & _1493_;
+ assign _1494_ = icapture_q & ld_rd_data;
+ assign _1495_ = idata_cnt_q + 3'h1;
+ assign _1496_ = _1494_ ? _1495_ : 3'h0;
+ assign _1497_ = ~ idata_clear;
+ assign _1498_ = icapture_q & ld_rd_data;
+ assign _1499_ = ~ _1498_;
+ assign _1500_ = _1497_ & _1499_;
+ assign _1501_ = _1500_ ? idata_cnt_q : 3'h0;
+ assign idata_cnt_d = _1496_ | _1501_;
+ assign _1502_ = idata_cnt_q == 3'h7;
+ assign rd_rsp_data_done = _1502_ ? 1'h1 : 1'h0;
+ assign _1503_ = wb_in_q[7:4] == 4'h0;
+ function [63:0] \1375 ;
+ input [63:0] a;
+ input [63:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \1375 = b[63:0];
+ default:
+ \1375 = a;
+ endcase
+ endfunction
+ assign local_rd_data = \1375 (64'hffffffffffffffff, { config_q[0], config_q[7:1], config_q[8], config_q[9], config_q[10], config_q[13:11], config_q[15:14], config_q[31:16], config_q[39:32], config_q[47:40], config_q[55:48], config_q[63:56] }, _1503_);
+ assign _1504_ = idata_cnt_q == 3'h0;
+ assign _1505_ = idata_cnt_q == 3'h1;
+ assign _1506_ = idata_cnt_q == 3'h2;
+ assign _1507_ = idata_cnt_q == 3'h3;
+ assign _1508_ = idata_cnt_q == 3'h4;
+ assign _1509_ = idata_cnt_q == 3'h5;
+ assign _1510_ = idata_cnt_q == 3'h6;
+ function [63:0] \1419 ;
+ input [63:0] a;
+ input [447:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \1419 = b[63:0];
+ 7'b?????1?:
+ \1419 = b[127:64];
+ 7'b????1??:
+ \1419 = b[191:128];
+ 7'b???1???:
+ \1419 = b[255:192];
+ 7'b??1????:
+ \1419 = b[319:256];
+ 7'b?1?????:
+ \1419 = b[383:320];
+ 7'b1??????:
+ \1419 = b[447:384];
+ default:
+ \1419 = a;
+ endcase
+ endfunction
+ assign rd_data_load = \1419 ({ idata_q, wb_out_q[55:0] }, { wb_out_q[63:56], idata_q, wb_out_q[47:0], wb_out_q[63:48], idata_q, wb_out_q[39:0], wb_out_q[63:40], idata_q, wb_out_q[31:0], wb_out_q[63:32], idata_q, wb_out_q[23:0], wb_out_q[63:24], idata_q, wb_out_q[15:0], wb_out_q[63:16], idata_q, wb_out_q[7:0], wb_out_q[63:8], idata_q }, { _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_ });
+ assign _1511_ = wb_local_rd ? local_rd_data : 64'h0000000000000000;
+ assign _1512_ = wb_remote_rd & ld_rd_data;
+ assign _1513_ = _1512_ ? rd_data_load : 64'h0000000000000000;
+ assign _1514_ = _1511_ | _1513_;
+ assign _1515_ = ~ wb_local_rd;
+ assign _1516_ = wb_remote_rd & ld_rd_data;
+ assign _1517_ = ~ _1516_;
+ assign _1518_ = _1515_ & _1517_;
+ assign _1519_ = _1518_ ? wb_out_q[63:0] : 64'h0000000000000000;
+ assign _1520_ = _1514_ | _1519_;
+ assign _1521_ = rd8_rsp & iseq_idle;
+ assign _1522_ = _1521_ & icapture_q;
+ assign _1523_ = idata_q[4:3] == 2'h0;
+ assign _1524_ = _1523_ ? 1'h1 : 1'h0;
+ assign _1525_ = ~ _1524_;
+ assign rd_err = _1522_ & _1525_;
+ assign _1526_ = wr8_rsp & iseq_idle;
+ assign _1527_ = _1526_ & icapture_q;
+ assign _1528_ = idata_q[4:3] == 2'h0;
+ assign _1529_ = _1528_ ? 1'h1 : 1'h0;
+ assign _1530_ = ~ _1529_;
+ assign wr_err = _1527_ & _1530_;
+ assign _1531_ = 1'h0 | 1'h0;
+ assign _1532_ = 1'h0 | 1'h0;
+ assign _1533_ = _1532_ | 1'h0;
+ assign _1534_ = 1'h0 | 1'h0;
+ assign _1535_ = 1'h0 | 1'h0;
+ assign _1536_ = wb_remote_rd | wb_remote_wr;
+ assign _1537_ = ~ idata_q[6];
+ assign _1538_ = idata_q[7] & _1537_;
+ assign _1539_ = ~ idata_q[5];
+ assign _1540_ = _1538_ & _1539_;
+ assign _1541_ = ~ idata_q[4];
+ assign _1542_ = _1540_ & _1541_;
+ assign _1543_ = _1542_ & idata_q[1];
+ assign _1544_ = ~ idata_q[0];
+ assign _1545_ = _1543_ & _1544_;
+ assign rd8_rsp = _1545_ & wb_remote_rd;
+ assign _1546_ = ~ idata_q[6];
+ assign _1547_ = idata_q[7] & _1546_;
+ assign _1548_ = ~ idata_q[5];
+ assign _1549_ = _1547_ & _1548_;
+ assign _1550_ = ~ idata_q[4];
+ assign _1551_ = _1549_ & _1550_;
+ assign _1552_ = _1551_ & idata_q[1];
+ assign _1553_ = _1552_ & idata_q[0];
+ assign wr8_rsp = _1553_ & wb_remote_wr;
+ assign _1554_ = idata_q[7] & idata_q[6];
+ assign _1555_ = ~ idata_q[5];
+ assign _1556_ = _1554_ & _1555_;
+ assign _1557_ = _1556_ & idata_q[4];
+ assign _1558_ = ~ idata_q[3];
+ assign int_req = _1557_ & _1558_;
+ assign _1559_ = idata_q[7] & idata_q[6];
+ assign _1560_ = ~ idata_q[5];
+ assign _1561_ = _1559_ & _1560_;
+ assign _1562_ = ~ idata_q[4];
+ assign _1563_ = _1561_ & _1562_;
+ assign _1564_ = ~ idata_q[3];
+ assign sync_ack = _1563_ & _1564_;
+ assign _1565_ = idata_q[7] & idata_q[6];
+ assign _1566_ = ~ idata_q[5];
+ assign _1567_ = _1565_ & _1566_;
+ assign _1568_ = ~ idata_q[4];
+ assign _1569_ = _1567_ & _1568_;
+ assign cache_inv = _1569_ & idata_q[3];
+ assign _1570_ = idata_q[7] & idata_q[6];
+ assign _1571_ = _1570_ & idata_q[5];
+ assign _1572_ = _1571_ & idata_q[4];
+ assign _1573_ = ~ idata_q[3];
+ assign link_req_i = _1572_ & _1573_;
+ assign _1574_ = idata_q[7] & idata_q[6];
+ assign _1575_ = _1574_ & idata_q[5];
+ assign _1576_ = _1575_ & idata_q[4];
+ assign link_rsp_i = _1576_ & idata_q[3];
+ assign _1577_ = ~ idata_q[6];
+ assign _1578_ = idata_q[7] & _1577_;
+ assign _1579_ = ~ idata_q[5];
+ assign _1580_ = _1578_ & _1579_;
+ assign _1581_ = ~ idata_q[4];
+ assign _1582_ = _1580_ & _1581_;
+ assign _1583_ = _1582_ & idata_q[1];
+ assign _1584_ = ~ idata_q[0];
+ assign _1585_ = _1583_ & _1584_;
+ assign _1586_ = _1585_ & wb_remote_rd;
+ assign _1587_ = ~ idata_q[6];
+ assign _1588_ = idata_q[7] & _1587_;
+ assign _1589_ = ~ idata_q[5];
+ assign _1590_ = _1588_ & _1589_;
+ assign _1591_ = ~ idata_q[4];
+ assign _1592_ = _1590_ & _1591_;
+ assign _1593_ = _1592_ & idata_q[1];
+ assign _1594_ = _1593_ & idata_q[0];
+ assign _1595_ = _1594_ & wb_remote_wr;
+ assign _1596_ = _1586_ | _1595_;
+ assign _1597_ = idata_q[7] & idata_q[6];
+ assign _1598_ = ~ idata_q[5];
+ assign _1599_ = _1597_ & _1598_;
+ assign _1600_ = ~ idata_q[4];
+ assign _1601_ = _1599_ & _1600_;
+ assign _1602_ = ~ idata_q[3];
+ assign _1603_ = _1601_ & _1602_;
+ assign _1604_ = _1596_ | _1603_;
+ assign _1605_ = idata_q[7] & idata_q[6];
+ assign _1606_ = ~ idata_q[5];
+ assign _1607_ = _1605_ & _1606_;
+ assign _1608_ = ~ idata_q[4];
+ assign _1609_ = _1607_ & _1608_;
+ assign _1610_ = _1609_ & idata_q[3];
+ assign _1611_ = _1604_ | _1610_;
+ assign _1612_ = idata_q[7] & idata_q[6];
+ assign _1613_ = ~ idata_q[5];
+ assign _1614_ = _1612_ & _1613_;
+ assign _1615_ = _1614_ & idata_q[4];
+ assign _1616_ = ~ idata_q[3];
+ assign _1617_ = _1615_ & _1616_;
+ assign _1618_ = _1611_ | _1617_;
+ assign _1619_ = idata_q[7] & idata_q[6];
+ assign _1620_ = _1619_ & idata_q[5];
+ assign _1621_ = _1620_ & idata_q[4];
+ assign _1622_ = ~ idata_q[3];
+ assign _1623_ = _1621_ & _1622_;
+ assign _1624_ = _1618_ | _1623_;
+ assign _1625_ = idata_q[7] & idata_q[6];
+ assign _1626_ = _1625_ & idata_q[5];
+ assign _1627_ = _1626_ & idata_q[4];
+ assign _1628_ = _1627_ & idata_q[3];
+ assign good_header = _1624_ | _1628_;
+ assign _1629_ = wbseq_q[3] & wbseq_q[2];
+ assign _1630_ = _1629_ & wbseq_q[1];
+ assign _1631_ = _1630_ & wbseq_q[0];
+ assign _1632_ = ~ wb_req;
+ assign _1633_ = _1631_ & _1632_;
+ assign _1634_ = wbseq_q[3] & wbseq_q[2];
+ assign _1635_ = _1634_ & wbseq_q[1];
+ assign _1636_ = _1635_ & wbseq_q[0];
+ assign _1637_ = _1636_ & wb_req;
+ assign _1638_ = _1637_ & wb_we;
+ assign _1639_ = ~ wb_local;
+ assign _1640_ = _1638_ & _1639_;
+ assign _1641_ = _1633_ | _1640_;
+ assign _1642_ = ~ wbseq_q[3];
+ assign _1643_ = ~ wbseq_q[2];
+ assign _1644_ = _1642_ & _1643_;
+ assign _1645_ = ~ wbseq_q[1];
+ assign _1646_ = _1644_ & _1645_;
+ assign _1647_ = _1646_ & wbseq_q[0];
+ assign _1648_ = _1641_ | _1647_;
+ assign _1649_ = ~ wbseq_q[3];
+ assign _1650_ = ~ wbseq_q[2];
+ assign _1651_ = _1649_ & _1650_;
+ assign _1652_ = _1651_ & wbseq_q[1];
+ assign _1653_ = ~ wbseq_q[0];
+ assign _1654_ = _1652_ & _1653_;
+ assign _1655_ = _1648_ | _1654_;
+ assign _1656_ = ~ wbseq_q[3];
+ assign _1657_ = _1656_ & wbseq_q[2];
+ assign _1658_ = _1657_ & wbseq_q[1];
+ assign _1659_ = ~ wbseq_q[0];
+ assign _1660_ = _1658_ & _1659_;
+ assign _1661_ = ~ rd_rsp_complete;
+ assign _1662_ = _1660_ & _1661_;
+ assign _1663_ = _1655_ | _1662_;
+ assign _1664_ = ~ wbseq_q[2];
+ assign _1665_ = wbseq_q[3] & _1664_;
+ assign _1666_ = ~ wbseq_q[1];
+ assign _1667_ = _1665_ & _1666_;
+ assign _1668_ = ~ wbseq_q[0];
+ assign _1669_ = _1667_ & _1668_;
+ assign _1670_ = ~ ob_complete;
+ assign _1671_ = _1669_ & _1670_;
+ assign _1672_ = _1663_ | _1671_;
+ assign _1673_ = ~ wbseq_q[2];
+ assign _1674_ = wbseq_q[3] & _1673_;
+ assign _1675_ = ~ wbseq_q[1];
+ assign _1676_ = _1674_ & _1675_;
+ assign _1677_ = ~ wbseq_q[0];
+ assign _1678_ = _1676_ & _1677_;
+ assign _1679_ = _1678_ & ob_complete;
+ assign _1680_ = _1672_ | _1679_;
+ assign _1681_ = ~ wbseq_q[2];
+ assign _1682_ = wbseq_q[3] & _1681_;
+ assign _1683_ = ~ wbseq_q[1];
+ assign _1684_ = _1682_ & _1683_;
+ assign _1685_ = _1684_ & wbseq_q[0];
+ assign _1686_ = ~ wr_rsp_complete;
+ assign _1687_ = _1685_ & _1686_;
+ assign _1688_ = _1680_ | _1687_;
+ assign _1689_ = ~ wbseq_q[2];
+ assign _1690_ = wbseq_q[3] & _1689_;
+ assign _1691_ = ~ wbseq_q[1];
+ assign _1692_ = _1690_ & _1691_;
+ assign _1693_ = _1692_ & wbseq_q[0];
+ assign _1694_ = _1693_ & wr_rsp_complete;
+ assign _1695_ = _1688_ | _1694_;
+ assign _1696_ = ~ wbseq_q[2];
+ assign _1697_ = wbseq_q[3] & _1696_;
+ assign _1698_ = _1697_ & wbseq_q[1];
+ assign _1699_ = ~ wbseq_q[0];
+ assign _1700_ = _1698_ & _1699_;
+ assign _1701_ = _1695_ | _1700_;
+ assign _1702_ = wbseq_q[3] & wbseq_q[2];
+ assign _1703_ = _1702_ & wbseq_q[1];
+ assign _1704_ = ~ wbseq_q[0];
+ assign _1705_ = _1703_ & _1704_;
+ assign _1706_ = _1701_ | _1705_;
+ assign _1707_ = ~ wbseq_q[2];
+ assign _1708_ = wbseq_q[3] & _1707_;
+ assign _1709_ = _1708_ & wbseq_q[1];
+ assign _1710_ = _1709_ & wbseq_q[0];
+ assign _1711_ = _1706_ | _1710_;
+ assign _1712_ = wbseq_q[3] & wbseq_q[2];
+ assign _1713_ = ~ wbseq_q[1];
+ assign _1714_ = _1712_ & _1713_;
+ assign _1715_ = ~ wbseq_q[0];
+ assign _1716_ = _1714_ & _1715_;
+ assign _1717_ = _1711_ | _1716_;
+ assign _1718_ = wbseq_q[3] & wbseq_q[2];
+ assign _1719_ = ~ wbseq_q[1];
+ assign _1720_ = _1718_ & _1719_;
+ assign _1721_ = _1720_ & wbseq_q[0];
+ assign _1722_ = _1717_ | _1721_;
+ assign _1723_ = wbseq_q[3] & wbseq_q[2];
+ assign _1724_ = _1723_ & wbseq_q[1];
+ assign _1725_ = _1724_ & wbseq_q[0];
+ assign _1726_ = ~ wb_req;
+ assign _1727_ = _1725_ & _1726_;
+ assign _1728_ = wbseq_q[3] & wbseq_q[2];
+ assign _1729_ = _1728_ & wbseq_q[1];
+ assign _1730_ = _1729_ & wbseq_q[0];
+ assign _1731_ = _1730_ & wb_req;
+ assign _1732_ = ~ wb_we;
+ assign _1733_ = _1731_ & _1732_;
+ assign _1734_ = ~ wb_local;
+ assign _1735_ = _1733_ & _1734_;
+ assign _1736_ = _1727_ | _1735_;
+ assign _1737_ = ~ wbseq_q[3];
+ assign _1738_ = ~ wbseq_q[2];
+ assign _1739_ = _1737_ & _1738_;
+ assign _1740_ = ~ wbseq_q[1];
+ assign _1741_ = _1739_ & _1740_;
+ assign _1742_ = _1741_ & wbseq_q[0];
+ assign _1743_ = _1736_ | _1742_;
+ assign _1744_ = ~ wbseq_q[3];
+ assign _1745_ = ~ wbseq_q[2];
+ assign _1746_ = _1744_ & _1745_;
+ assign _1747_ = _1746_ & wbseq_q[1];
+ assign _1748_ = ~ wbseq_q[0];
+ assign _1749_ = _1747_ & _1748_;
+ assign _1750_ = _1743_ | _1749_;
+ assign _1751_ = ~ wbseq_q[3];
+ assign _1752_ = _1751_ & wbseq_q[2];
+ assign _1753_ = ~ wbseq_q[1];
+ assign _1754_ = _1752_ & _1753_;
+ assign _1755_ = ~ wbseq_q[0];
+ assign _1756_ = _1754_ & _1755_;
+ assign _1757_ = ~ ob_complete;
+ assign _1758_ = _1756_ & _1757_;
+ assign _1759_ = _1750_ | _1758_;
+ assign _1760_ = ~ wbseq_q[3];
+ assign _1761_ = _1760_ & wbseq_q[2];
+ assign _1762_ = ~ wbseq_q[1];
+ assign _1763_ = _1761_ & _1762_;
+ assign _1764_ = ~ wbseq_q[0];
+ assign _1765_ = _1763_ & _1764_;
+ assign _1766_ = _1765_ & ob_complete;
+ assign _1767_ = _1759_ | _1766_;
+ assign _1768_ = ~ wbseq_q[3];
+ assign _1769_ = _1768_ & wbseq_q[2];
+ assign _1770_ = ~ wbseq_q[1];
+ assign _1771_ = _1769_ & _1770_;
+ assign _1772_ = _1771_ & wbseq_q[0];
+ assign _1773_ = ~ rd_rsp_complete;
+ assign _1774_ = _1772_ & _1773_;
+ assign _1775_ = _1767_ | _1774_;
+ assign _1776_ = ~ wbseq_q[3];
+ assign _1777_ = _1776_ & wbseq_q[2];
+ assign _1778_ = ~ wbseq_q[1];
+ assign _1779_ = _1777_ & _1778_;
+ assign _1780_ = _1779_ & wbseq_q[0];
+ assign _1781_ = _1780_ & rd_rsp_complete;
+ assign _1782_ = _1775_ | _1781_;
+ assign _1783_ = ~ wbseq_q[3];
+ assign _1784_ = _1783_ & wbseq_q[2];
+ assign _1785_ = _1784_ & wbseq_q[1];
+ assign _1786_ = ~ wbseq_q[0];
+ assign _1787_ = _1785_ & _1786_;
+ assign _1788_ = ~ rd_rsp_complete;
+ assign _1789_ = _1787_ & _1788_;
+ assign _1790_ = _1782_ | _1789_;
+ assign _1791_ = ~ wbseq_q[2];
+ assign _1792_ = wbseq_q[3] & _1791_;
+ assign _1793_ = _1792_ & wbseq_q[1];
+ assign _1794_ = ~ wbseq_q[0];
+ assign _1795_ = _1793_ & _1794_;
+ assign _1796_ = _1790_ | _1795_;
+ assign _1797_ = wbseq_q[3] & wbseq_q[2];
+ assign _1798_ = _1797_ & wbseq_q[1];
+ assign _1799_ = ~ wbseq_q[0];
+ assign _1800_ = _1798_ & _1799_;
+ assign _1801_ = _1796_ | _1800_;
+ assign _1802_ = ~ wbseq_q[3];
+ assign _1803_ = _1802_ & wbseq_q[2];
+ assign _1804_ = _1803_ & wbseq_q[1];
+ assign _1805_ = _1804_ & wbseq_q[0];
+ assign _1806_ = _1801_ | _1805_;
+ assign _1807_ = wbseq_q[3] & wbseq_q[2];
+ assign _1808_ = ~ wbseq_q[1];
+ assign _1809_ = _1807_ & _1808_;
+ assign _1810_ = ~ wbseq_q[0];
+ assign _1811_ = _1809_ & _1810_;
+ assign _1812_ = _1806_ | _1811_;
+ assign _1813_ = wbseq_q[3] & wbseq_q[2];
+ assign _1814_ = ~ wbseq_q[1];
+ assign _1815_ = _1813_ & _1814_;
+ assign _1816_ = _1815_ & wbseq_q[0];
+ assign _1817_ = _1812_ | _1816_;
+ assign _1818_ = wbseq_q[3] & wbseq_q[2];
+ assign _1819_ = _1818_ & wbseq_q[1];
+ assign _1820_ = _1819_ & wbseq_q[0];
+ assign _1821_ = ~ wb_req;
+ assign _1822_ = _1820_ & _1821_;
+ assign _1823_ = wbseq_q[3] & wbseq_q[2];
+ assign _1824_ = _1823_ & wbseq_q[1];
+ assign _1825_ = _1824_ & wbseq_q[0];
+ assign _1826_ = _1825_ & wb_req;
+ assign _1827_ = _1826_ & wb_we;
+ assign _1828_ = _1827_ & wb_local;
+ assign _1829_ = _1822_ | _1828_;
+ assign _1830_ = ~ wbseq_q[3];
+ assign _1831_ = ~ wbseq_q[2];
+ assign _1832_ = _1830_ & _1831_;
+ assign _1833_ = ~ wbseq_q[1];
+ assign _1834_ = _1832_ & _1833_;
+ assign _1835_ = _1834_ & wbseq_q[0];
+ assign _1836_ = _1829_ | _1835_;
+ assign _1837_ = ~ wbseq_q[3];
+ assign _1838_ = ~ wbseq_q[2];
+ assign _1839_ = _1837_ & _1838_;
+ assign _1840_ = _1839_ & wbseq_q[1];
+ assign _1841_ = ~ wbseq_q[0];
+ assign _1842_ = _1840_ & _1841_;
+ assign _1843_ = _1836_ | _1842_;
+ assign _1844_ = ~ wbseq_q[3];
+ assign _1845_ = _1844_ & wbseq_q[2];
+ assign _1846_ = ~ wbseq_q[1];
+ assign _1847_ = _1845_ & _1846_;
+ assign _1848_ = _1847_ & wbseq_q[0];
+ assign _1849_ = _1848_ & rd_rsp_complete;
+ assign _1850_ = _1843_ | _1849_;
+ assign _1851_ = ~ wbseq_q[3];
+ assign _1852_ = _1851_ & wbseq_q[2];
+ assign _1853_ = _1852_ & wbseq_q[1];
+ assign _1854_ = ~ wbseq_q[0];
+ assign _1855_ = _1853_ & _1854_;
+ assign _1856_ = ~ rd_rsp_complete;
+ assign _1857_ = _1855_ & _1856_;
+ assign _1858_ = _1850_ | _1857_;
+ assign _1859_ = ~ wbseq_q[2];
+ assign _1860_ = wbseq_q[3] & _1859_;
+ assign _1861_ = ~ wbseq_q[1];
+ assign _1862_ = _1860_ & _1861_;
+ assign _1863_ = _1862_ & wbseq_q[0];
+ assign _1864_ = _1863_ & wr_rsp_complete;
+ assign _1865_ = _1858_ | _1864_;
+ assign _1866_ = ~ wbseq_q[2];
+ assign _1867_ = wbseq_q[3] & _1866_;
+ assign _1868_ = _1867_ & wbseq_q[1];
+ assign _1869_ = ~ wbseq_q[0];
+ assign _1870_ = _1868_ & _1869_;
+ assign _1871_ = _1865_ | _1870_;
+ assign _1872_ = wbseq_q[3] & wbseq_q[2];
+ assign _1873_ = _1872_ & wbseq_q[1];
+ assign _1874_ = ~ wbseq_q[0];
+ assign _1875_ = _1873_ & _1874_;
+ assign _1876_ = _1871_ | _1875_;
+ assign _1877_ = ~ wbseq_q[3];
+ assign _1878_ = ~ wbseq_q[2];
+ assign _1879_ = _1877_ & _1878_;
+ assign _1880_ = _1879_ & wbseq_q[1];
+ assign _1881_ = _1880_ & wbseq_q[0];
+ assign _1882_ = _1876_ | _1881_;
+ assign _1883_ = ~ wbseq_q[3];
+ assign _1884_ = _1883_ & wbseq_q[2];
+ assign _1885_ = _1884_ & wbseq_q[1];
+ assign _1886_ = _1885_ & wbseq_q[0];
+ assign _1887_ = _1882_ | _1886_;
+ assign _1888_ = ~ wbseq_q[2];
+ assign _1889_ = wbseq_q[3] & _1888_;
+ assign _1890_ = _1889_ & wbseq_q[1];
+ assign _1891_ = _1890_ & wbseq_q[0];
+ assign _1892_ = _1887_ | _1891_;
+ assign _1893_ = wbseq_q[3] & wbseq_q[2];
+ assign _1894_ = _1893_ & wbseq_q[1];
+ assign _1895_ = _1894_ & wbseq_q[0];
+ assign _1896_ = ~ wb_req;
+ assign _1897_ = _1895_ & _1896_;
+ assign _1898_ = wbseq_q[3] & wbseq_q[2];
+ assign _1899_ = _1898_ & wbseq_q[1];
+ assign _1900_ = _1899_ & wbseq_q[0];
+ assign _1901_ = _1900_ & wb_req;
+ assign _1902_ = ~ wb_we;
+ assign _1903_ = _1901_ & _1902_;
+ assign _1904_ = _1903_ & wb_local;
+ assign _1905_ = _1897_ | _1904_;
+ assign _1906_ = ~ wbseq_q[3];
+ assign _1907_ = _1906_ & wbseq_q[2];
+ assign _1908_ = ~ wbseq_q[1];
+ assign _1909_ = _1907_ & _1908_;
+ assign _1910_ = ~ wbseq_q[0];
+ assign _1911_ = _1909_ & _1910_;
+ assign _1912_ = _1911_ & ob_complete;
+ assign _1913_ = _1905_ | _1912_;
+ assign _1914_ = ~ wbseq_q[3];
+ assign _1915_ = _1914_ & wbseq_q[2];
+ assign _1916_ = ~ wbseq_q[1];
+ assign _1917_ = _1915_ & _1916_;
+ assign _1918_ = _1917_ & wbseq_q[0];
+ assign _1919_ = ~ rd_rsp_complete;
+ assign _1920_ = _1918_ & _1919_;
+ assign _1921_ = _1913_ | _1920_;
+ assign _1922_ = ~ wbseq_q[2];
+ assign _1923_ = wbseq_q[3] & _1922_;
+ assign _1924_ = ~ wbseq_q[1];
+ assign _1925_ = _1923_ & _1924_;
+ assign _1926_ = ~ wbseq_q[0];
+ assign _1927_ = _1925_ & _1926_;
+ assign _1928_ = _1927_ & ob_complete;
+ assign _1929_ = _1921_ | _1928_;
+ assign _1930_ = ~ wbseq_q[2];
+ assign _1931_ = wbseq_q[3] & _1930_;
+ assign _1932_ = ~ wbseq_q[1];
+ assign _1933_ = _1931_ & _1932_;
+ assign _1934_ = _1933_ & wbseq_q[0];
+ assign _1935_ = ~ wr_rsp_complete;
+ assign _1936_ = _1934_ & _1935_;
+ assign _1937_ = _1929_ | _1936_;
+ assign _1938_ = wbseq_q[3] & wbseq_q[2];
+ assign _1939_ = _1938_ & wbseq_q[1];
+ assign _1940_ = ~ wbseq_q[0];
+ assign _1941_ = _1939_ & _1940_;
+ assign _1942_ = _1937_ | _1941_;
+ assign _1943_ = ~ wbseq_q[3];
+ assign _1944_ = ~ wbseq_q[2];
+ assign _1945_ = _1943_ & _1944_;
+ assign _1946_ = _1945_ & wbseq_q[1];
+ assign _1947_ = _1946_ & wbseq_q[0];
+ assign _1948_ = _1942_ | _1947_;
+ assign _1949_ = ~ wbseq_q[3];
+ assign _1950_ = _1949_ & wbseq_q[2];
+ assign _1951_ = _1950_ & wbseq_q[1];
+ assign _1952_ = _1951_ & wbseq_q[0];
+ assign _1953_ = _1948_ | _1952_;
+ assign _1954_ = ~ wbseq_q[2];
+ assign _1955_ = wbseq_q[3] & _1954_;
+ assign _1956_ = _1955_ & wbseq_q[1];
+ assign _1957_ = _1956_ & wbseq_q[0];
+ assign _1958_ = _1953_ | _1957_;
+ assign _1959_ = wbseq_q[3] & wbseq_q[2];
+ assign _1960_ = ~ wbseq_q[1];
+ assign _1961_ = _1959_ & _1960_;
+ assign _1962_ = _1961_ & wbseq_q[0];
+ assign _1963_ = _1958_ | _1962_;
+ assign _1964_ = wbseq_q[3] & wbseq_q[2];
+ assign _1965_ = _1964_ & wbseq_q[1];
+ assign _1966_ = _1965_ & wbseq_q[0];
+ assign _1967_ = _1966_ & wb_req;
+ assign _1968_ = ~ wb_we;
+ assign _1969_ = _1967_ & _1968_;
+ assign wb_local_rd = _1969_ & wb_local;
+ assign _1970_ = wbseq_q[3] & wbseq_q[2];
+ assign _1971_ = _1970_ & wbseq_q[1];
+ assign _1972_ = _1971_ & wbseq_q[0];
+ assign _1973_ = _1972_ & wb_req;
+ assign _1974_ = _1973_ & wb_we;
+ assign wb_local_wr = _1974_ & wb_local;
+ assign _1975_ = wbseq_q[3] & wbseq_q[2];
+ assign _1976_ = _1975_ & wbseq_q[1];
+ assign _1977_ = _1976_ & wbseq_q[0];
+ assign _1978_ = _1977_ & wb_req;
+ assign _1979_ = ~ wb_we;
+ assign _1980_ = _1978_ & _1979_;
+ assign _1981_ = ~ wb_local;
+ assign _1982_ = _1980_ & _1981_;
+ assign _1983_ = ~ wbseq_q[3];
+ assign _1984_ = _1983_ & wbseq_q[2];
+ assign _1985_ = ~ wbseq_q[1];
+ assign _1986_ = _1984_ & _1985_;
+ assign _1987_ = ~ wbseq_q[0];
+ assign _1988_ = _1986_ & _1987_;
+ assign _1989_ = _1982_ | _1988_;
+ assign _1990_ = ~ wbseq_q[3];
+ assign _1991_ = _1990_ & wbseq_q[2];
+ assign _1992_ = ~ wbseq_q[1];
+ assign _1993_ = _1991_ & _1992_;
+ assign _1994_ = _1993_ & wbseq_q[0];
+ assign _1995_ = _1989_ | _1994_;
+ assign _1996_ = ~ wbseq_q[3];
+ assign _1997_ = _1996_ & wbseq_q[2];
+ assign _1998_ = _1997_ & wbseq_q[1];
+ assign _1999_ = ~ wbseq_q[0];
+ assign _2000_ = _1998_ & _1999_;
+ assign _2001_ = ~ rd_rsp_complete;
+ assign _2002_ = _2000_ & _2001_;
+ assign wb_remote_rd = _1995_ | _2002_;
+ assign _2003_ = wbseq_q[3] & wbseq_q[2];
+ assign _2004_ = _2003_ & wbseq_q[1];
+ assign _2005_ = _2004_ & wbseq_q[0];
+ assign _2006_ = _2005_ & wb_req;
+ assign _2007_ = _2006_ & wb_we;
+ assign _2008_ = ~ wb_local;
+ assign _2009_ = _2007_ & _2008_;
+ assign _2010_ = ~ wbseq_q[2];
+ assign _2011_ = wbseq_q[3] & _2010_;
+ assign _2012_ = ~ wbseq_q[1];
+ assign _2013_ = _2011_ & _2012_;
+ assign _2014_ = ~ wbseq_q[0];
+ assign _2015_ = _2013_ & _2014_;
+ assign _2016_ = _2009_ | _2015_;
+ assign _2017_ = ~ wbseq_q[2];
+ assign _2018_ = wbseq_q[3] & _2017_;
+ assign _2019_ = ~ wbseq_q[1];
+ assign _2020_ = _2018_ & _2019_;
+ assign _2021_ = _2020_ & wbseq_q[0];
+ assign wb_remote_wr = _2016_ | _2021_;
+ assign _2022_ = wbseq_q[3] & wbseq_q[2];
+ assign _2023_ = _2022_ & wbseq_q[1];
+ assign _2024_ = _2023_ & wbseq_q[0];
+ assign _2025_ = _2024_ & wb_req;
+ assign _2026_ = ~ wb_we;
+ assign _0000_ = _2025_ & _2026_;
+ assign _0001_ = _0000_ & wb_local;
+ assign _0002_ = wbseq_q[3] & wbseq_q[2];
+ assign _0003_ = _0002_ & wbseq_q[1];
+ assign _0004_ = _0003_ & wbseq_q[0];
+ assign _0005_ = _0004_ & wb_req;
+ assign _0006_ = _0005_ & wb_we;
+ assign _0007_ = _0006_ & wb_local;
+ assign _0008_ = _0001_ | _0007_;
+ assign _0009_ = wbseq_q[3] & wbseq_q[2];
+ assign _0010_ = _0009_ & wbseq_q[1];
+ assign _0011_ = _0010_ & wbseq_q[0];
+ assign _0012_ = _0011_ & wb_req;
+ assign _0013_ = ~ wb_we;
+ assign _0014_ = _0012_ & _0013_;
+ assign _0015_ = ~ wb_local;
+ assign _0016_ = _0014_ & _0015_;
+ assign _0017_ = _0008_ | _0016_;
+ assign _0018_ = wbseq_q[3] & wbseq_q[2];
+ assign _0019_ = _0018_ & wbseq_q[1];
+ assign _0020_ = _0019_ & wbseq_q[0];
+ assign _0021_ = _0020_ & wb_req;
+ assign _0022_ = _0021_ & wb_we;
+ assign _0023_ = ~ wb_local;
+ assign _0024_ = _0022_ & _0023_;
+ assign _0025_ = _0017_ | _0024_;
+ assign _0026_ = ~ wbseq_q[3];
+ assign _0027_ = ~ wbseq_q[2];
+ assign _0028_ = _0026_ & _0027_;
+ assign _0029_ = ~ wbseq_q[1];
+ assign _0030_ = _0028_ & _0029_;
+ assign _0031_ = _0030_ & wbseq_q[0];
+ assign _0032_ = _0025_ | _0031_;
+ assign _0033_ = ~ wbseq_q[3];
+ assign _0034_ = ~ wbseq_q[2];
+ assign _0035_ = _0033_ & _0034_;
+ assign _0036_ = _0035_ & wbseq_q[1];
+ assign _0037_ = ~ wbseq_q[0];
+ assign _0038_ = _0036_ & _0037_;
+ assign _0039_ = _0032_ | _0038_;
+ assign _0040_ = ~ wbseq_q[3];
+ assign _0041_ = _0040_ & wbseq_q[2];
+ assign _0042_ = ~ wbseq_q[1];
+ assign _0043_ = _0041_ & _0042_;
+ assign _0044_ = ~ wbseq_q[0];
+ assign _0045_ = _0043_ & _0044_;
+ assign _0046_ = _0039_ | _0045_;
+ assign _0047_ = ~ wbseq_q[3];
+ assign _0048_ = _0047_ & wbseq_q[2];
+ assign _0049_ = ~ wbseq_q[1];
+ assign _0050_ = _0048_ & _0049_;
+ assign _0051_ = _0050_ & wbseq_q[0];
+ assign _0052_ = _0046_ | _0051_;
+ assign _0053_ = ~ wbseq_q[3];
+ assign _0054_ = _0053_ & wbseq_q[2];
+ assign _0055_ = _0054_ & wbseq_q[1];
+ assign _0056_ = ~ wbseq_q[0];
+ assign _0057_ = _0055_ & _0056_;
+ assign _0058_ = ~ rd_rsp_complete;
+ assign _0059_ = _0057_ & _0058_;
+ assign _0060_ = _0052_ | _0059_;
+ assign _0061_ = ~ wbseq_q[2];
+ assign _0062_ = wbseq_q[3] & _0061_;
+ assign _0063_ = ~ wbseq_q[1];
+ assign _0064_ = _0062_ & _0063_;
+ assign _0065_ = ~ wbseq_q[0];
+ assign _0066_ = _0064_ & _0065_;
+ assign _0067_ = _0060_ | _0066_;
+ assign _0068_ = ~ wbseq_q[2];
+ assign _0069_ = wbseq_q[3] & _0068_;
+ assign _0070_ = ~ wbseq_q[1];
+ assign _0071_ = _0069_ & _0070_;
+ assign _0072_ = _0071_ & wbseq_q[0];
+ assign _0073_ = _0067_ | _0072_;
+ assign _0074_ = ~ wbseq_q[2];
+ assign _0075_ = wbseq_q[3] & _0074_;
+ assign _0076_ = _0075_ & wbseq_q[1];
+ assign _0077_ = ~ wbseq_q[0];
+ assign _0078_ = _0076_ & _0077_;
+ assign _0079_ = _0073_ | _0078_;
+ assign _0080_ = ~ wbseq_q[3];
+ assign _0081_ = ~ wbseq_q[2];
+ assign _0082_ = _0080_ & _0081_;
+ assign _0083_ = ~ wbseq_q[1];
+ assign _0084_ = _0082_ & _0083_;
+ assign _0085_ = _0084_ & wbseq_q[0];
+ assign _0086_ = ~ wbseq_q[3];
+ assign _0087_ = ~ wbseq_q[2];
+ assign _0088_ = _0086_ & _0087_;
+ assign _0089_ = _0088_ & wbseq_q[1];
+ assign _0090_ = ~ wbseq_q[0];
+ assign _0091_ = _0089_ & _0090_;
+ assign _0092_ = _0085_ | _0091_;
+ assign _0093_ = ~ wbseq_q[3];
+ assign _0094_ = _0093_ & wbseq_q[2];
+ assign _0095_ = _0094_ & wbseq_q[1];
+ assign _0096_ = ~ wbseq_q[0];
+ assign _0097_ = _0095_ & _0096_;
+ assign _0098_ = ~ rd_rsp_complete;
+ assign _0099_ = _0097_ & _0098_;
+ assign _0100_ = _0092_ | _0099_;
+ assign _0101_ = ~ wbseq_q[2];
+ assign _0102_ = wbseq_q[3] & _0101_;
+ assign _0103_ = _0102_ & wbseq_q[1];
+ assign _0104_ = ~ wbseq_q[0];
+ assign _0105_ = _0103_ & _0104_;
+ assign _0106_ = _0100_ | _0105_;
+ assign _0107_ = ~ wbseq_q[3];
+ assign _0108_ = _0107_ & wbseq_q[2];
+ assign _0109_ = ~ wbseq_q[1];
+ assign _0110_ = _0108_ & _0109_;
+ assign _0111_ = _0110_ & wbseq_q[0];
+ assign _0112_ = ~ wbseq_q[3];
+ assign _0113_ = _0112_ & wbseq_q[2];
+ assign _0114_ = _0113_ & wbseq_q[1];
+ assign _0115_ = ~ wbseq_q[0];
+ assign _0116_ = _0114_ & _0115_;
+ assign _0117_ = ~ rd_rsp_complete;
+ assign _0118_ = _0116_ & _0117_;
+ assign _0119_ = _0111_ | _0118_;
+ assign _0120_ = ~ wbseq_q[2];
+ assign _0121_ = wbseq_q[3] & _0120_;
+ assign _0122_ = ~ wbseq_q[1];
+ assign _0123_ = _0121_ & _0122_;
+ assign _0124_ = _0123_ & wbseq_q[0];
+ assign _0125_ = _0119_ | _0124_;
+ assign _0126_ = ~ wbseq_q[2];
+ assign _0127_ = wbseq_q[3] & _0126_;
+ assign _0128_ = _0127_ & wbseq_q[1];
+ assign _0129_ = ~ wbseq_q[0];
+ assign _0130_ = _0128_ & _0129_;
+ assign _0131_ = _0125_ | _0130_;
+ assign _0132_ = wbseq_q[3] & wbseq_q[2];
+ assign _0133_ = _0132_ & wbseq_q[1];
+ assign _0134_ = ~ wbseq_q[0];
+ assign _0135_ = _0133_ & _0134_;
+ assign oseq_hold = _0131_ | _0135_;
+ assign _0136_ = ~ wbseq_q[3];
+ assign _0137_ = ~ wbseq_q[2];
+ assign _0138_ = _0136_ & _0137_;
+ assign _0139_ = ~ wbseq_q[1];
+ assign _0140_ = _0138_ & _0139_;
+ assign _0141_ = ~ wbseq_q[0];
+ assign _0142_ = _0140_ & _0141_;
+ assign _0143_ = ~ wbseq_q[3];
+ assign _0144_ = ~ wbseq_q[2];
+ assign _0145_ = _0143_ & _0144_;
+ assign _0146_ = _0145_ & wbseq_q[1];
+ assign _0147_ = _0146_ & wbseq_q[0];
+ assign _0148_ = _0142_ | _0147_;
+ assign _0149_ = ~ wbseq_q[3];
+ assign _0150_ = _0149_ & wbseq_q[2];
+ assign _0151_ = _0150_ & wbseq_q[1];
+ assign _0152_ = _0151_ & wbseq_q[0];
+ assign _0153_ = _0148_ | _0152_;
+ assign _0154_ = ~ wbseq_q[2];
+ assign _0155_ = wbseq_q[3] & _0154_;
+ assign _0156_ = _0155_ & wbseq_q[1];
+ assign _0157_ = _0156_ & wbseq_q[0];
+ assign _0158_ = _0153_ | _0157_;
+ assign _0159_ = wbseq_q[3] & wbseq_q[2];
+ assign _0160_ = ~ wbseq_q[1];
+ assign _0161_ = _0159_ & _0160_;
+ assign _0162_ = ~ wbseq_q[0];
+ assign _0163_ = _0161_ & _0162_;
+ assign _0164_ = _0158_ | _0163_;
+ assign _0165_ = wbseq_q[3] & wbseq_q[2];
+ assign _0166_ = ~ wbseq_q[1];
+ assign _0167_ = _0165_ & _0166_;
+ assign _0168_ = _0167_ & wbseq_q[0];
+ assign wbseq_err = _0164_ | _0168_;
+ assign _0169_ = oseq_q[3] & oseq_q[2];
+ assign _0170_ = _0169_ & oseq_q[1];
+ assign _0171_ = _0170_ & oseq_q[0];
+ assign _0172_ = _0171_ & oseq_hold;
+ assign _0173_ = oseq_q[3] & oseq_q[2];
+ assign _0174_ = _0173_ & oseq_q[1];
+ assign _0175_ = _0174_ & oseq_q[0];
+ assign _0176_ = ~ wb_remote_rd;
+ assign _0177_ = _0175_ & _0176_;
+ assign _0178_ = ~ wb_remote_wr;
+ assign _0179_ = _0177_ & _0178_;
+ assign _0180_ = _0172_ | _0179_;
+ assign _0181_ = oseq_q[3] & oseq_q[2];
+ assign _0182_ = _0181_ & oseq_q[1];
+ assign _0183_ = _0182_ & oseq_q[0];
+ assign _0184_ = ~ oseq_hold;
+ assign _0185_ = _0183_ & _0184_;
+ assign _0186_ = ~ oclk_advance;
+ assign _0187_ = _0185_ & _0186_;
+ assign _0188_ = _0180_ | _0187_;
+ assign _0189_ = ~ oseq_q[3];
+ assign _0190_ = ~ oseq_q[2];
+ assign _0191_ = _0189_ & _0190_;
+ assign _0192_ = _0191_ & oseq_q[1];
+ assign _0193_ = ~ oseq_q[0];
+ assign _0194_ = _0192_ & _0193_;
+ assign _0195_ = ~ wb_remote_wr;
+ assign _0196_ = _0194_ & _0195_;
+ assign _0197_ = _0196_ & oclk_advance;
+ assign _0198_ = _0197_ & oaddr_last;
+ assign _0199_ = _0188_ | _0198_;
+ assign _0200_ = ~ oseq_q[3];
+ assign _0201_ = _0200_ & oseq_q[2];
+ assign _0202_ = ~ oseq_q[1];
+ assign _0203_ = _0201_ & _0202_;
+ assign _0204_ = ~ oseq_q[0];
+ assign _0205_ = _0203_ & _0204_;
+ assign _0206_ = _0205_ & oclk_advance;
+ assign _0207_ = _0206_ & odata_last;
+ assign _0208_ = _0199_ | _0207_;
+ assign _0209_ = ~ oseq_q[2];
+ assign _0210_ = oseq_q[3] & _0209_;
+ assign _0211_ = ~ oseq_q[1];
+ assign _0212_ = _0210_ & _0211_;
+ assign _0213_ = ~ oseq_q[0];
+ assign _0214_ = _0212_ & _0213_;
+ assign _0215_ = _0208_ | _0214_;
+ assign _0216_ = ~ oseq_q[2];
+ assign _0217_ = oseq_q[3] & _0216_;
+ assign _0218_ = ~ oseq_q[1];
+ assign _0219_ = _0217_ & _0218_;
+ assign _0220_ = _0219_ & oseq_q[0];
+ assign _0221_ = _0215_ | _0220_;
+ assign _0222_ = ~ oseq_q[2];
+ assign _0223_ = oseq_q[3] & _0222_;
+ assign _0224_ = _0223_ & oseq_q[1];
+ assign _0225_ = ~ oseq_q[0];
+ assign _0226_ = _0224_ & _0225_;
+ assign _0227_ = _0221_ | _0226_;
+ assign _0228_ = ~ oseq_q[2];
+ assign _0229_ = oseq_q[3] & _0228_;
+ assign _0230_ = _0229_ & oseq_q[1];
+ assign _0231_ = _0230_ & oseq_q[0];
+ assign _0232_ = _0227_ | _0231_;
+ assign _0233_ = oseq_q[3] & oseq_q[2];
+ assign _0234_ = ~ oseq_q[1];
+ assign _0235_ = _0233_ & _0234_;
+ assign _0236_ = ~ oseq_q[0];
+ assign _0237_ = _0235_ & _0236_;
+ assign _0238_ = _0232_ | _0237_;
+ assign _0239_ = oseq_q[3] & oseq_q[2];
+ assign _0240_ = ~ oseq_q[1];
+ assign _0241_ = _0239_ & _0240_;
+ assign _0242_ = _0241_ & oseq_q[0];
+ assign _0243_ = _0238_ | _0242_;
+ assign _0244_ = oseq_q[3] & oseq_q[2];
+ assign _0245_ = _0244_ & oseq_q[1];
+ assign _0246_ = ~ oseq_q[0];
+ assign _0247_ = _0245_ & _0246_;
+ assign _0248_ = _0243_ | _0247_;
+ assign _0249_ = oseq_q[3] & oseq_q[2];
+ assign _0250_ = _0249_ & oseq_q[1];
+ assign _0251_ = _0250_ & oseq_q[0];
+ assign _0252_ = _0251_ & oseq_hold;
+ assign _0253_ = oseq_q[3] & oseq_q[2];
+ assign _0254_ = _0253_ & oseq_q[1];
+ assign _0255_ = _0254_ & oseq_q[0];
+ assign _0256_ = ~ wb_remote_rd;
+ assign _0257_ = _0255_ & _0256_;
+ assign _0258_ = ~ wb_remote_wr;
+ assign _0259_ = _0257_ & _0258_;
+ assign _0260_ = _0252_ | _0259_;
+ assign _0261_ = oseq_q[3] & oseq_q[2];
+ assign _0262_ = _0261_ & oseq_q[1];
+ assign _0263_ = _0262_ & oseq_q[0];
+ assign _0264_ = ~ oseq_hold;
+ assign _0265_ = _0263_ & _0264_;
+ assign _0266_ = ~ oclk_advance;
+ assign _0267_ = _0265_ & _0266_;
+ assign _0268_ = _0260_ | _0267_;
+ assign _0269_ = ~ oseq_q[3];
+ assign _0270_ = ~ oseq_q[2];
+ assign _0271_ = _0269_ & _0270_;
+ assign _0272_ = _0271_ & oseq_q[1];
+ assign _0273_ = ~ oseq_q[0];
+ assign _0274_ = _0272_ & _0273_;
+ assign _0275_ = ~ wb_remote_wr;
+ assign _0276_ = _0274_ & _0275_;
+ assign _0277_ = _0276_ & oclk_advance;
+ assign _0278_ = _0277_ & oaddr_last;
+ assign _0279_ = _0268_ | _0278_;
+ assign _0280_ = ~ oseq_q[3];
+ assign _0281_ = ~ oseq_q[2];
+ assign _0282_ = _0280_ & _0281_;
+ assign _0283_ = _0282_ & oseq_q[1];
+ assign _0284_ = _0283_ & oseq_q[0];
+ assign _0285_ = _0284_ & oclk_advance;
+ assign _0286_ = _0279_ | _0285_;
+ assign _0287_ = ~ oseq_q[3];
+ assign _0288_ = _0287_ & oseq_q[2];
+ assign _0289_ = ~ oseq_q[1];
+ assign _0290_ = _0288_ & _0289_;
+ assign _0291_ = ~ oseq_q[0];
+ assign _0292_ = _0290_ & _0291_;
+ assign _0293_ = ~ oclk_advance;
+ assign _0294_ = _0292_ & _0293_;
+ assign _0295_ = _0286_ | _0294_;
+ assign _0296_ = ~ oseq_q[3];
+ assign _0297_ = _0296_ & oseq_q[2];
+ assign _0298_ = ~ oseq_q[1];
+ assign _0299_ = _0297_ & _0298_;
+ assign _0300_ = ~ oseq_q[0];
+ assign _0301_ = _0299_ & _0300_;
+ assign _0302_ = _0301_ & oclk_advance;
+ assign _0303_ = ~ odata_last;
+ assign _0304_ = _0302_ & _0303_;
+ assign _0305_ = _0295_ | _0304_;
+ assign _0306_ = ~ oseq_q[3];
+ assign _0307_ = _0306_ & oseq_q[2];
+ assign _0308_ = ~ oseq_q[1];
+ assign _0309_ = _0307_ & _0308_;
+ assign _0310_ = ~ oseq_q[0];
+ assign _0311_ = _0309_ & _0310_;
+ assign _0312_ = _0311_ & oclk_advance;
+ assign _0313_ = _0312_ & odata_last;
+ assign _0314_ = _0305_ | _0313_;
+ assign _0315_ = ~ oseq_q[3];
+ assign _0316_ = _0315_ & oseq_q[2];
+ assign _0317_ = ~ oseq_q[1];
+ assign _0318_ = _0316_ & _0317_;
+ assign _0319_ = _0318_ & oseq_q[0];
+ assign _0320_ = _0314_ | _0319_;
+ assign _0321_ = ~ oseq_q[3];
+ assign _0322_ = _0321_ & oseq_q[2];
+ assign _0323_ = _0322_ & oseq_q[1];
+ assign _0324_ = ~ oseq_q[0];
+ assign _0325_ = _0323_ & _0324_;
+ assign _0326_ = _0320_ | _0325_;
+ assign _0327_ = ~ oseq_q[3];
+ assign _0328_ = _0327_ & oseq_q[2];
+ assign _0329_ = _0328_ & oseq_q[1];
+ assign _0330_ = _0329_ & oseq_q[0];
+ assign _0331_ = _0326_ | _0330_;
+ assign _0332_ = oseq_q[3] & oseq_q[2];
+ assign _0333_ = ~ oseq_q[1];
+ assign _0334_ = _0332_ & _0333_;
+ assign _0335_ = ~ oseq_q[0];
+ assign _0336_ = _0334_ & _0335_;
+ assign _0337_ = _0331_ | _0336_;
+ assign _0338_ = oseq_q[3] & oseq_q[2];
+ assign _0339_ = ~ oseq_q[1];
+ assign _0340_ = _0338_ & _0339_;
+ assign _0341_ = _0340_ & oseq_q[0];
+ assign _0342_ = _0337_ | _0341_;
+ assign _0343_ = oseq_q[3] & oseq_q[2];
+ assign _0344_ = _0343_ & oseq_q[1];
+ assign _0345_ = ~ oseq_q[0];
+ assign _0346_ = _0344_ & _0345_;
+ assign _0347_ = _0342_ | _0346_;
+ assign _0348_ = oseq_q[3] & oseq_q[2];
+ assign _0349_ = _0348_ & oseq_q[1];
+ assign _0350_ = _0349_ & oseq_q[0];
+ assign _0351_ = _0350_ & oseq_hold;
+ assign _0352_ = oseq_q[3] & oseq_q[2];
+ assign _0353_ = _0352_ & oseq_q[1];
+ assign _0354_ = _0353_ & oseq_q[0];
+ assign _0355_ = ~ wb_remote_rd;
+ assign _0356_ = _0354_ & _0355_;
+ assign _0357_ = ~ wb_remote_wr;
+ assign _0358_ = _0356_ & _0357_;
+ assign _0359_ = _0351_ | _0358_;
+ assign _0360_ = oseq_q[3] & oseq_q[2];
+ assign _0361_ = _0360_ & oseq_q[1];
+ assign _0362_ = _0361_ & oseq_q[0];
+ assign _0363_ = ~ oseq_hold;
+ assign _0364_ = _0362_ & _0363_;
+ assign _0365_ = ~ oclk_advance;
+ assign _0366_ = _0364_ & _0365_;
+ assign _0367_ = _0359_ | _0366_;
+ assign _0368_ = ~ oseq_q[3];
+ assign _0369_ = ~ oseq_q[2];
+ assign _0370_ = _0368_ & _0369_;
+ assign _0371_ = ~ oseq_q[1];
+ assign _0372_ = _0370_ & _0371_;
+ assign _0373_ = _0372_ & oseq_q[0];
+ assign _0374_ = _0373_ & wb_remote_rd;
+ assign _0375_ = _0374_ & oclk_advance;
+ assign _0376_ = _0367_ | _0375_;
+ assign _0377_ = ~ oseq_q[3];
+ assign _0378_ = ~ oseq_q[2];
+ assign _0379_ = _0377_ & _0378_;
+ assign _0380_ = ~ oseq_q[1];
+ assign _0381_ = _0379_ & _0380_;
+ assign _0382_ = _0381_ & oseq_q[0];
+ assign _0383_ = _0382_ & wb_remote_wr;
+ assign _0384_ = _0383_ & oclk_advance;
+ assign _0385_ = _0376_ | _0384_;
+ assign _0386_ = ~ oseq_q[3];
+ assign _0387_ = ~ oseq_q[2];
+ assign _0388_ = _0386_ & _0387_;
+ assign _0389_ = _0388_ & oseq_q[1];
+ assign _0390_ = ~ oseq_q[0];
+ assign _0391_ = _0389_ & _0390_;
+ assign _0392_ = ~ oclk_advance;
+ assign _0393_ = _0391_ & _0392_;
+ assign _0394_ = _0385_ | _0393_;
+ assign _0395_ = ~ oseq_q[3];
+ assign _0396_ = ~ oseq_q[2];
+ assign _0397_ = _0395_ & _0396_;
+ assign _0398_ = _0397_ & oseq_q[1];
+ assign _0399_ = ~ oseq_q[0];
+ assign _0400_ = _0398_ & _0399_;
+ assign _0401_ = _0400_ & oclk_advance;
+ assign _0402_ = ~ oaddr_last;
+ assign _0403_ = _0401_ & _0402_;
+ assign _0404_ = _0394_ | _0403_;
+ assign _0405_ = ~ oseq_q[3];
+ assign _0406_ = ~ oseq_q[2];
+ assign _0407_ = _0405_ & _0406_;
+ assign _0408_ = _0407_ & oseq_q[1];
+ assign _0409_ = ~ oseq_q[0];
+ assign _0410_ = _0408_ & _0409_;
+ assign _0411_ = ~ wb_remote_wr;
+ assign _0412_ = _0410_ & _0411_;
+ assign _0413_ = _0412_ & oclk_advance;
+ assign _0414_ = _0413_ & oaddr_last;
+ assign _0415_ = _0404_ | _0414_;
+ assign _0416_ = ~ oseq_q[3];
+ assign _0417_ = ~ oseq_q[2];
+ assign _0418_ = _0416_ & _0417_;
+ assign _0419_ = _0418_ & oseq_q[1];
+ assign _0420_ = ~ oseq_q[0];
+ assign _0421_ = _0419_ & _0420_;
+ assign _0422_ = _0421_ & wb_remote_wr;
+ assign _0423_ = _0422_ & oclk_advance;
+ assign _0424_ = _0423_ & oaddr_last;
+ assign _0425_ = _0415_ | _0424_;
+ assign _0426_ = ~ oseq_q[3];
+ assign _0427_ = ~ oseq_q[2];
+ assign _0428_ = _0426_ & _0427_;
+ assign _0429_ = _0428_ & oseq_q[1];
+ assign _0430_ = _0429_ & oseq_q[0];
+ assign _0431_ = ~ oclk_advance;
+ assign _0432_ = _0430_ & _0431_;
+ assign _0433_ = _0425_ | _0432_;
+ assign _0434_ = ~ oseq_q[3];
+ assign _0435_ = _0434_ & oseq_q[2];
+ assign _0436_ = ~ oseq_q[1];
+ assign _0437_ = _0435_ & _0436_;
+ assign _0438_ = ~ oseq_q[0];
+ assign _0439_ = _0437_ & _0438_;
+ assign _0440_ = _0439_ & oclk_advance;
+ assign _0441_ = _0440_ & odata_last;
+ assign _0442_ = _0433_ | _0441_;
+ assign _0443_ = ~ oseq_q[3];
+ assign _0444_ = _0443_ & oseq_q[2];
+ assign _0445_ = _0444_ & oseq_q[1];
+ assign _0446_ = ~ oseq_q[0];
+ assign _0447_ = _0445_ & _0446_;
+ assign _0448_ = _0442_ | _0447_;
+ assign _0449_ = ~ oseq_q[3];
+ assign _0450_ = _0449_ & oseq_q[2];
+ assign _0451_ = _0450_ & oseq_q[1];
+ assign _0452_ = _0451_ & oseq_q[0];
+ assign _0453_ = _0448_ | _0452_;
+ assign _0454_ = ~ oseq_q[2];
+ assign _0455_ = oseq_q[3] & _0454_;
+ assign _0456_ = _0455_ & oseq_q[1];
+ assign _0457_ = ~ oseq_q[0];
+ assign _0458_ = _0456_ & _0457_;
+ assign _0459_ = _0453_ | _0458_;
+ assign _0460_ = ~ oseq_q[2];
+ assign _0461_ = oseq_q[3] & _0460_;
+ assign _0462_ = _0461_ & oseq_q[1];
+ assign _0463_ = _0462_ & oseq_q[0];
+ assign _0464_ = _0459_ | _0463_;
+ assign _0465_ = oseq_q[3] & oseq_q[2];
+ assign _0466_ = _0465_ & oseq_q[1];
+ assign _0467_ = ~ oseq_q[0];
+ assign _0468_ = _0466_ & _0467_;
+ assign _0469_ = _0464_ | _0468_;
+ assign _0470_ = oseq_q[3] & oseq_q[2];
+ assign _0471_ = _0470_ & oseq_q[1];
+ assign _0472_ = _0471_ & oseq_q[0];
+ assign _0473_ = _0472_ & oseq_hold;
+ assign _0474_ = oseq_q[3] & oseq_q[2];
+ assign _0475_ = _0474_ & oseq_q[1];
+ assign _0476_ = _0475_ & oseq_q[0];
+ assign _0477_ = ~ wb_remote_rd;
+ assign _0478_ = _0476_ & _0477_;
+ assign _0479_ = ~ wb_remote_wr;
+ assign _0480_ = _0478_ & _0479_;
+ assign _0481_ = _0473_ | _0480_;
+ assign _0482_ = oseq_q[3] & oseq_q[2];
+ assign _0483_ = _0482_ & oseq_q[1];
+ assign _0484_ = _0483_ & oseq_q[0];
+ assign _0485_ = ~ oseq_hold;
+ assign _0486_ = _0484_ & _0485_;
+ assign _0487_ = ~ oclk_advance;
+ assign _0488_ = _0486_ & _0487_;
+ assign _0489_ = _0481_ | _0488_;
+ assign _0490_ = oseq_q[3] & oseq_q[2];
+ assign _0491_ = _0490_ & oseq_q[1];
+ assign _0492_ = _0491_ & oseq_q[0];
+ assign _0493_ = ~ oseq_hold;
+ assign _0494_ = _0492_ & _0493_;
+ assign _0495_ = _0494_ & wb_remote_rd;
+ assign _0496_ = _0495_ & oclk_advance;
+ assign _0497_ = _0489_ | _0496_;
+ assign _0498_ = oseq_q[3] & oseq_q[2];
+ assign _0499_ = _0498_ & oseq_q[1];
+ assign _0500_ = _0499_ & oseq_q[0];
+ assign _0501_ = ~ oseq_hold;
+ assign _0502_ = _0500_ & _0501_;
+ assign _0503_ = _0502_ & wb_remote_wr;
+ assign _0504_ = _0503_ & oclk_advance;
+ assign _0505_ = _0497_ | _0504_;
+ assign _0506_ = ~ oseq_q[3];
+ assign _0507_ = ~ oseq_q[2];
+ assign _0508_ = _0506_ & _0507_;
+ assign _0509_ = ~ oseq_q[1];
+ assign _0510_ = _0508_ & _0509_;
+ assign _0511_ = _0510_ & oseq_q[0];
+ assign _0512_ = ~ oclk_advance;
+ assign _0513_ = _0511_ & _0512_;
+ assign _0514_ = _0505_ | _0513_;
+ assign _0515_ = ~ oseq_q[3];
+ assign _0516_ = ~ oseq_q[2];
+ assign _0517_ = _0515_ & _0516_;
+ assign _0518_ = _0517_ & oseq_q[1];
+ assign _0519_ = ~ oseq_q[0];
+ assign _0520_ = _0518_ & _0519_;
+ assign _0521_ = ~ wb_remote_wr;
+ assign _0522_ = _0520_ & _0521_;
+ assign _0523_ = _0522_ & oclk_advance;
+ assign _0524_ = _0523_ & oaddr_last;
+ assign _0525_ = _0514_ | _0524_;
+ assign _0526_ = ~ oseq_q[3];
+ assign _0527_ = ~ oseq_q[2];
+ assign _0528_ = _0526_ & _0527_;
+ assign _0529_ = _0528_ & oseq_q[1];
+ assign _0530_ = ~ oseq_q[0];
+ assign _0531_ = _0529_ & _0530_;
+ assign _0532_ = _0531_ & wb_remote_wr;
+ assign _0533_ = _0532_ & oclk_advance;
+ assign _0534_ = _0533_ & oaddr_last;
+ assign _0535_ = _0525_ | _0534_;
+ assign _0536_ = ~ oseq_q[3];
+ assign _0537_ = ~ oseq_q[2];
+ assign _0538_ = _0536_ & _0537_;
+ assign _0539_ = _0538_ & oseq_q[1];
+ assign _0540_ = _0539_ & oseq_q[0];
+ assign _0541_ = ~ oclk_advance;
+ assign _0542_ = _0540_ & _0541_;
+ assign _0543_ = _0535_ | _0542_;
+ assign _0544_ = ~ oseq_q[3];
+ assign _0545_ = _0544_ & oseq_q[2];
+ assign _0546_ = ~ oseq_q[1];
+ assign _0547_ = _0545_ & _0546_;
+ assign _0548_ = ~ oseq_q[0];
+ assign _0549_ = _0547_ & _0548_;
+ assign _0550_ = _0549_ & oclk_advance;
+ assign _0551_ = _0550_ & odata_last;
+ assign _0552_ = _0543_ | _0551_;
+ assign _0553_ = ~ oseq_q[3];
+ assign _0554_ = _0553_ & oseq_q[2];
+ assign _0555_ = ~ oseq_q[1];
+ assign _0556_ = _0554_ & _0555_;
+ assign _0557_ = _0556_ & oseq_q[0];
+ assign _0558_ = _0552_ | _0557_;
+ assign _0559_ = ~ oseq_q[3];
+ assign _0560_ = _0559_ & oseq_q[2];
+ assign _0561_ = _0560_ & oseq_q[1];
+ assign _0562_ = _0561_ & oseq_q[0];
+ assign _0563_ = _0558_ | _0562_;
+ assign _0564_ = ~ oseq_q[2];
+ assign _0565_ = oseq_q[3] & _0564_;
+ assign _0566_ = ~ oseq_q[1];
+ assign _0567_ = _0565_ & _0566_;
+ assign _0568_ = _0567_ & oseq_q[0];
+ assign _0569_ = _0563_ | _0568_;
+ assign _0570_ = ~ oseq_q[2];
+ assign _0571_ = oseq_q[3] & _0570_;
+ assign _0572_ = _0571_ & oseq_q[1];
+ assign _0573_ = _0572_ & oseq_q[0];
+ assign _0574_ = _0569_ | _0573_;
+ assign _0575_ = oseq_q[3] & oseq_q[2];
+ assign _0576_ = ~ oseq_q[1];
+ assign _0577_ = _0575_ & _0576_;
+ assign _0578_ = _0577_ & oseq_q[0];
+ assign _0579_ = _0574_ | _0578_;
+ assign _0580_ = oseq_q[3] & oseq_q[2];
+ assign _0581_ = _0580_ & oseq_q[1];
+ assign _0582_ = _0581_ & oseq_q[0];
+ assign _0583_ = ~ oseq_hold;
+ assign _0584_ = _0582_ & _0583_;
+ assign _0585_ = _0584_ & wb_remote_rd;
+ assign _0586_ = _0585_ & oclk_advance;
+ assign _0587_ = oseq_q[3] & oseq_q[2];
+ assign _0588_ = _0587_ & oseq_q[1];
+ assign _0589_ = _0588_ & oseq_q[0];
+ assign _0590_ = ~ oseq_hold;
+ assign _0591_ = _0589_ & _0590_;
+ assign _0592_ = _0591_ & wb_remote_wr;
+ assign _0593_ = _0592_ & oclk_advance;
+ assign odata_ld_header = _0586_ | _0593_;
+ assign _0594_ = ~ oseq_q[3];
+ assign _0595_ = ~ oseq_q[2];
+ assign _0596_ = _0594_ & _0595_;
+ assign _0597_ = ~ oseq_q[1];
+ assign _0598_ = _0596_ & _0597_;
+ assign _0599_ = _0598_ & oseq_q[0];
+ assign _0600_ = _0599_ & wb_remote_rd;
+ assign _0601_ = _0600_ & oclk_advance;
+ assign _0602_ = ~ oseq_q[3];
+ assign _0603_ = ~ oseq_q[2];
+ assign _0604_ = _0602_ & _0603_;
+ assign _0605_ = ~ oseq_q[1];
+ assign _0606_ = _0604_ & _0605_;
+ assign _0607_ = _0606_ & oseq_q[0];
+ assign _0608_ = _0607_ & wb_remote_wr;
+ assign _0609_ = _0608_ & oclk_advance;
+ assign _0610_ = _0601_ | _0609_;
+ assign _0611_ = ~ oseq_q[3];
+ assign _0612_ = ~ oseq_q[2];
+ assign _0613_ = _0611_ & _0612_;
+ assign _0614_ = _0613_ & oseq_q[1];
+ assign _0615_ = ~ oseq_q[0];
+ assign _0616_ = _0614_ & _0615_;
+ assign _0617_ = ~ oclk_advance;
+ assign _0618_ = _0616_ & _0617_;
+ assign _0619_ = _0610_ | _0618_;
+ assign _0620_ = ~ oseq_q[3];
+ assign _0621_ = ~ oseq_q[2];
+ assign _0622_ = _0620_ & _0621_;
+ assign _0623_ = _0622_ & oseq_q[1];
+ assign _0624_ = ~ oseq_q[0];
+ assign _0625_ = _0623_ & _0624_;
+ assign _0626_ = _0625_ & oclk_advance;
+ assign _0627_ = ~ oaddr_last;
+ assign _0628_ = _0626_ & _0627_;
+ assign odata_ld_addr = _0619_ | _0628_;
+ assign _0629_ = ~ oseq_q[3];
+ assign _0630_ = ~ oseq_q[2];
+ assign _0631_ = _0629_ & _0630_;
+ assign _0632_ = _0631_ & oseq_q[1];
+ assign _0633_ = ~ oseq_q[0];
+ assign _0634_ = _0632_ & _0633_;
+ assign _0635_ = _0634_ & wb_remote_wr;
+ assign _0636_ = _0635_ & oclk_advance;
+ assign odata_ld_sel = _0636_ & oaddr_last;
+ assign _0637_ = oseq_q[3] & oseq_q[2];
+ assign _0638_ = _0637_ & oseq_q[1];
+ assign _0639_ = _0638_ & oseq_q[0];
+ assign _0640_ = _0639_ & oseq_hold;
+ assign _0641_ = oseq_q[3] & oseq_q[2];
+ assign _0642_ = _0641_ & oseq_q[1];
+ assign _0643_ = _0642_ & oseq_q[0];
+ assign _0644_ = ~ wb_remote_rd;
+ assign _0645_ = _0643_ & _0644_;
+ assign _0646_ = ~ wb_remote_wr;
+ assign _0647_ = _0645_ & _0646_;
+ assign _0648_ = _0640_ | _0647_;
+ assign _0649_ = oseq_q[3] & oseq_q[2];
+ assign _0650_ = _0649_ & oseq_q[1];
+ assign _0651_ = _0650_ & oseq_q[0];
+ assign _0652_ = ~ oseq_hold;
+ assign _0653_ = _0651_ & _0652_;
+ assign _0654_ = ~ oclk_advance;
+ assign _0655_ = _0653_ & _0654_;
+ assign _0656_ = _0648_ | _0655_;
+ assign _0657_ = ~ oseq_q[3];
+ assign _0658_ = ~ oseq_q[2];
+ assign _0659_ = _0657_ & _0658_;
+ assign _0660_ = _0659_ & oseq_q[1];
+ assign _0661_ = ~ oseq_q[0];
+ assign _0662_ = _0660_ & _0661_;
+ assign _0663_ = ~ wb_remote_wr;
+ assign _0664_ = _0662_ & _0663_;
+ assign _0665_ = _0664_ & oclk_advance;
+ assign _0666_ = _0665_ & oaddr_last;
+ assign _0667_ = _0656_ | _0666_;
+ assign _0668_ = ~ oseq_q[3];
+ assign _0669_ = ~ oseq_q[2];
+ assign _0670_ = _0668_ & _0669_;
+ assign _0671_ = _0670_ & oseq_q[1];
+ assign _0672_ = ~ oseq_q[0];
+ assign _0673_ = _0671_ & _0672_;
+ assign _0674_ = _0673_ & wb_remote_wr;
+ assign _0675_ = _0674_ & oclk_advance;
+ assign _0676_ = _0675_ & oaddr_last;
+ assign odata_clear = _0667_ | _0676_;
+ assign _0677_ = ~ oseq_q[3];
+ assign _0678_ = ~ oseq_q[2];
+ assign _0679_ = _0677_ & _0678_;
+ assign _0680_ = _0679_ & oseq_q[1];
+ assign _0681_ = _0680_ & oseq_q[0];
+ assign _0682_ = _0681_ & oclk_advance;
+ assign _0683_ = ~ oseq_q[3];
+ assign _0684_ = _0683_ & oseq_q[2];
+ assign _0685_ = ~ oseq_q[1];
+ assign _0686_ = _0684_ & _0685_;
+ assign _0687_ = ~ oseq_q[0];
+ assign _0688_ = _0686_ & _0687_;
+ assign _0689_ = ~ oclk_advance;
+ assign _0690_ = _0688_ & _0689_;
+ assign _0691_ = _0682_ | _0690_;
+ assign _0692_ = ~ oseq_q[3];
+ assign _0693_ = _0692_ & oseq_q[2];
+ assign _0694_ = ~ oseq_q[1];
+ assign _0695_ = _0693_ & _0694_;
+ assign _0696_ = ~ oseq_q[0];
+ assign _0697_ = _0695_ & _0696_;
+ assign _0698_ = _0697_ & oclk_advance;
+ assign _0699_ = ~ odata_last;
+ assign _0700_ = _0698_ & _0699_;
+ assign _0701_ = _0691_ | _0700_;
+ assign _0702_ = ~ oseq_q[3];
+ assign _0703_ = _0702_ & oseq_q[2];
+ assign _0704_ = ~ oseq_q[1];
+ assign _0705_ = _0703_ & _0704_;
+ assign _0706_ = ~ oseq_q[0];
+ assign _0707_ = _0705_ & _0706_;
+ assign _0708_ = _0707_ & oclk_advance;
+ assign _0709_ = _0708_ & odata_last;
+ assign odata_ld_data = _0701_ | _0709_;
+ assign _0710_ = ~ oseq_q[3];
+ assign _0711_ = ~ oseq_q[2];
+ assign _0712_ = _0710_ & _0711_;
+ assign _0713_ = _0712_ & oseq_q[1];
+ assign _0714_ = ~ oseq_q[0];
+ assign _0715_ = _0713_ & _0714_;
+ assign _0716_ = ~ wb_remote_wr;
+ assign _0717_ = _0715_ & _0716_;
+ assign _0718_ = _0717_ & oclk_advance;
+ assign _0719_ = _0718_ & oaddr_last;
+ assign _0720_ = ~ oseq_q[3];
+ assign _0721_ = _0720_ & oseq_q[2];
+ assign _0722_ = ~ oseq_q[1];
+ assign _0723_ = _0721_ & _0722_;
+ assign _0724_ = ~ oseq_q[0];
+ assign _0725_ = _0723_ & _0724_;
+ assign _0726_ = _0725_ & oclk_advance;
+ assign _0727_ = _0726_ & odata_last;
+ assign ob_complete = _0719_ | _0727_;
+ assign _0728_ = ~ oseq_q[3];
+ assign _0729_ = ~ oseq_q[2];
+ assign _0730_ = _0728_ & _0729_;
+ assign _0731_ = ~ oseq_q[1];
+ assign _0732_ = _0730_ & _0731_;
+ assign _0733_ = ~ oseq_q[0];
+ assign _0734_ = _0732_ & _0733_;
+ assign _0735_ = ~ oseq_q[3];
+ assign _0736_ = _0735_ & oseq_q[2];
+ assign _0737_ = ~ oseq_q[1];
+ assign _0738_ = _0736_ & _0737_;
+ assign _0739_ = _0738_ & oseq_q[0];
+ assign _0740_ = _0734_ | _0739_;
+ assign _0741_ = ~ oseq_q[3];
+ assign _0742_ = _0741_ & oseq_q[2];
+ assign _0743_ = _0742_ & oseq_q[1];
+ assign _0744_ = ~ oseq_q[0];
+ assign _0745_ = _0743_ & _0744_;
+ assign _0746_ = _0740_ | _0745_;
+ assign _0747_ = ~ oseq_q[3];
+ assign _0748_ = _0747_ & oseq_q[2];
+ assign _0749_ = _0748_ & oseq_q[1];
+ assign _0750_ = _0749_ & oseq_q[0];
+ assign _0751_ = _0746_ | _0750_;
+ assign _0752_ = ~ oseq_q[2];
+ assign _0753_ = oseq_q[3] & _0752_;
+ assign _0754_ = ~ oseq_q[1];
+ assign _0755_ = _0753_ & _0754_;
+ assign _0756_ = ~ oseq_q[0];
+ assign _0757_ = _0755_ & _0756_;
+ assign _0758_ = _0751_ | _0757_;
+ assign _0759_ = ~ oseq_q[2];
+ assign _0760_ = oseq_q[3] & _0759_;
+ assign _0761_ = ~ oseq_q[1];
+ assign _0762_ = _0760_ & _0761_;
+ assign _0763_ = _0762_ & oseq_q[0];
+ assign _0764_ = _0758_ | _0763_;
+ assign _0765_ = ~ oseq_q[2];
+ assign _0766_ = oseq_q[3] & _0765_;
+ assign _0767_ = _0766_ & oseq_q[1];
+ assign _0768_ = ~ oseq_q[0];
+ assign _0769_ = _0767_ & _0768_;
+ assign _0770_ = _0764_ | _0769_;
+ assign _0771_ = ~ oseq_q[2];
+ assign _0772_ = oseq_q[3] & _0771_;
+ assign _0773_ = _0772_ & oseq_q[1];
+ assign _0774_ = _0773_ & oseq_q[0];
+ assign _0775_ = _0770_ | _0774_;
+ assign _0776_ = oseq_q[3] & oseq_q[2];
+ assign _0777_ = ~ oseq_q[1];
+ assign _0778_ = _0776_ & _0777_;
+ assign _0779_ = ~ oseq_q[0];
+ assign _0780_ = _0778_ & _0779_;
+ assign _0781_ = _0775_ | _0780_;
+ assign _0782_ = oseq_q[3] & oseq_q[2];
+ assign _0783_ = ~ oseq_q[1];
+ assign _0784_ = _0782_ & _0783_;
+ assign _0785_ = _0784_ & oseq_q[0];
+ assign _0786_ = _0781_ | _0785_;
+ assign _0787_ = oseq_q[3] & oseq_q[2];
+ assign _0788_ = _0787_ & oseq_q[1];
+ assign _0789_ = ~ oseq_q[0];
+ assign _0790_ = _0788_ & _0789_;
+ assign oseq_err = _0786_ | _0790_;
+ assign _0791_ = iseq_q[3] & iseq_q[2];
+ assign _0792_ = _0791_ & iseq_q[1];
+ assign _0793_ = _0792_ & iseq_q[0];
+ assign _0794_ = ~ icapture_q;
+ assign _0795_ = _0793_ & _0794_;
+ assign _0796_ = iseq_q[3] & iseq_q[2];
+ assign _0797_ = _0796_ & iseq_q[1];
+ assign _0798_ = _0797_ & iseq_q[0];
+ assign _0799_ = _0798_ & icapture_q;
+ assign _0800_ = _0799_ & idle_header;
+ assign _0801_ = _0795_ | _0800_;
+ assign _0802_ = iseq_q[3] & iseq_q[2];
+ assign _0803_ = _0802_ & iseq_q[1];
+ assign _0804_ = _0803_ & iseq_q[0];
+ assign _0805_ = _0804_ & icapture_q;
+ assign _0806_ = _0805_ & rd8_rsp;
+ assign _0807_ = _0801_ | _0806_;
+ assign _0808_ = ~ iseq_q[2];
+ assign _0809_ = iseq_q[3] & _0808_;
+ assign _0810_ = ~ iseq_q[1];
+ assign _0811_ = _0809_ & _0810_;
+ assign _0812_ = ~ iseq_q[0];
+ assign _0813_ = _0811_ & _0812_;
+ assign _0814_ = ~ icapture_q;
+ assign _0815_ = _0813_ & _0814_;
+ assign _0816_ = _0807_ | _0815_;
+ assign _0817_ = ~ iseq_q[2];
+ assign _0818_ = iseq_q[3] & _0817_;
+ assign _0819_ = ~ iseq_q[1];
+ assign _0820_ = _0818_ & _0819_;
+ assign _0821_ = ~ iseq_q[0];
+ assign _0822_ = _0820_ & _0821_;
+ assign _0823_ = _0822_ & icapture_q;
+ assign _0824_ = ~ rd_rsp_data_done;
+ assign _0825_ = _0823_ & _0824_;
+ assign _0826_ = _0816_ | _0825_;
+ assign _0827_ = ~ iseq_q[2];
+ assign _0828_ = iseq_q[3] & _0827_;
+ assign _0829_ = ~ iseq_q[1];
+ assign _0830_ = _0828_ & _0829_;
+ assign _0831_ = ~ iseq_q[0];
+ assign _0832_ = _0830_ & _0831_;
+ assign _0833_ = _0832_ & icapture_q;
+ assign _0834_ = _0833_ & rd_rsp_data_done;
+ assign _0835_ = _0826_ | _0834_;
+ assign _0836_ = ~ iseq_q[3];
+ assign _0837_ = ~ iseq_q[2];
+ assign _0838_ = _0836_ & _0837_;
+ assign _0839_ = ~ iseq_q[1];
+ assign _0840_ = _0838_ & _0839_;
+ assign _0841_ = _0840_ & iseq_q[0];
+ assign _0842_ = _0835_ | _0841_;
+ assign _0843_ = ~ iseq_q[3];
+ assign _0844_ = ~ iseq_q[2];
+ assign _0845_ = _0843_ & _0844_;
+ assign _0846_ = _0845_ & iseq_q[1];
+ assign _0847_ = ~ iseq_q[0];
+ assign _0848_ = _0846_ & _0847_;
+ assign _0849_ = _0842_ | _0848_;
+ assign _0850_ = ~ iseq_q[3];
+ assign _0851_ = _0850_ & iseq_q[2];
+ assign _0852_ = _0851_ & iseq_q[1];
+ assign _0853_ = _0852_ & iseq_q[0];
+ assign _0854_ = _0853_ & icapture_q;
+ assign _0855_ = _0854_ & idle_header;
+ assign _0856_ = _0849_ | _0855_;
+ assign _0857_ = ~ iseq_q[2];
+ assign _0858_ = iseq_q[3] & _0857_;
+ assign _0859_ = ~ iseq_q[1];
+ assign _0860_ = _0858_ & _0859_;
+ assign _0861_ = _0860_ & iseq_q[0];
+ assign _0862_ = _0856_ | _0861_;
+ assign _0863_ = ~ iseq_q[2];
+ assign _0864_ = iseq_q[3] & _0863_;
+ assign _0865_ = _0864_ & iseq_q[1];
+ assign _0866_ = ~ iseq_q[0];
+ assign _0867_ = _0865_ & _0866_;
+ assign _0868_ = _0862_ | _0867_;
+ assign _0869_ = ~ iseq_q[2];
+ assign _0870_ = iseq_q[3] & _0869_;
+ assign _0871_ = _0870_ & iseq_q[1];
+ assign _0872_ = _0871_ & iseq_q[0];
+ assign _0873_ = _0868_ | _0872_;
+ assign _0874_ = iseq_q[3] & iseq_q[2];
+ assign _0875_ = ~ iseq_q[1];
+ assign _0876_ = _0874_ & _0875_;
+ assign _0877_ = ~ iseq_q[0];
+ assign _0878_ = _0876_ & _0877_;
+ assign _0879_ = _0873_ | _0878_;
+ assign _0880_ = iseq_q[3] & iseq_q[2];
+ assign _0881_ = ~ iseq_q[1];
+ assign _0882_ = _0880_ & _0881_;
+ assign _0883_ = _0882_ & iseq_q[0];
+ assign _0884_ = _0879_ | _0883_;
+ assign _0885_ = iseq_q[3] & iseq_q[2];
+ assign _0886_ = _0885_ & iseq_q[1];
+ assign _0887_ = ~ iseq_q[0];
+ assign _0888_ = _0886_ & _0887_;
+ assign _0889_ = _0884_ | _0888_;
+ assign _0890_ = iseq_q[3] & iseq_q[2];
+ assign _0891_ = _0890_ & iseq_q[1];
+ assign _0892_ = _0891_ & iseq_q[0];
+ assign _0893_ = ~ icapture_q;
+ assign _0894_ = _0892_ & _0893_;
+ assign _0895_ = iseq_q[3] & iseq_q[2];
+ assign _0896_ = _0895_ & iseq_q[1];
+ assign _0897_ = _0896_ & iseq_q[0];
+ assign _0898_ = _0897_ & icapture_q;
+ assign _0899_ = _0898_ & idle_header;
+ assign _0900_ = _0894_ | _0899_;
+ assign _0901_ = iseq_q[3] & iseq_q[2];
+ assign _0902_ = _0901_ & iseq_q[1];
+ assign _0903_ = _0902_ & iseq_q[0];
+ assign _0904_ = _0903_ & icapture_q;
+ assign _0905_ = _0904_ & bad_header;
+ assign _0906_ = _0900_ | _0905_;
+ assign _0907_ = iseq_q[3] & iseq_q[2];
+ assign _0908_ = _0907_ & iseq_q[1];
+ assign _0909_ = _0908_ & iseq_q[0];
+ assign _0910_ = _0909_ & icapture_q;
+ assign _0911_ = _0910_ & sync_ack;
+ assign _0912_ = _0906_ | _0911_;
+ assign _0913_ = iseq_q[3] & iseq_q[2];
+ assign _0914_ = _0913_ & iseq_q[1];
+ assign _0915_ = _0914_ & iseq_q[0];
+ assign _0916_ = _0915_ & icapture_q;
+ assign _0917_ = _0916_ & cache_inv;
+ assign _0918_ = _0912_ | _0917_;
+ assign _0919_ = iseq_q[3] & iseq_q[2];
+ assign _0920_ = _0919_ & iseq_q[1];
+ assign _0921_ = _0920_ & iseq_q[0];
+ assign _0922_ = _0921_ & icapture_q;
+ assign _0923_ = _0922_ & link_req_i;
+ assign _0924_ = _0918_ | _0923_;
+ assign _0925_ = iseq_q[3] & iseq_q[2];
+ assign _0926_ = _0925_ & iseq_q[1];
+ assign _0927_ = _0926_ & iseq_q[0];
+ assign _0928_ = _0927_ & icapture_q;
+ assign _0929_ = _0928_ & link_rsp_i;
+ assign _0930_ = _0924_ | _0929_;
+ assign _0931_ = ~ iseq_q[2];
+ assign _0932_ = iseq_q[3] & _0931_;
+ assign _0933_ = ~ iseq_q[1];
+ assign _0934_ = _0932_ & _0933_;
+ assign _0935_ = ~ iseq_q[0];
+ assign _0936_ = _0934_ & _0935_;
+ assign _0937_ = _0936_ & icapture_q;
+ assign _0938_ = _0937_ & rd_rsp_data_done;
+ assign _0939_ = _0930_ | _0938_;
+ assign _0940_ = ~ iseq_q[3];
+ assign _0941_ = ~ iseq_q[2];
+ assign _0942_ = _0940_ & _0941_;
+ assign _0943_ = ~ iseq_q[1];
+ assign _0944_ = _0942_ & _0943_;
+ assign _0945_ = _0944_ & iseq_q[0];
+ assign _0946_ = _0939_ | _0945_;
+ assign _0947_ = ~ iseq_q[3];
+ assign _0948_ = ~ iseq_q[2];
+ assign _0949_ = _0947_ & _0948_;
+ assign _0950_ = _0949_ & iseq_q[1];
+ assign _0951_ = ~ iseq_q[0];
+ assign _0952_ = _0950_ & _0951_;
+ assign _0953_ = _0946_ | _0952_;
+ assign _0954_ = ~ iseq_q[3];
+ assign _0955_ = _0954_ & iseq_q[2];
+ assign _0956_ = _0955_ & iseq_q[1];
+ assign _0957_ = ~ iseq_q[0];
+ assign _0958_ = _0956_ & _0957_;
+ assign _0959_ = _0953_ | _0958_;
+ assign _0960_ = ~ iseq_q[3];
+ assign _0961_ = _0960_ & iseq_q[2];
+ assign _0962_ = _0961_ & iseq_q[1];
+ assign _0963_ = _0962_ & iseq_q[0];
+ assign _0964_ = ~ icapture_q;
+ assign _0965_ = _0963_ & _0964_;
+ assign _0966_ = _0959_ | _0965_;
+ assign _0967_ = ~ iseq_q[3];
+ assign _0968_ = _0967_ & iseq_q[2];
+ assign _0969_ = _0968_ & iseq_q[1];
+ assign _0970_ = _0969_ & iseq_q[0];
+ assign _0971_ = _0970_ & icapture_q;
+ assign _0972_ = _0971_ & idle_header;
+ assign _0973_ = _0966_ | _0972_;
+ assign _0974_ = ~ iseq_q[3];
+ assign _0975_ = _0974_ & iseq_q[2];
+ assign _0976_ = _0975_ & iseq_q[1];
+ assign _0977_ = _0976_ & iseq_q[0];
+ assign _0978_ = _0977_ & icapture_q;
+ assign _0979_ = ~ idle_header;
+ assign _0980_ = _0978_ & _0979_;
+ assign _0981_ = _0973_ | _0980_;
+ assign _0982_ = ~ iseq_q[3];
+ assign _0983_ = _0982_ & iseq_q[2];
+ assign _0984_ = ~ iseq_q[1];
+ assign _0985_ = _0983_ & _0984_;
+ assign _0986_ = ~ iseq_q[0];
+ assign _0987_ = _0985_ & _0986_;
+ assign _0988_ = _0981_ | _0987_;
+ assign _0989_ = ~ iseq_q[3];
+ assign _0990_ = _0989_ & iseq_q[2];
+ assign _0991_ = ~ iseq_q[1];
+ assign _0992_ = _0990_ & _0991_;
+ assign _0993_ = _0992_ & iseq_q[0];
+ assign _0994_ = _0988_ | _0993_;
+ assign _0995_ = iseq_q[3] & iseq_q[2];
+ assign _0996_ = ~ iseq_q[1];
+ assign _0997_ = _0995_ & _0996_;
+ assign _0998_ = ~ iseq_q[0];
+ assign _0999_ = _0997_ & _0998_;
+ assign _1000_ = _0994_ | _0999_;
+ assign _1001_ = iseq_q[3] & iseq_q[2];
+ assign _1002_ = ~ iseq_q[1];
+ assign _1003_ = _1001_ & _1002_;
+ assign _1004_ = _1003_ & iseq_q[0];
+ assign _1005_ = _1000_ | _1004_;
+ assign _1006_ = iseq_q[3] & iseq_q[2];
+ assign _1007_ = _1006_ & iseq_q[1];
+ assign _1008_ = ~ iseq_q[0];
+ assign _1009_ = _1007_ & _1008_;
+ assign _1010_ = _1005_ | _1009_;
+ assign _1011_ = iseq_q[3] & iseq_q[2];
+ assign _1012_ = _1011_ & iseq_q[1];
+ assign _1013_ = _1012_ & iseq_q[0];
+ assign _1014_ = ~ icapture_q;
+ assign _1015_ = _1013_ & _1014_;
+ assign _1016_ = iseq_q[3] & iseq_q[2];
+ assign _1017_ = _1016_ & iseq_q[1];
+ assign _1018_ = _1017_ & iseq_q[0];
+ assign _1019_ = _1018_ & icapture_q;
+ assign _1020_ = _1019_ & idle_header;
+ assign _1021_ = _1015_ | _1020_;
+ assign _1022_ = iseq_q[3] & iseq_q[2];
+ assign _1023_ = _1022_ & iseq_q[1];
+ assign _1024_ = _1023_ & iseq_q[0];
+ assign _1025_ = _1024_ & icapture_q;
+ assign _1026_ = _1025_ & bad_header;
+ assign _1027_ = _1021_ | _1026_;
+ assign _1028_ = iseq_q[3] & iseq_q[2];
+ assign _1029_ = _1028_ & iseq_q[1];
+ assign _1030_ = _1029_ & iseq_q[0];
+ assign _1031_ = _1030_ & icapture_q;
+ assign _1032_ = _1031_ & int_req;
+ assign _1033_ = _1027_ | _1032_;
+ assign _1034_ = iseq_q[3] & iseq_q[2];
+ assign _1035_ = _1034_ & iseq_q[1];
+ assign _1036_ = _1035_ & iseq_q[0];
+ assign _1037_ = _1036_ & icapture_q;
+ assign _1038_ = _1037_ & sync_ack;
+ assign _1039_ = _1033_ | _1038_;
+ assign _1040_ = iseq_q[3] & iseq_q[2];
+ assign _1041_ = _1040_ & iseq_q[1];
+ assign _1042_ = _1041_ & iseq_q[0];
+ assign _1043_ = _1042_ & icapture_q;
+ assign _1044_ = _1043_ & cache_inv;
+ assign _1045_ = _1039_ | _1044_;
+ assign _1046_ = iseq_q[3] & iseq_q[2];
+ assign _1047_ = _1046_ & iseq_q[1];
+ assign _1048_ = _1047_ & iseq_q[0];
+ assign _1049_ = _1048_ & icapture_q;
+ assign _1050_ = _1049_ & link_req_i;
+ assign _1051_ = _1045_ | _1050_;
+ assign _1052_ = iseq_q[3] & iseq_q[2];
+ assign _1053_ = _1052_ & iseq_q[1];
+ assign _1054_ = _1053_ & iseq_q[0];
+ assign _1055_ = _1054_ & icapture_q;
+ assign _1056_ = _1055_ & link_rsp_i;
+ assign _1057_ = _1051_ | _1056_;
+ assign _1058_ = ~ iseq_q[2];
+ assign _1059_ = iseq_q[3] & _1058_;
+ assign _1060_ = ~ iseq_q[1];
+ assign _1061_ = _1059_ & _1060_;
+ assign _1062_ = ~ iseq_q[0];
+ assign _1063_ = _1061_ & _1062_;
+ assign _1064_ = _1063_ & icapture_q;
+ assign _1065_ = _1064_ & rd_rsp_data_done;
+ assign _1066_ = _1057_ | _1065_;
+ assign _1067_ = ~ iseq_q[3];
+ assign _1068_ = ~ iseq_q[2];
+ assign _1069_ = _1067_ & _1068_;
+ assign _1070_ = ~ iseq_q[1];
+ assign _1071_ = _1069_ & _1070_;
+ assign _1072_ = _1071_ & iseq_q[0];
+ assign _1073_ = _1066_ | _1072_;
+ assign _1074_ = ~ iseq_q[3];
+ assign _1075_ = ~ iseq_q[2];
+ assign _1076_ = _1074_ & _1075_;
+ assign _1077_ = _1076_ & iseq_q[1];
+ assign _1078_ = ~ iseq_q[0];
+ assign _1079_ = _1077_ & _1078_;
+ assign _1080_ = _1073_ | _1079_;
+ assign _1081_ = ~ iseq_q[3];
+ assign _1082_ = _1081_ & iseq_q[2];
+ assign _1083_ = _1082_ & iseq_q[1];
+ assign _1084_ = ~ iseq_q[0];
+ assign _1085_ = _1083_ & _1084_;
+ assign _1086_ = _1080_ | _1085_;
+ assign _1087_ = ~ iseq_q[3];
+ assign _1088_ = _1087_ & iseq_q[2];
+ assign _1089_ = _1088_ & iseq_q[1];
+ assign _1090_ = _1089_ & iseq_q[0];
+ assign _1091_ = ~ icapture_q;
+ assign _1092_ = _1090_ & _1091_;
+ assign _1093_ = _1086_ | _1092_;
+ assign _1094_ = ~ iseq_q[3];
+ assign _1095_ = _1094_ & iseq_q[2];
+ assign _1096_ = _1095_ & iseq_q[1];
+ assign _1097_ = _1096_ & iseq_q[0];
+ assign _1098_ = _1097_ & icapture_q;
+ assign _1099_ = _1098_ & idle_header;
+ assign _1100_ = _1093_ | _1099_;
+ assign _1101_ = ~ iseq_q[3];
+ assign _1102_ = _1101_ & iseq_q[2];
+ assign _1103_ = _1102_ & iseq_q[1];
+ assign _1104_ = _1103_ & iseq_q[0];
+ assign _1105_ = _1104_ & icapture_q;
+ assign _1106_ = ~ idle_header;
+ assign _1107_ = _1105_ & _1106_;
+ assign _1108_ = _1100_ | _1107_;
+ assign _1109_ = ~ iseq_q[3];
+ assign _1110_ = ~ iseq_q[2];
+ assign _1111_ = _1109_ & _1110_;
+ assign _1112_ = _1111_ & iseq_q[1];
+ assign _1113_ = _1112_ & iseq_q[0];
+ assign _1114_ = _1108_ | _1113_;
+ assign _1115_ = ~ iseq_q[2];
+ assign _1116_ = iseq_q[3] & _1115_;
+ assign _1117_ = _1116_ & iseq_q[1];
+ assign _1118_ = ~ iseq_q[0];
+ assign _1119_ = _1117_ & _1118_;
+ assign _1120_ = _1114_ | _1119_;
+ assign _1121_ = ~ iseq_q[2];
+ assign _1122_ = iseq_q[3] & _1121_;
+ assign _1123_ = _1122_ & iseq_q[1];
+ assign _1124_ = _1123_ & iseq_q[0];
+ assign _1125_ = _1120_ | _1124_;
+ assign _1126_ = iseq_q[3] & iseq_q[2];
+ assign _1127_ = _1126_ & iseq_q[1];
+ assign _1128_ = ~ iseq_q[0];
+ assign _1129_ = _1127_ & _1128_;
+ assign _1130_ = _1125_ | _1129_;
+ assign _1131_ = iseq_q[3] & iseq_q[2];
+ assign _1132_ = _1131_ & iseq_q[1];
+ assign _1133_ = _1132_ & iseq_q[0];
+ assign _1134_ = ~ icapture_q;
+ assign _1135_ = _1133_ & _1134_;
+ assign _1136_ = iseq_q[3] & iseq_q[2];
+ assign _1137_ = _1136_ & iseq_q[1];
+ assign _1138_ = _1137_ & iseq_q[0];
+ assign _1139_ = _1138_ & icapture_q;
+ assign _1140_ = _1139_ & idle_header;
+ assign _1141_ = _1135_ | _1140_;
+ assign _1142_ = iseq_q[3] & iseq_q[2];
+ assign _1143_ = _1142_ & iseq_q[1];
+ assign _1144_ = _1143_ & iseq_q[0];
+ assign _1145_ = _1144_ & icapture_q;
+ assign _1146_ = _1145_ & wr8_rsp;
+ assign _1147_ = _1141_ | _1146_;
+ assign _1148_ = ~ iseq_q[2];
+ assign _1149_ = iseq_q[3] & _1148_;
+ assign _1150_ = ~ iseq_q[1];
+ assign _1151_ = _1149_ & _1150_;
+ assign _1152_ = ~ iseq_q[0];
+ assign _1153_ = _1151_ & _1152_;
+ assign _1154_ = _1153_ & icapture_q;
+ assign _1155_ = _1154_ & rd_rsp_data_done;
+ assign _1156_ = _1147_ | _1155_;
+ assign _1157_ = ~ iseq_q[3];
+ assign _1158_ = ~ iseq_q[2];
+ assign _1159_ = _1157_ & _1158_;
+ assign _1160_ = ~ iseq_q[1];
+ assign _1161_ = _1159_ & _1160_;
+ assign _1162_ = _1161_ & iseq_q[0];
+ assign _1163_ = _1156_ | _1162_;
+ assign _1164_ = ~ iseq_q[3];
+ assign _1165_ = ~ iseq_q[2];
+ assign _1166_ = _1164_ & _1165_;
+ assign _1167_ = _1166_ & iseq_q[1];
+ assign _1168_ = ~ iseq_q[0];
+ assign _1169_ = _1167_ & _1168_;
+ assign _1170_ = _1163_ | _1169_;
+ assign _1171_ = ~ iseq_q[3];
+ assign _1172_ = _1171_ & iseq_q[2];
+ assign _1173_ = _1172_ & iseq_q[1];
+ assign _1174_ = ~ iseq_q[0];
+ assign _1175_ = _1173_ & _1174_;
+ assign _1176_ = _1170_ | _1175_;
+ assign _1177_ = ~ iseq_q[3];
+ assign _1178_ = _1177_ & iseq_q[2];
+ assign _1179_ = _1178_ & iseq_q[1];
+ assign _1180_ = _1179_ & iseq_q[0];
+ assign _1181_ = _1180_ & icapture_q;
+ assign _1182_ = _1181_ & idle_header;
+ assign _1183_ = _1176_ | _1182_;
+ assign _1184_ = ~ iseq_q[3];
+ assign _1185_ = ~ iseq_q[2];
+ assign _1186_ = _1184_ & _1185_;
+ assign _1187_ = _1186_ & iseq_q[1];
+ assign _1188_ = _1187_ & iseq_q[0];
+ assign _1189_ = _1183_ | _1188_;
+ assign _1190_ = ~ iseq_q[3];
+ assign _1191_ = _1190_ & iseq_q[2];
+ assign _1192_ = ~ iseq_q[1];
+ assign _1193_ = _1191_ & _1192_;
+ assign _1194_ = _1193_ & iseq_q[0];
+ assign _1195_ = _1189_ | _1194_;
+ assign _1196_ = ~ iseq_q[2];
+ assign _1197_ = iseq_q[3] & _1196_;
+ assign _1198_ = ~ iseq_q[1];
+ assign _1199_ = _1197_ & _1198_;
+ assign _1200_ = _1199_ & iseq_q[0];
+ assign _1201_ = _1195_ | _1200_;
+ assign _1202_ = ~ iseq_q[2];
+ assign _1203_ = iseq_q[3] & _1202_;
+ assign _1204_ = _1203_ & iseq_q[1];
+ assign _1205_ = _1204_ & iseq_q[0];
+ assign _1206_ = _1201_ | _1205_;
+ assign _1207_ = iseq_q[3] & iseq_q[2];
+ assign _1208_ = ~ iseq_q[1];
+ assign _1209_ = _1207_ & _1208_;
+ assign _1210_ = _1209_ & iseq_q[0];
+ assign _1211_ = _1206_ | _1210_;
+ assign _1212_ = ~ iseq_q[2];
+ assign _1213_ = iseq_q[3] & _1212_;
+ assign _1214_ = ~ iseq_q[1];
+ assign _1215_ = _1213_ & _1214_;
+ assign _1216_ = ~ iseq_q[0];
+ assign _1217_ = _1215_ & _1216_;
+ assign _1218_ = _1217_ & icapture_q;
+ assign _1219_ = ~ rd_rsp_data_done;
+ assign _1220_ = _1218_ & _1219_;
+ assign _1221_ = ~ iseq_q[2];
+ assign _1222_ = iseq_q[3] & _1221_;
+ assign _1223_ = ~ iseq_q[1];
+ assign _1224_ = _1222_ & _1223_;
+ assign _1225_ = ~ iseq_q[0];
+ assign _1226_ = _1224_ & _1225_;
+ assign _1227_ = _1226_ & icapture_q;
+ assign _1228_ = _1227_ & rd_rsp_data_done;
+ assign ld_rd_data = _1220_ | _1228_;
+ assign _1229_ = ~ iseq_q[2];
+ assign _1230_ = iseq_q[3] & _1229_;
+ assign _1231_ = ~ iseq_q[1];
+ assign _1232_ = _1230_ & _1231_;
+ assign _1233_ = ~ iseq_q[0];
+ assign _1234_ = _1232_ & _1233_;
+ assign _1235_ = _1234_ & icapture_q;
+ assign rd_rsp_complete = _1235_ & rd_rsp_data_done;
+ assign _1236_ = ~ iseq_q[3];
+ assign _1237_ = ~ iseq_q[2];
+ assign _1238_ = _1236_ & _1237_;
+ assign _1239_ = ~ iseq_q[1];
+ assign _1240_ = _1238_ & _1239_;
+ assign wr_rsp_complete = _1240_ & iseq_q[0];
+ assign _1241_ = ~ iseq_q[3];
+ assign _1242_ = ~ iseq_q[2];
+ assign _1243_ = _1241_ & _1242_;
+ assign _1244_ = _1243_ & iseq_q[1];
+ assign _1245_ = ~ iseq_q[0];
+ assign int_req_complete = _1244_ & _1245_;
+ assign _1246_ = iseq_q[3] & iseq_q[2];
+ assign _1247_ = _1246_ & iseq_q[1];
+ assign _1248_ = _1247_ & iseq_q[0];
+ assign _1249_ = ~ icapture_q;
+ assign _1250_ = _1248_ & _1249_;
+ assign _1251_ = iseq_q[3] & iseq_q[2];
+ assign _1252_ = _1251_ & iseq_q[1];
+ assign _1253_ = _1252_ & iseq_q[0];
+ assign _1254_ = _1253_ & icapture_q;
+ assign _1255_ = _1254_ & idle_header;
+ assign idata_clear = _1250_ | _1255_;
+ assign _1256_ = ~ iseq_q[3];
+ assign _1257_ = ~ iseq_q[2];
+ assign _1258_ = _1256_ & _1257_;
+ assign _1259_ = _1258_ & iseq_q[1];
+ assign _1260_ = ~ iseq_q[0];
+ assign _1261_ = _1259_ & _1260_;
+ assign _1262_ = ~ iseq_q[3];
+ assign _1263_ = _1262_ & iseq_q[2];
+ assign _1264_ = _1263_ & iseq_q[1];
+ assign _1265_ = ~ iseq_q[0];
+ assign _1266_ = _1264_ & _1265_;
+ assign save_header = _1261_ | _1266_;
+ assign _1267_ = iseq_q[3] & iseq_q[2];
+ assign _1268_ = _1267_ & iseq_q[1];
+ assign iseq_idle = _1268_ & iseq_q[0];
+ assign _1269_ = ~ iseq_q[3];
+ assign _1270_ = ~ iseq_q[2];
+ assign _1271_ = _1269_ & _1270_;
+ assign _1272_ = ~ iseq_q[1];
+ assign _1273_ = _1271_ & _1272_;
+ assign _1274_ = ~ iseq_q[0];
+ assign _1275_ = _1273_ & _1274_;
+ assign _1276_ = ~ iseq_q[3];
+ assign _1277_ = ~ iseq_q[2];
+ assign _1278_ = _1276_ & _1277_;
+ assign _1279_ = _1278_ & iseq_q[1];
+ assign _1280_ = _1279_ & iseq_q[0];
+ assign _1281_ = _1275_ | _1280_;
+ assign _1282_ = ~ iseq_q[3];
+ assign _1283_ = _1282_ & iseq_q[2];
+ assign _1284_ = ~ iseq_q[1];
+ assign _1285_ = _1283_ & _1284_;
+ assign _1286_ = ~ iseq_q[0];
+ assign _1287_ = _1285_ & _1286_;
+ assign _1288_ = _1281_ | _1287_;
+ assign _1289_ = ~ iseq_q[3];
+ assign _1290_ = _1289_ & iseq_q[2];
+ assign _1291_ = ~ iseq_q[1];
+ assign _1292_ = _1290_ & _1291_;
+ assign _1293_ = _1292_ & iseq_q[0];
+ assign _1294_ = _1288_ | _1293_;
+ assign _1295_ = ~ iseq_q[2];
+ assign _1296_ = iseq_q[3] & _1295_;
+ assign _1297_ = ~ iseq_q[1];
+ assign _1298_ = _1296_ & _1297_;
+ assign _1299_ = _1298_ & iseq_q[0];
+ assign _1300_ = _1294_ | _1299_;
+ assign _1301_ = ~ iseq_q[2];
+ assign _1302_ = iseq_q[3] & _1301_;
+ assign _1303_ = _1302_ & iseq_q[1];
+ assign _1304_ = ~ iseq_q[0];
+ assign _1305_ = _1303_ & _1304_;
+ assign _1306_ = _1300_ | _1305_;
+ assign _1307_ = ~ iseq_q[2];
+ assign _1308_ = iseq_q[3] & _1307_;
+ assign _1309_ = _1308_ & iseq_q[1];
+ assign _1310_ = _1309_ & iseq_q[0];
+ assign _1311_ = _1306_ | _1310_;
+ assign _1312_ = iseq_q[3] & iseq_q[2];
+ assign _1313_ = ~ iseq_q[1];
+ assign _1314_ = _1312_ & _1313_;
+ assign _1315_ = ~ iseq_q[0];
+ assign _1316_ = _1314_ & _1315_;
+ assign _1317_ = _1311_ | _1316_;
+ assign _1318_ = iseq_q[3] & iseq_q[2];
+ assign _1319_ = ~ iseq_q[1];
+ assign _1320_ = _1318_ & _1319_;
+ assign _1321_ = _1320_ & iseq_q[0];
+ assign _1322_ = _1317_ | _1321_;
+ assign _1323_ = iseq_q[3] & iseq_q[2];
+ assign _1324_ = _1323_ & iseq_q[1];
+ assign _1325_ = ~ iseq_q[0];
+ assign _1326_ = _1324_ & _1325_;
+ assign iseq_err = _1322_ | _1326_;
+ assign _1327_ = config_q[63] | config_q[62];
+ assign _1328_ = _1327_ | config_q[61];
+ assign _1329_ = _1328_ | config_q[60];
+ assign _1330_ = _1329_ | config_q[59];
+ assign _1331_ = _1330_ | config_q[58];
+ assign _1332_ = _1331_ | config_q[57];
+ assign _1333_ = _1332_ | config_q[56];
+ assign _1334_ = rst ? 64'h000000001fffc463 : { _1384_, _1379_, _1378_, _1377_, _1376_, _1373_, _1375_, _1372_, _1371_, _1370_, _1369_, _1368_, _1367_, _1366_ };
+ assign _1335_ = rst ? 4'hf : { _1722_, _1817_, _1892_, _1963_ };
+ assign _1336_ = rst ? 107'h000000000000000000000000000 : { _1358_, _1355_, _1352_, _1361_, _1360_, _1359_ };
+ assign _1337_ = rst ? 66'h00000000000000000 : { _0079_, _0106_, _1520_ };
+ assign _1338_ = rst ? 1'h0 : oclk_d;
+ assign _1339_ = rst ? 1'h0 : oclk_last_d;
+ assign _1340_ = rst ? 8'h00 : odata_d;
+ assign _1341_ = rst ? 1'h1 : opty_d;
+ assign _1342_ = rst ? 4'hf : { _0248_, _0347_, _0469_, _0579_ };
+ assign _1343_ = rst ? 16'h0000 : oclk_cnt_d;
+ assign _1344_ = rst ? 3'h0 : odata_cnt_d;
+ assign _1345_ = rst ? 8'h00 : idata_d;
+ assign _1346_ = rst ? 1'h1 : ipty_d;
+ assign _1347_ = rst ? 4'hf : { _0889_, _1010_, _1130_, _1211_ };
+ assign _1348_ = rst ? 1'h0 : icapture_d;
+ assign _1349_ = rst ? 3'h0 : idata_cnt_d;
+ always @(posedge clk)
+ config_q <= _1334_;
+ always @(posedge clk)
+ wbseq_q <= _1335_;
+ always @(posedge clk)
+ wb_in_q <= _1336_;
+ always @(posedge clk)
+ wb_out_q <= _1337_;
+ always @(posedge clk)
+ oclk_q <= _1338_;
+ always @(posedge clk)
+ oclk_last_q <= _1339_;
+ always @(posedge clk)
+ odata_q <= _1340_;
+ always @(posedge clk)
+ opty_q <= _1341_;
+ always @(posedge clk)
+ oseq_q <= _1342_;
+ always @(posedge clk)
+ oclk_cnt_q <= _1343_;
+ always @(posedge clk)
+ odata_cnt_q <= _1344_;
+ always @(posedge clk)
+ idata_q <= _1345_;
+ always @(posedge clk)
+ ipty_q <= _1346_;
+ always @(posedge clk)
+ iseq_q <= _1347_;
+ always @(posedge clk)
+ icapture_q <= _1348_;
+ always @(posedge clk)
+ idata_cnt_q <= _1349_;
+ assign _1350_ = wb_cyc & wb_stb;
+ assign _1351_ = ~ wb_out_q[65];
+ assign wb_req = _1350_ & _1351_;
+ assign _1352_ = wb_req ? 1'h1 : _1354_;
+ assign _1353_ = ~ wb_out_q[64];
+ assign _1354_ = wb_in_q[104] & _1353_;
+ assign _1355_ = wb_req ? 1'h1 : _1357_;
+ assign _1356_ = ~ wb_out_q[64];
+ assign _1357_ = wb_in_q[105] & _1356_;
+ assign _1358_ = wb_req ? wb_we : wb_in_q[106];
+ assign _1359_ = wb_req ? wb_addr : wb_in_q[31:0];
+ assign _1360_ = wb_req ? wb_wr_data : wb_in_q[95:32];
+ assign _1361_ = wb_req ? wb_sel : wb_in_q[103:96];
+ assign _1362_ = wb_addr[31:16] == config_q[31:16];
+ assign _1363_ = _1362_ ? 1'h1 : 1'h0;
+ assign wb_local = config_q[14] & _1363_;
+ assign _1364_ = wb_addr[15:0] == 16'h0000;
+ assign _1365_ = _1364_ ? 1'h1 : 1'h0;
+ assign config_write = wb_local_wr & _1365_;
+ assign _1366_ = config_write ? _1360_[63] : config_q[0];
+ assign _1367_ = config_write ? _1360_[62:59] : config_q[4:1];
+ assign _1368_ = config_write ? _1360_[58:56] : config_q[7:5];
+ assign _1369_ = config_write ? _1360_[55] : config_q[8];
+ assign _1370_ = config_write ? _1360_[54] : config_q[9];
+ assign _1371_ = config_write ? _1360_[50] : config_q[10];
+ assign _1372_ = config_write ? _1360_[53:51] : config_q[13:11];
+ assign _1373_ = config_write ? _1360_[49] : _1374_;
+ assign _1374_ = config_q[15] | int_req_complete;
+ assign _1375_ = config_write ? _1360_[48] : config_q[14];
+ assign _1376_ = config_write ? _1360_[47:32] : config_q[31:16];
+ assign _1377_ = config_write ? _1360_[31:24] : config_q[39:32];
+ assign _1378_ = config_write ? _1360_[23:16] : config_q[47:40];
+ assign _1379_ = config_write ? _1360_[15:8] : _1383_;
+ assign _1380_ = save_header ? idata_q : 8'h00;
+ assign _1381_ = ~ save_header;
+ assign _1382_ = _1381_ ? config_q[55:48] : 8'h00;
+ assign _1383_ = _1380_ | _1382_;
+ assign _1384_ = config_write ? _1360_[7:0] : { _1385_, _1386_, _1387_, _1388_, _1389_, _1390_, _1391_, config_q[56] };
+ assign _1385_ = config_q[63] | wbseq_err;
+ assign _1386_ = config_q[62] | oseq_err;
+ assign _1387_ = config_q[61] | iseq_err;
+ assign _1388_ = config_q[60] | rd_err;
+ assign _1389_ = config_q[59] | wr_err;
+ assign _1390_ = config_q[58] | pty_err;
+ assign _1391_ = config_q[57] | bad_header;
+ assign _1392_ = config_q[4:1] == 4'h0;
+ assign _1393_ = config_q[4:1] == 4'h1;
+ assign _1394_ = config_q[4:1] == 4'h2;
+ assign _1395_ = config_q[4:1] == 4'h3;
+ assign _1396_ = config_q[4:1] == 4'h4;
+ assign _1397_ = config_q[4:1] == 4'h5;
+ assign _1398_ = config_q[4:1] == 4'h6;
+ assign _1399_ = config_q[4:1] == 4'h7;
+ assign _1400_ = config_q[4:1] == 4'h8;
+ assign _1401_ = config_q[4:1] == 4'h9;
+ function [15:0] \993 ;
+ input [15:0] a;
+ input [159:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \993 = b[15:0];
+ 10'b????????1?:
+ \993 = b[31:16];
+ 10'b???????1??:
+ \993 = b[47:32];
+ 10'b??????1???:
+ \993 = b[63:48];
+ 10'b?????1????:
+ \993 = b[79:64];
+ 10'b????1?????:
+ \993 = b[95:80];
+ 10'b???1??????:
+ \993 = b[111:96];
+ 10'b??1???????:
+ \993 = b[127:112];
+ 10'b?1????????:
+ \993 = b[143:128];
+ 10'b1?????????:
+ \993 = b[159:144];
+ default:
+ \993 = a;
+ endcase
+ endfunction
+ assign oclk_toggle = \993 (16'h0200, 160'h0100008000400020001000080004000200010000, { _1401_, _1400_, _1399_, _1398_, _1397_, _1396_, _1395_, _1394_, _1393_, _1392_ });
+ assign wb_ack = wb_out_q[64];
+ assign wb_err = 1'h0;
+ assign wb_stall = wb_out_q[65];
+ assign wb_rd_data = wb_out_q[63:0];
+ assign oib_clk = oclk_q;
+ assign ob_data = odata_q;
+ assign ob_pty = opty_q;
+ assign err = _1333_;
+ assign \int = config_q[15];
+endmodule
+
+module mmu(clk, rst, l_in, d_in, l_out, d_out, i_out);
+ wire [63:0] _000_;
+ wire _001_;
+ wire [67:0] _002_;
+ wire [63:0] _003_;
+ wire [31:0] _004_;
+ wire [3:0] _005_;
+ wire [65:0] _006_;
+ wire _007_;
+ wire [63:0] _008_;
+ wire _009_;
+ wire [135:0] _010_;
+ wire _011_;
+ wire _012_;
+ wire [30:0] _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire [18:0] _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire [63:0] _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire [3:0] _145_;
+ wire _146_;
+ wire [3:0] _147_;
+ wire [5:0] _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire [3:0] _152_;
+ wire _153_;
+ wire _154_;
+ wire [5:0] _155_;
+ wire _156_;
+ wire [3:0] _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire [63:0] _161_;
+ wire [31:0] _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire [100:0] _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire [67:0] _170_;
+ wire [5:0] _171_;
+ wire _172_;
+ wire _173_;
+ wire [3:0] _174_;
+ wire _175_;
+ wire _176_;
+ wire [64:0] _177_;
+ wire [64:0] _178_;
+ wire _179_;
+ wire [3:0] _180_;
+ wire _181_;
+ wire [3:0] _182_;
+ wire [196:0] _183_;
+ wire _184_;
+ wire [3:0] _185_;
+ wire _186_;
+ wire _187_;
+ wire [5:0] _188_;
+ wire [5:0] _189_;
+ wire [30:0] _190_;
+ wire [30:0] _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire [5:0] _198_;
+ wire _199_;
+ wire _200_;
+ wire [3:0] _201_;
+ wire _202_;
+ wire [3:0] _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire [3:0] _223_;
+ wire [1:0] _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire [5:0] _230_;
+ wire [3:0] _231_;
+ wire [66:0] _232_;
+ wire _233_;
+ wire [3:0] _234_;
+ wire [66:0] _235_;
+ wire _236_;
+ wire [1:0] _237_;
+ wire [3:0] _238_;
+ wire [66:0] _239_;
+ wire _240_;
+ wire _241_;
+ wire [1:0] _242_;
+ wire [3:0] _243_;
+ wire [1:0] _244_;
+ wire [3:0] _245_;
+ wire _246_;
+ wire _247_;
+ wire [131:0] _248_;
+ wire _249_;
+ wire _250_;
+ wire [3:0] _251_;
+ wire _252_;
+ wire _253_;
+ wire _254_;
+ wire _255_;
+ wire [67:0] _256_;
+ wire [96:0] _257_;
+ wire [3:0] _258_;
+ wire [63:0] _259_;
+ wire _260_;
+ wire [63:0] _261_;
+ wire _262_;
+ wire [5:0] _263_;
+ wire [4:0] _264_;
+ wire [55:0] _265_;
+ wire [63:0] _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire [1:0] _270_;
+ wire _271_;
+ wire _272_;
+ wire _273_;
+ wire _274_;
+ wire _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire _279_;
+ wire _280_;
+ wire _281_;
+ wire _282_;
+ wire _283_;
+ wire _284_;
+ wire [1:0] _285_;
+ wire [31:0] _286_;
+ wire [23:0] _287_;
+ wire [23:0] _288_;
+ wire [23:0] _289_;
+ wire [23:0] _290_;
+ wire [15:0] _291_;
+ wire [15:0] _292_;
+ wire [15:0] _293_;
+ wire [15:0] _294_;
+ wire [43:0] _295_;
+ wire [43:0] _296_;
+ wire [43:0] _297_;
+ wire [43:0] _298_;
+ wire [63:0] _299_;
+ wire [63:0] _300_;
+ wire [63:0] _301_;
+ wire [63:0] _302_;
+ wire [63:0] _303_;
+ wire [15:0] addrsh;
+ input clk;
+ input [66:0] d_in;
+ output [131:0] d_out;
+ output [130:0] i_out;
+ input [144:0] l_in;
+ output [70:0] l_out;
+ reg [436:0] r;
+ input rst;
+ assign _000_ = l_in[16] ? r[132:69] : { 32'h00000000, r[164:133] };
+ assign _001_ = rst ? 1'h0 : _256_[0];
+ assign _002_ = rst ? r[68:1] : { _257_[0], _256_[67:1] };
+ assign _003_ = rst ? 64'h0000000000000000 : _257_[64:1];
+ assign _004_ = rst ? r[164:133] : _257_[96:65];
+ assign _005_ = rst ? 4'h0 : _258_;
+ assign _006_ = rst ? r[234:169] : { _259_, _285_ };
+ assign _007_ = rst ? 1'h0 : _260_;
+ assign _008_ = rst ? r[299:236] : _261_;
+ assign _009_ = rst ? 1'h0 : _262_;
+ assign _010_ = rst ? r[436:301] : { _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_ };
+ always @(posedge clk)
+ r <= { _010_, _009_, _008_, _007_, _006_, _005_, _004_, _003_, _002_, _001_ };
+ assign _011_ = r[306:305] == 2'h0;
+ assign _012_ = r[306:305] == 2'h1;
+ function [30:0] \16216 ;
+ input [30:0] a;
+ input [61:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \16216 = b[30:0];
+ 2'b1?:
+ \16216 = b[61:31];
+ default:
+ \16216 = a;
+ endcase
+ endfunction
+ assign _013_ = \16216 ({ 13'h0000, r[65:48] }, { r[62:32], r[46:16] }, { _012_, _011_ });
+ assign _014_ = r[304:303] == 2'h0;
+ assign _015_ = r[304:303] == 2'h1;
+ assign _016_ = r[304:303] == 2'h2;
+ function [18:0] \16229 ;
+ input [18:0] a;
+ input [56:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \16229 = b[18:0];
+ 3'b?1?:
+ \16229 = b[37:19];
+ 3'b1??:
+ \16229 = b[56:38];
+ default:
+ \16229 = a;
+ endcase
+ endfunction
+ assign _017_ = \16229 (_013_[30:12], { _013_[26:8], _013_[22:4], _013_[18:0] }, { _016_, _015_, _014_ });
+ assign _018_ = r[302:301] == 2'h0;
+ assign _019_ = r[302:301] == 2'h1;
+ assign _020_ = r[302:301] == 2'h2;
+ function [15:0] \16242 ;
+ input [15:0] a;
+ input [47:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \16242 = b[15:0];
+ 3'b?1?:
+ \16242 = b[31:16];
+ 3'b1??:
+ \16242 = b[47:32];
+ default:
+ \16242 = a;
+ endcase
+ endfunction
+ assign addrsh = \16242 (_017_[18:3], { _017_[17:2], _017_[16:1], _017_[15:0] }, { _020_, _019_, _018_ });
+ assign _021_ = $signed(32'd5) < $signed({ 27'h0000000, r[311:307] });
+ assign _022_ = _021_ ? 1'h1 : 1'h0;
+ assign _023_ = $signed(32'd6) < $signed({ 27'h0000000, r[311:307] });
+ assign _024_ = _023_ ? 1'h1 : 1'h0;
+ assign _025_ = $signed(32'd7) < $signed({ 27'h0000000, r[311:307] });
+ assign _026_ = _025_ ? 1'h1 : 1'h0;
+ assign _027_ = $signed(32'd8) < $signed({ 27'h0000000, r[311:307] });
+ assign _028_ = _027_ ? 1'h1 : 1'h0;
+ assign _029_ = $signed(32'd9) < $signed({ 27'h0000000, r[311:307] });
+ assign _030_ = _029_ ? 1'h1 : 1'h0;
+ assign _031_ = $signed(32'd10) < $signed({ 27'h0000000, r[311:307] });
+ assign _032_ = _031_ ? 1'h1 : 1'h0;
+ assign _033_ = $signed(32'd11) < $signed({ 27'h0000000, r[311:307] });
+ assign _034_ = _033_ ? 1'h1 : 1'h0;
+ assign _035_ = $signed(32'd12) < $signed({ 27'h0000000, r[311:307] });
+ assign _036_ = _035_ ? 1'h1 : 1'h0;
+ assign _037_ = $signed(32'd13) < $signed({ 27'h0000000, r[311:307] });
+ assign _038_ = _037_ ? 1'h1 : 1'h0;
+ assign _039_ = $signed(32'd14) < $signed({ 27'h0000000, r[311:307] });
+ assign _040_ = _039_ ? 1'h1 : 1'h0;
+ assign _041_ = $signed(32'd15) < $signed({ 27'h0000000, r[311:307] });
+ assign _042_ = _041_ ? 1'h1 : 1'h0;
+ assign _043_ = $signed(32'd0) < $signed({ 26'h0000000, r[306:301] });
+ assign _044_ = _043_ ? 1'h1 : 1'h0;
+ assign _045_ = $signed(32'd1) < $signed({ 26'h0000000, r[306:301] });
+ assign _046_ = _045_ ? 1'h1 : 1'h0;
+ assign _047_ = $signed(32'd2) < $signed({ 26'h0000000, r[306:301] });
+ assign _048_ = _047_ ? 1'h1 : 1'h0;
+ assign _049_ = $signed(32'd3) < $signed({ 26'h0000000, r[306:301] });
+ assign _050_ = _049_ ? 1'h1 : 1'h0;
+ assign _051_ = $signed(32'd4) < $signed({ 26'h0000000, r[306:301] });
+ assign _052_ = _051_ ? 1'h1 : 1'h0;
+ assign _053_ = $signed(32'd5) < $signed({ 26'h0000000, r[306:301] });
+ assign _054_ = _053_ ? 1'h1 : 1'h0;
+ assign _055_ = $signed(32'd6) < $signed({ 26'h0000000, r[306:301] });
+ assign _056_ = _055_ ? 1'h1 : 1'h0;
+ assign _057_ = $signed(32'd7) < $signed({ 26'h0000000, r[306:301] });
+ assign _058_ = _057_ ? 1'h1 : 1'h0;
+ assign _059_ = $signed(32'd8) < $signed({ 26'h0000000, r[306:301] });
+ assign _060_ = _059_ ? 1'h1 : 1'h0;
+ assign _061_ = $signed(32'd9) < $signed({ 26'h0000000, r[306:301] });
+ assign _062_ = _061_ ? 1'h1 : 1'h0;
+ assign _063_ = $signed(32'd10) < $signed({ 26'h0000000, r[306:301] });
+ assign _064_ = _063_ ? 1'h1 : 1'h0;
+ assign _065_ = $signed(32'd11) < $signed({ 26'h0000000, r[306:301] });
+ assign _066_ = _065_ ? 1'h1 : 1'h0;
+ assign _067_ = $signed(32'd12) < $signed({ 26'h0000000, r[306:301] });
+ assign _068_ = _067_ ? 1'h1 : 1'h0;
+ assign _069_ = $signed(32'd13) < $signed({ 26'h0000000, r[306:301] });
+ assign _070_ = _069_ ? 1'h1 : 1'h0;
+ assign _071_ = $signed(32'd14) < $signed({ 26'h0000000, r[306:301] });
+ assign _072_ = _071_ ? 1'h1 : 1'h0;
+ assign _073_ = $signed(32'd15) < $signed({ 26'h0000000, r[306:301] });
+ assign _074_ = _073_ ? 1'h1 : 1'h0;
+ assign _075_ = $signed(32'd16) < $signed({ 26'h0000000, r[306:301] });
+ assign _076_ = _075_ ? 1'h1 : 1'h0;
+ assign _077_ = $signed(32'd17) < $signed({ 26'h0000000, r[306:301] });
+ assign _078_ = _077_ ? 1'h1 : 1'h0;
+ assign _079_ = $signed(32'd18) < $signed({ 26'h0000000, r[306:301] });
+ assign _080_ = _079_ ? 1'h1 : 1'h0;
+ assign _081_ = $signed(32'd19) < $signed({ 26'h0000000, r[306:301] });
+ assign _082_ = _081_ ? 1'h1 : 1'h0;
+ assign _083_ = $signed(32'd20) < $signed({ 26'h0000000, r[306:301] });
+ assign _084_ = _083_ ? 1'h1 : 1'h0;
+ assign _085_ = $signed(32'd21) < $signed({ 26'h0000000, r[306:301] });
+ assign _086_ = _085_ ? 1'h1 : 1'h0;
+ assign _087_ = $signed(32'd22) < $signed({ 26'h0000000, r[306:301] });
+ assign _088_ = _087_ ? 1'h1 : 1'h0;
+ assign _089_ = $signed(32'd23) < $signed({ 26'h0000000, r[306:301] });
+ assign _090_ = _089_ ? 1'h1 : 1'h0;
+ assign _091_ = $signed(32'd24) < $signed({ 26'h0000000, r[306:301] });
+ assign _092_ = _091_ ? 1'h1 : 1'h0;
+ assign _093_ = $signed(32'd25) < $signed({ 26'h0000000, r[306:301] });
+ assign _094_ = _093_ ? 1'h1 : 1'h0;
+ assign _095_ = $signed(32'd26) < $signed({ 26'h0000000, r[306:301] });
+ assign _096_ = _095_ ? 1'h1 : 1'h0;
+ assign _097_ = $signed(32'd27) < $signed({ 26'h0000000, r[306:301] });
+ assign _098_ = _097_ ? 1'h1 : 1'h0;
+ assign _099_ = $signed(32'd28) < $signed({ 26'h0000000, r[306:301] });
+ assign _100_ = _099_ ? 1'h1 : 1'h0;
+ assign _101_ = $signed(32'd29) < $signed({ 26'h0000000, r[306:301] });
+ assign _102_ = _101_ ? 1'h1 : 1'h0;
+ assign _103_ = $signed(32'd30) < $signed({ 26'h0000000, r[306:301] });
+ assign _104_ = _103_ ? 1'h1 : 1'h0;
+ assign _105_ = $signed(32'd31) < $signed({ 26'h0000000, r[306:301] });
+ assign _106_ = _105_ ? 1'h1 : 1'h0;
+ assign _107_ = $signed(32'd32) < $signed({ 26'h0000000, r[306:301] });
+ assign _108_ = _107_ ? 1'h1 : 1'h0;
+ assign _109_ = $signed(32'd33) < $signed({ 26'h0000000, r[306:301] });
+ assign _110_ = _109_ ? 1'h1 : 1'h0;
+ assign _111_ = $signed(32'd34) < $signed({ 26'h0000000, r[306:301] });
+ assign _112_ = _111_ ? 1'h1 : 1'h0;
+ assign _113_ = $signed(32'd35) < $signed({ 26'h0000000, r[306:301] });
+ assign _114_ = _113_ ? 1'h1 : 1'h0;
+ assign _115_ = $signed(32'd36) < $signed({ 26'h0000000, r[306:301] });
+ assign _116_ = _115_ ? 1'h1 : 1'h0;
+ assign _117_ = $signed(32'd37) < $signed({ 26'h0000000, r[306:301] });
+ assign _118_ = _117_ ? 1'h1 : 1'h0;
+ assign _119_ = $signed(32'd38) < $signed({ 26'h0000000, r[306:301] });
+ assign _120_ = _119_ ? 1'h1 : 1'h0;
+ assign _121_ = $signed(32'd39) < $signed({ 26'h0000000, r[306:301] });
+ assign _122_ = _121_ ? 1'h1 : 1'h0;
+ assign _123_ = $signed(32'd40) < $signed({ 26'h0000000, r[306:301] });
+ assign _124_ = _123_ ? 1'h1 : 1'h0;
+ assign _125_ = $signed(32'd41) < $signed({ 26'h0000000, r[306:301] });
+ assign _126_ = _125_ ? 1'h1 : 1'h0;
+ assign _127_ = $signed(32'd42) < $signed({ 26'h0000000, r[306:301] });
+ assign _128_ = _127_ ? 1'h1 : 1'h0;
+ assign _129_ = $signed(32'd43) < $signed({ 26'h0000000, r[306:301] });
+ assign _130_ = _129_ ? 1'h1 : 1'h0;
+ assign _131_ = ~ l_in[80];
+ assign _132_ = _131_ ? r[235] : r[300];
+ assign _133_ = _131_ ? r[234:171] : r[299:236];
+ assign _134_ = l_in[5] | l_in[4];
+ assign _135_ = ~ _134_;
+ assign _136_ = l_in[2] | l_in[28];
+ assign _137_ = _136_ | l_in[27];
+ assign _138_ = _137_ | l_in[24];
+ assign _139_ = _138_ | l_in[23];
+ assign _140_ = _139_ | l_in[22];
+ assign _141_ = _158_ ? 1'h0 : r[235];
+ assign _142_ = _154_ ? 1'h0 : r[300];
+ assign _143_ = ~ _132_;
+ assign _144_ = { 1'h0, _133_[4:0] } == 6'h00;
+ assign _145_ = _144_ ? 4'h9 : 4'h5;
+ assign _146_ = _144_ ? 1'h1 : 1'h0;
+ assign _147_ = _143_ ? 4'h3 : _145_;
+ assign _148_ = _143_ ? { 1'h0, r[73:69] } : { 1'h0, _133_[62:61], _133_[7:5] };
+ assign _149_ = _143_ ? 1'h0 : _146_;
+ assign _150_ = l_in[1] ? 1'h0 : 1'h1;
+ assign _151_ = l_in[1] ? _140_ : 1'h0;
+ assign _152_ = l_in[1] ? 4'h1 : _147_;
+ assign _153_ = l_in[1] & l_in[10];
+ assign _154_ = l_in[1] & l_in[10];
+ assign _155_ = l_in[1] ? { 1'h0, _133_[62:61], _133_[7:5] } : _148_;
+ assign _156_ = l_in[1] ? 1'h0 : _149_;
+ assign _157_ = l_in[0] ? _152_ : r[168:165];
+ assign _158_ = l_in[0] & _153_;
+ assign _159_ = l_in[0] ? _156_ : 1'h0;
+ assign _160_ = ~ l_in[16];
+ assign _161_ = _160_ ? r[132:69] : l_in[144:81];
+ assign _162_ = _160_ ? l_in[112:81] : r[164:133];
+ assign _163_ = l_in[0] ? _142_ : r[300];
+ assign _164_ = _160_ ? _163_ : 1'h0;
+ assign _165_ = l_in[0] ? _151_ : 1'h0;
+ assign _166_ = l_in[3] ? { 4'h1, _162_, _161_, 1'h1 } : { _157_, r[164:69], _165_ };
+ assign _167_ = l_in[3] ? 1'h0 : _141_;
+ assign _168_ = l_in[0] ? _142_ : r[300];
+ assign _169_ = l_in[3] ? _164_ : _168_;
+ assign _170_ = l_in[0] ? { l_in[80:17], l_in[6], _135_, l_in[4], _150_ } : { r[67:1], 1'h0 };
+ assign _171_ = l_in[0] ? _155_ : { 1'h0, _133_[62:61], _133_[7:5] };
+ assign _172_ = r[168:165] == 4'h0;
+ assign _173_ = r[168:165] == 4'h1;
+ assign _174_ = d_in[1] ? 4'h9 : r[168:165];
+ assign _175_ = r[168:165] == 4'h2;
+ assign _176_ = r[168:165] == 4'h3;
+ assign _177_ = r[67] ? r[235:171] : { 1'h1, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59] };
+ assign _178_ = r[67] ? { 1'h1, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59] } : r[300:236];
+ assign _179_ = { 1'h0, d_in[63:59] } == 6'h00;
+ assign _180_ = _179_ ? 4'h9 : 4'h5;
+ assign _181_ = _184_ ? 1'h1 : 1'h0;
+ assign _182_ = d_in[1] ? _180_ : r[168:165];
+ assign _183_ = d_in[1] ? { d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], 8'h00, d_in[63:59], 1'h0, d_in[9:8], d_in[66:64], _178_, _177_ } : r[367:171];
+ assign _184_ = d_in[1] & _179_;
+ assign _185_ = d_in[2] ? 4'h9 : _182_;
+ assign _186_ = d_in[2] ? 1'h1 : 1'h0;
+ assign _187_ = r[168:165] == 4'h4;
+ assign _188_ = r[306:301] + 6'h13;
+ assign _189_ = _188_ - { 1'h0, r[311:307] };
+ assign _190_ = ~ { _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _191_ = r[65:35] & _190_;
+ assign _192_ = | _191_;
+ assign _193_ = r[67] != r[66];
+ assign _194_ = _193_ | _192_;
+ assign _195_ = { 1'h0, r[311:307] } < 6'h05;
+ assign _196_ = { 1'h0, r[311:307] } > 6'h10;
+ assign _197_ = _195_ | _196_;
+ assign _198_ = r[306:301] + 6'h13;
+ assign _199_ = { 1'h0, r[311:307] } > _198_;
+ assign _200_ = _197_ | _199_;
+ assign _201_ = _200_ ? 4'h9 : 4'h6;
+ assign _202_ = _200_ ? 1'h1 : 1'h0;
+ assign _203_ = _194_ ? 4'h9 : _201_;
+ assign _204_ = _194_ ? 1'h0 : _202_;
+ assign _205_ = _194_ ? 1'h1 : 1'h0;
+ assign _206_ = r[168:165] == 4'h5;
+ assign _207_ = r[168:165] == 4'h6;
+ assign _208_ = ~ d_in[62];
+ assign _209_ = r[3] | _208_;
+ assign _210_ = ~ r[1];
+ assign _211_ = ~ r[2];
+ assign _212_ = d_in[61] & _211_;
+ assign _213_ = d_in[60] | _212_;
+ assign _214_ = ~ d_in[64];
+ assign _215_ = d_in[59] & _214_;
+ assign _216_ = _210_ ? _213_ : _215_;
+ assign _217_ = _209_ ? _216_ : 1'h0;
+ assign _218_ = ~ r[2];
+ assign _219_ = d_in[66] | _218_;
+ assign _220_ = d_in[51] & _219_;
+ assign _221_ = _217_ & _220_;
+ assign _222_ = ~ _217_;
+ assign _223_ = _221_ ? 4'h8 : 4'h9;
+ assign _224_ = _221_ ? 2'h0 : { _217_, _222_ };
+ assign _225_ = { 1'h0, d_in[63:59] } < 6'h05;
+ assign _226_ = { 1'h0, d_in[63:59] } > 6'h10;
+ assign _227_ = _225_ | _226_;
+ assign _228_ = { 1'h0, d_in[63:59] } > r[306:301];
+ assign _229_ = _227_ | _228_;
+ assign _230_ = r[306:301] - { 1'h0, d_in[63:59] };
+ assign _231_ = _229_ ? 4'h9 : 4'h6;
+ assign _232_ = _229_ ? r[367:301] : { d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], 8'h00, d_in[63:59], _230_ };
+ assign _233_ = _229_ ? 1'h1 : 1'h0;
+ assign _234_ = d_in[9] ? _223_ : _231_;
+ assign _235_ = d_in[9] ? r[367:301] : _232_;
+ assign _236_ = d_in[9] ? 1'h0 : _233_;
+ assign _237_ = d_in[9] ? _224_ : 2'h0;
+ assign _238_ = d_in[10] ? _234_ : 4'h9;
+ assign _239_ = d_in[10] ? _235_ : r[367:301];
+ assign _240_ = d_in[10] ? 1'h0 : 1'h1;
+ assign _241_ = d_in[10] ? _236_ : 1'h0;
+ assign _242_ = d_in[10] ? _237_ : 2'h0;
+ assign _243_ = d_in[1] ? _238_ : r[168:165];
+ assign _244_ = d_in[1] ? _242_ : 2'h0;
+ assign _245_ = d_in[2] ? 4'h9 : _243_;
+ assign _246_ = d_in[1] ? _241_ : 1'h0;
+ assign _247_ = d_in[2] ? 1'h1 : _246_;
+ assign _248_ = d_in[1] ? { _240_, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59], _239_ } : { 1'h0, r[431:301] };
+ assign _249_ = r[168:165] == 4'h7;
+ assign _250_ = ~ r[1];
+ assign _251_ = _250_ ? 4'h2 : 4'h0;
+ assign _252_ = _250_ ? 1'h1 : 1'h0;
+ assign _253_ = _250_ ? 1'h0 : 1'h1;
+ assign _254_ = r[168:165] == 4'h8;
+ assign _255_ = r[168:165] == 4'h9;
+ function [67:0] \17161 ;
+ input [67:0] a;
+ input [679:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17161 = b[67:0];
+ 10'b????????1?:
+ \17161 = b[135:68];
+ 10'b???????1??:
+ \17161 = b[203:136];
+ 10'b??????1???:
+ \17161 = b[271:204];
+ 10'b?????1????:
+ \17161 = b[339:272];
+ 10'b????1?????:
+ \17161 = b[407:340];
+ 10'b???1??????:
+ \17161 = b[475:408];
+ 10'b??1???????:
+ \17161 = b[543:476];
+ 10'b?1????????:
+ \17161 = b[611:544];
+ 10'b1?????????:
+ \17161 = b[679:612];
+ default:
+ \17161 = a;
+ endcase
+ endfunction
+ assign _256_ = \17161 (68'hxxxxxxxxxxxxxxxxx, { r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, _170_ }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [96:0] \17166 ;
+ input [96:0] a;
+ input [969:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17166 = b[96:0];
+ 10'b????????1?:
+ \17166 = b[193:97];
+ 10'b???????1??:
+ \17166 = b[290:194];
+ 10'b??????1???:
+ \17166 = b[387:291];
+ 10'b?????1????:
+ \17166 = b[484:388];
+ 10'b????1?????:
+ \17166 = b[581:485];
+ 10'b???1??????:
+ \17166 = b[678:582];
+ 10'b??1???????:
+ \17166 = b[775:679];
+ 10'b?1????????:
+ \17166 = b[872:776];
+ 10'b1?????????:
+ \17166 = b[969:873];
+ default:
+ \17166 = a;
+ endcase
+ endfunction
+ assign _257_ = \17166 (97'hxxxxxxxxxxxxxxxxxxxxxxxxx, { r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, r[164:69], 1'h0, _166_[96:0] }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [3:0] \17169 ;
+ input [3:0] a;
+ input [39:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17169 = b[3:0];
+ 10'b????????1?:
+ \17169 = b[7:4];
+ 10'b???????1??:
+ \17169 = b[11:8];
+ 10'b??????1???:
+ \17169 = b[15:12];
+ 10'b?????1????:
+ \17169 = b[19:16];
+ 10'b????1?????:
+ \17169 = b[23:20];
+ 10'b???1??????:
+ \17169 = b[27:24];
+ 10'b??1???????:
+ \17169 = b[31:28];
+ 10'b?1????????:
+ \17169 = b[35:32];
+ 10'b1?????????:
+ \17169 = b[39:36];
+ default:
+ \17169 = a;
+ endcase
+ endfunction
+ assign _258_ = \17169 (4'hx, { 4'h0, _251_, _245_, 4'h7, _203_, _185_, 4'h4, _174_, 4'h2, _166_[100:97] }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [63:0] \17173 ;
+ input [63:0] a;
+ input [639:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17173 = b[63:0];
+ 10'b????????1?:
+ \17173 = b[127:64];
+ 10'b???????1??:
+ \17173 = b[191:128];
+ 10'b??????1???:
+ \17173 = b[255:192];
+ 10'b?????1????:
+ \17173 = b[319:256];
+ 10'b????1?????:
+ \17173 = b[383:320];
+ 10'b???1??????:
+ \17173 = b[447:384];
+ 10'b??1???????:
+ \17173 = b[511:448];
+ 10'b?1????????:
+ \17173 = b[575:512];
+ 10'b1?????????:
+ \17173 = b[639:576];
+ default:
+ \17173 = a;
+ endcase
+ endfunction
+ assign _259_ = \17173 (64'hxxxxxxxxxxxxxxxx, { r[234:171], r[234:171], r[234:171], r[234:171], r[234:171], _183_[63:0], r[234:171], r[234:171], r[234:171], r[234:171] }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17177 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17177 = b[0:0];
+ 10'b????????1?:
+ \17177 = b[1:1];
+ 10'b???????1??:
+ \17177 = b[2:2];
+ 10'b??????1???:
+ \17177 = b[3:3];
+ 10'b?????1????:
+ \17177 = b[4:4];
+ 10'b????1?????:
+ \17177 = b[5:5];
+ 10'b???1??????:
+ \17177 = b[6:6];
+ 10'b??1???????:
+ \17177 = b[7:7];
+ 10'b?1????????:
+ \17177 = b[8:8];
+ 10'b1?????????:
+ \17177 = b[9:9];
+ default:
+ \17177 = a;
+ endcase
+ endfunction
+ assign _260_ = \17177 (1'hx, { r[235], r[235], r[235], r[235], r[235], _183_[64], r[235], r[235], r[235], _167_ }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [63:0] \17181 ;
+ input [63:0] a;
+ input [639:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17181 = b[63:0];
+ 10'b????????1?:
+ \17181 = b[127:64];
+ 10'b???????1??:
+ \17181 = b[191:128];
+ 10'b??????1???:
+ \17181 = b[255:192];
+ 10'b?????1????:
+ \17181 = b[319:256];
+ 10'b????1?????:
+ \17181 = b[383:320];
+ 10'b???1??????:
+ \17181 = b[447:384];
+ 10'b??1???????:
+ \17181 = b[511:448];
+ 10'b?1????????:
+ \17181 = b[575:512];
+ 10'b1?????????:
+ \17181 = b[639:576];
+ default:
+ \17181 = a;
+ endcase
+ endfunction
+ assign _261_ = \17181 (64'hxxxxxxxxxxxxxxxx, { r[299:236], r[299:236], r[299:236], r[299:236], r[299:236], _183_[128:65], r[299:236], r[299:236], r[299:236], r[299:236] }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17185 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17185 = b[0:0];
+ 10'b????????1?:
+ \17185 = b[1:1];
+ 10'b???????1??:
+ \17185 = b[2:2];
+ 10'b??????1???:
+ \17185 = b[3:3];
+ 10'b?????1????:
+ \17185 = b[4:4];
+ 10'b????1?????:
+ \17185 = b[5:5];
+ 10'b???1??????:
+ \17185 = b[6:6];
+ 10'b??1???????:
+ \17185 = b[7:7];
+ 10'b?1????????:
+ \17185 = b[8:8];
+ 10'b1?????????:
+ \17185 = b[9:9];
+ default:
+ \17185 = a;
+ endcase
+ endfunction
+ assign _262_ = \17185 (1'hx, { r[300], r[300], r[300], r[300], r[300], _183_[129], r[300], r[300], r[300], _169_ }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [5:0] \17190 ;
+ input [5:0] a;
+ input [59:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17190 = b[5:0];
+ 10'b????????1?:
+ \17190 = b[11:6];
+ 10'b???????1??:
+ \17190 = b[17:12];
+ 10'b??????1???:
+ \17190 = b[23:18];
+ 10'b?????1????:
+ \17190 = b[29:24];
+ 10'b????1?????:
+ \17190 = b[35:30];
+ 10'b???1??????:
+ \17190 = b[41:36];
+ 10'b??1???????:
+ \17190 = b[47:42];
+ 10'b?1????????:
+ \17190 = b[53:48];
+ 10'b1?????????:
+ \17190 = b[59:54];
+ default:
+ \17190 = a;
+ endcase
+ endfunction
+ assign _263_ = \17190 (6'hxx, { r[306:301], r[306:301], _248_[5:0], r[306:301], _189_, _183_[135:130], r[306:301], r[306:301], r[306:301], _171_ }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [4:0] \17195 ;
+ input [4:0] a;
+ input [49:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17195 = b[4:0];
+ 10'b????????1?:
+ \17195 = b[9:5];
+ 10'b???????1??:
+ \17195 = b[14:10];
+ 10'b??????1???:
+ \17195 = b[19:15];
+ 10'b?????1????:
+ \17195 = b[24:20];
+ 10'b????1?????:
+ \17195 = b[29:25];
+ 10'b???1??????:
+ \17195 = b[34:30];
+ 10'b??1???????:
+ \17195 = b[39:35];
+ 10'b?1????????:
+ \17195 = b[44:40];
+ 10'b1?????????:
+ \17195 = b[49:45];
+ default:
+ \17195 = a;
+ endcase
+ endfunction
+ assign _264_ = \17195 (5'hxx, { r[311:307], r[311:307], _248_[10:6], r[311:307], r[311:307], _183_[140:136], r[311:307], r[311:307], r[311:307], _133_[4:0] }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [55:0] \17200 ;
+ input [55:0] a;
+ input [559:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17200 = b[55:0];
+ 10'b????????1?:
+ \17200 = b[111:56];
+ 10'b???????1??:
+ \17200 = b[167:112];
+ 10'b??????1???:
+ \17200 = b[223:168];
+ 10'b?????1????:
+ \17200 = b[279:224];
+ 10'b????1?????:
+ \17200 = b[335:280];
+ 10'b???1??????:
+ \17200 = b[391:336];
+ 10'b??1???????:
+ \17200 = b[447:392];
+ 10'b?1????????:
+ \17200 = b[503:448];
+ 10'b1?????????:
+ \17200 = b[559:504];
+ default:
+ \17200 = a;
+ endcase
+ endfunction
+ assign _265_ = \17200 (56'hxxxxxxxxxxxxxx, { r[367:312], r[367:312], _248_[66:11], r[367:312], r[367:312], _183_[196:141], r[367:312], r[367:312], r[367:312], _133_[55:8], 8'h00 }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [63:0] \17204 ;
+ input [63:0] a;
+ input [639:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17204 = b[63:0];
+ 10'b????????1?:
+ \17204 = b[127:64];
+ 10'b???????1??:
+ \17204 = b[191:128];
+ 10'b??????1???:
+ \17204 = b[255:192];
+ 10'b?????1????:
+ \17204 = b[319:256];
+ 10'b????1?????:
+ \17204 = b[383:320];
+ 10'b???1??????:
+ \17204 = b[447:384];
+ 10'b??1???????:
+ \17204 = b[511:448];
+ 10'b?1????????:
+ \17204 = b[575:512];
+ 10'b1?????????:
+ \17204 = b[639:576];
+ default:
+ \17204 = a;
+ endcase
+ endfunction
+ assign _266_ = \17204 (64'hxxxxxxxxxxxxxxxx, { r[431:368], r[431:368], _248_[130:67], r[431:368], r[431:368], r[431:368], r[431:368], r[431:368], r[431:368], r[431:368] }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17207 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17207 = b[0:0];
+ 10'b????????1?:
+ \17207 = b[1:1];
+ 10'b???????1??:
+ \17207 = b[2:2];
+ 10'b??????1???:
+ \17207 = b[3:3];
+ 10'b?????1????:
+ \17207 = b[4:4];
+ 10'b????1?????:
+ \17207 = b[5:5];
+ 10'b???1??????:
+ \17207 = b[6:6];
+ 10'b??1???????:
+ \17207 = b[7:7];
+ 10'b?1????????:
+ \17207 = b[8:8];
+ 10'b1?????????:
+ \17207 = b[9:9];
+ default:
+ \17207 = a;
+ endcase
+ endfunction
+ assign _267_ = \17207 (1'hx, { 2'h0, _248_[131], 2'h0, _181_, 3'h0, _159_ }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17209 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17209 = b[0:0];
+ 10'b????????1?:
+ \17209 = b[1:1];
+ 10'b???????1??:
+ \17209 = b[2:2];
+ 10'b??????1???:
+ \17209 = b[3:3];
+ 10'b?????1????:
+ \17209 = b[4:4];
+ 10'b????1?????:
+ \17209 = b[5:5];
+ 10'b???1??????:
+ \17209 = b[6:6];
+ 10'b??1???????:
+ \17209 = b[7:7];
+ 10'b?1????????:
+ \17209 = b[8:8];
+ 10'b1?????????:
+ \17209 = b[9:9];
+ default:
+ \17209 = a;
+ endcase
+ endfunction
+ assign _268_ = \17209 (1'hx, { 2'h0, _247_, 1'h0, _204_, _186_, 4'h0 }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17211 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17211 = b[0:0];
+ 10'b????????1?:
+ \17211 = b[1:1];
+ 10'b???????1??:
+ \17211 = b[2:2];
+ 10'b??????1???:
+ \17211 = b[3:3];
+ 10'b?????1????:
+ \17211 = b[4:4];
+ 10'b????1?????:
+ \17211 = b[5:5];
+ 10'b???1??????:
+ \17211 = b[6:6];
+ 10'b??1???????:
+ \17211 = b[7:7];
+ 10'b?1????????:
+ \17211 = b[8:8];
+ 10'b1?????????:
+ \17211 = b[9:9];
+ default:
+ \17211 = a;
+ endcase
+ endfunction
+ assign _269_ = \17211 (1'hx, { 4'h0, _205_, 5'h00 }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [1:0] \17214 ;
+ input [1:0] a;
+ input [19:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17214 = b[1:0];
+ 10'b????????1?:
+ \17214 = b[3:2];
+ 10'b???????1??:
+ \17214 = b[5:4];
+ 10'b??????1???:
+ \17214 = b[7:6];
+ 10'b?????1????:
+ \17214 = b[9:8];
+ 10'b????1?????:
+ \17214 = b[11:10];
+ 10'b???1??????:
+ \17214 = b[13:12];
+ 10'b??1???????:
+ \17214 = b[15:14];
+ 10'b?1????????:
+ \17214 = b[17:16];
+ 10'b1?????????:
+ \17214 = b[19:18];
+ default:
+ \17214 = a;
+ endcase
+ endfunction
+ assign _270_ = \17214 (2'hx, { 4'h0, _244_, 14'h0000 }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17228 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17228 = b[0:0];
+ 10'b????????1?:
+ \17228 = b[1:1];
+ 10'b???????1??:
+ \17228 = b[2:2];
+ 10'b??????1???:
+ \17228 = b[3:3];
+ 10'b?????1????:
+ \17228 = b[4:4];
+ 10'b????1?????:
+ \17228 = b[5:5];
+ 10'b???1??????:
+ \17228 = b[6:6];
+ 10'b??1???????:
+ \17228 = b[7:7];
+ 10'b?1????????:
+ \17228 = b[8:8];
+ 10'b1?????????:
+ \17228 = b[9:9];
+ default:
+ \17228 = a;
+ endcase
+ endfunction
+ assign _271_ = \17228 (1'hx, { 1'h0, _252_, 8'h4a }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17233 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17233 = b[0:0];
+ 10'b????????1?:
+ \17233 = b[1:1];
+ 10'b???????1??:
+ \17233 = b[2:2];
+ 10'b??????1???:
+ \17233 = b[3:3];
+ 10'b?????1????:
+ \17233 = b[4:4];
+ 10'b????1?????:
+ \17233 = b[5:5];
+ 10'b???1??????:
+ \17233 = b[6:6];
+ 10'b??1???????:
+ \17233 = b[7:7];
+ 10'b?1????????:
+ \17233 = b[8:8];
+ 10'b1?????????:
+ \17233 = b[9:9];
+ default:
+ \17233 = a;
+ endcase
+ endfunction
+ assign _272_ = \17233 (1'hx, 10'h100, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17237 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17237 = b[0:0];
+ 10'b????????1?:
+ \17237 = b[1:1];
+ 10'b???????1??:
+ \17237 = b[2:2];
+ 10'b??????1???:
+ \17237 = b[3:3];
+ 10'b?????1????:
+ \17237 = b[4:4];
+ 10'b????1?????:
+ \17237 = b[5:5];
+ 10'b???1??????:
+ \17237 = b[6:6];
+ 10'b??1???????:
+ \17237 = b[7:7];
+ 10'b?1????????:
+ \17237 = b[8:8];
+ 10'b1?????????:
+ \17237 = b[9:9];
+ default:
+ \17237 = a;
+ endcase
+ endfunction
+ assign _273_ = \17237 (1'hx, { 1'h0, _253_, 8'h00 }, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17242 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17242 = b[0:0];
+ 10'b????????1?:
+ \17242 = b[1:1];
+ 10'b???????1??:
+ \17242 = b[2:2];
+ 10'b??????1???:
+ \17242 = b[3:3];
+ 10'b?????1????:
+ \17242 = b[4:4];
+ 10'b????1?????:
+ \17242 = b[5:5];
+ 10'b???1??????:
+ \17242 = b[6:6];
+ 10'b??1???????:
+ \17242 = b[7:7];
+ 10'b?1????????:
+ \17242 = b[8:8];
+ 10'b1?????????:
+ \17242 = b[9:9];
+ default:
+ \17242 = a;
+ endcase
+ endfunction
+ assign _274_ = \17242 (1'hx, 10'h002, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ function [0:0] \17247 ;
+ input [0:0] a;
+ input [9:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \17247 = b[0:0];
+ 10'b????????1?:
+ \17247 = b[1:1];
+ 10'b???????1??:
+ \17247 = b[2:2];
+ 10'b??????1???:
+ \17247 = b[3:3];
+ 10'b?????1????:
+ \17247 = b[4:4];
+ 10'b????1?????:
+ \17247 = b[5:5];
+ 10'b???1??????:
+ \17247 = b[6:6];
+ 10'b??1???????:
+ \17247 = b[7:7];
+ 10'b?1????????:
+ \17247 = b[8:8];
+ 10'b1?????????:
+ \17247 = b[9:9];
+ default:
+ \17247 = a;
+ endcase
+ endfunction
+ assign _275_ = \17247 (1'hx, 10'h008, { _255_, _254_, _249_, _207_, _206_, _187_, _176_, _175_, _173_, _172_ });
+ assign _276_ = _258_ == 4'h9;
+ assign _277_ = _258_ == 4'h8;
+ assign _278_ = _277_ & r[1];
+ assign _279_ = _276_ | _278_;
+ assign _280_ = _267_ | _268_;
+ assign _281_ = _280_ | _269_;
+ assign _282_ = _281_ | _270_[0];
+ assign _283_ = _282_ | _270_[1];
+ assign _284_ = ~ _283_;
+ assign _285_ = _279_ ? { _283_, _284_ } : 2'h0;
+ assign _286_ = r[67] ? 32'd0 : r[164:133];
+ assign _287_ = ~ { _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _288_ = r[104:81] & _287_;
+ assign _289_ = _286_[31:8] & { _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _290_ = _288_ | _289_;
+ assign _291_ = ~ { _042_, _040_, _038_, _036_, _034_, _032_, _030_, _028_, _026_, _024_, _022_, 5'h1f };
+ assign _292_ = r[330:315] & _291_;
+ assign _293_ = addrsh & { _042_, _040_, _038_, _036_, _034_, _032_, _030_, _028_, _026_, _024_, _022_, 5'h1f };
+ assign _294_ = _292_ | _293_;
+ assign _295_ = ~ { _130_, _128_, _126_, _124_, _122_, _120_, _118_, _116_, _114_, _112_, _110_, _108_, _106_, _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _296_ = r[423:380] & _295_;
+ assign _297_ = r[59:16] & { _130_, _128_, _126_, _124_, _122_, _120_, _118_, _116_, _114_, _112_, _110_, _108_, _106_, _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _298_ = _296_ | _297_;
+ assign _299_ = _275_ ? { 8'h00, r[124:105], _290_, _286_[7:0], 4'h0 } : { 8'h00, r[367:331], _294_, 3'h0 };
+ assign _300_ = _272_ ? { 8'h00, _298_, r[379:368] } : 64'h0000000000000000;
+ assign _301_ = _272_ ? { r[67:16], 12'h000 } : _299_;
+ assign _302_ = _274_ ? 64'h0000000000000000 : _300_;
+ assign _303_ = _274_ ? r[67:4] : _301_;
+ assign l_out = { _000_, r[436:432], r[170:169] };
+ assign d_out = { _302_, _303_, _272_, r[68], _274_, _271_ };
+ assign i_out = { _302_, _303_, r[68], _274_, _273_ };
+endmodule
+
+
+
+module random(clk, data, raw, err);
+ input clk;
+ output [63:0] data;
+ output err;
+ output [63:0] raw;
+ assign data = 64'hffffffffffffffff;
+ assign raw = 64'hffffffffffffffff;
+ assign err = 1'h1;
+endmodule
+
+
+module rotator(rs, ra, shift, insn, is_32bit, right_shift, arith, clear_left, clear_right, sign_ext_rs, result, carry_out);
+ wire [31:0] _000_;
+ wire [31:0] _001_;
+ wire [5:0] _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire [6:0] _014_;
+ wire _015_;
+ wire [6:0] _016_;
+ wire [6:0] _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire [5:0] _021_;
+ wire [6:0] _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire _233_;
+ wire _234_;
+ wire _235_;
+ wire _236_;
+ wire _237_;
+ wire _238_;
+ wire _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire _245_;
+ wire _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire _250_;
+ wire _251_;
+ wire _252_;
+ wire _253_;
+ wire _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire _259_;
+ wire _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire _264_;
+ wire _265_;
+ wire _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire _270_;
+ wire _271_;
+ wire _272_;
+ wire _273_;
+ wire _274_;
+ wire _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire _279_;
+ wire _280_;
+ wire _281_;
+ wire _282_;
+ wire _283_;
+ wire _284_;
+ wire _285_;
+ wire _286_;
+ wire [63:0] _287_;
+ wire [63:0] _288_;
+ wire [63:0] _289_;
+ wire [63:0] _290_;
+ wire [63:0] _291_;
+ wire [63:0] _292_;
+ wire _293_;
+ wire [63:0] _294_;
+ wire [63:0] _295_;
+ wire [63:0] _296_;
+ wire [63:0] _297_;
+ wire [63:0] _298_;
+ wire [63:0] _299_;
+ wire _300_;
+ wire [63:0] _301_;
+ wire _302_;
+ wire [63:0] _303_;
+ wire [63:0] _304_;
+ wire [63:0] _305_;
+ wire _306_;
+ wire [63:0] _307_;
+ wire [63:0] _308_;
+ wire _309_;
+ wire _310_;
+ input arith;
+ output carry_out;
+ input clear_left;
+ input clear_right;
+ input [31:0] insn;
+ input is_32bit;
+ wire [6:0] mb;
+ wire [6:0] me;
+ wire [63:0] ml;
+ wire [1:0] output_mode;
+ input [63:0] ra;
+ output [63:0] result;
+ input right_shift;
+ wire [63:0] rot;
+ wire [63:0] rot1;
+ wire [63:0] rot2;
+ wire [5:0] rot_count;
+ input [63:0] rs;
+ input [6:0] shift;
+ input sign_ext_rs;
+ assign _000_ = sign_ext_rs ? { rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31] } : rs[63:32];
+ assign _001_ = is_32bit ? rs[31:0] : _000_;
+ assign _002_ = - $signed(shift[5:0]);
+ assign rot_count = right_shift ? _002_ : shift[5:0];
+ assign _003_ = rot_count[1:0] == 2'h0;
+ assign _004_ = rot_count[1:0] == 2'h1;
+ assign _005_ = rot_count[1:0] == 2'h2;
+ function [63:0] \20645 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20645 = b[63:0];
+ 3'b?1?:
+ \20645 = b[127:64];
+ 3'b1??:
+ \20645 = b[191:128];
+ default:
+ \20645 = a;
+ endcase
+ endfunction
+ assign rot1 = \20645 ({ _001_[28:0], rs[31:0], _001_[31:29] }, { _001_[29:0], rs[31:0], _001_[31:30], _001_[30:0], rs[31:0], _001_[31], _001_, rs[31:0] }, { _005_, _004_, _003_ });
+ assign _006_ = rot_count[3:2] == 2'h0;
+ assign _007_ = rot_count[3:2] == 2'h1;
+ assign _008_ = rot_count[3:2] == 2'h2;
+ function [63:0] \20663 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20663 = b[63:0];
+ 3'b?1?:
+ \20663 = b[127:64];
+ 3'b1??:
+ \20663 = b[191:128];
+ default:
+ \20663 = a;
+ endcase
+ endfunction
+ assign rot2 = \20663 ({ rot1[51:0], rot1[63:52] }, { rot1[55:0], rot1[63:56], rot1[59:0], rot1[63:60], rot1 }, { _008_, _007_, _006_ });
+ assign _009_ = rot_count[5:4] == 2'h0;
+ assign _010_ = rot_count[5:4] == 2'h1;
+ assign _011_ = rot_count[5:4] == 2'h2;
+ function [63:0] \20681 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20681 = b[63:0];
+ 3'b?1?:
+ \20681 = b[127:64];
+ 3'b1??:
+ \20681 = b[191:128];
+ default:
+ \20681 = a;
+ endcase
+ endfunction
+ assign rot = \20681 ({ rot2[15:0], rot2[63:16] }, { rot2[31:0], rot2[63:32], rot2[47:0], rot2[63:48], rot2 }, { _011_, _010_, _009_ });
+ assign _012_ = ~ is_32bit;
+ assign _013_ = shift[6] & _012_;
+ assign _014_ = is_32bit ? { 2'h1, insn[10:6] } : { 1'h0, insn[5], insn[10:6] };
+ assign _015_ = ~ shift[5];
+ assign _016_ = is_32bit ? { shift[5], _015_, shift[4:0] } : { _013_, shift[5:0] };
+ assign _017_ = right_shift ? _016_ : { 1'h0, is_32bit, 5'h00 };
+ assign mb = clear_left ? _014_ : _017_;
+ assign _018_ = clear_right & is_32bit;
+ assign _019_ = ~ clear_left;
+ assign _020_ = clear_right & _019_;
+ assign _021_ = ~ shift[5:0];
+ assign _022_ = _020_ ? { 1'h0, insn[5], insn[10:6] } : { _013_, _021_ };
+ assign me = _018_ ? { 2'h1, insn[5:1] } : _022_;
+ assign _023_ = $signed(32'd0) >= $signed({ 25'h0000000, mb });
+ assign _024_ = _023_ ? 1'h1 : 1'h0;
+ assign _025_ = $signed(32'd1) >= $signed({ 25'h0000000, mb });
+ assign _026_ = _025_ ? 1'h1 : 1'h0;
+ assign _027_ = $signed(32'd2) >= $signed({ 25'h0000000, mb });
+ assign _028_ = _027_ ? 1'h1 : 1'h0;
+ assign _029_ = $signed(32'd3) >= $signed({ 25'h0000000, mb });
+ assign _030_ = _029_ ? 1'h1 : 1'h0;
+ assign _031_ = $signed(32'd4) >= $signed({ 25'h0000000, mb });
+ assign _032_ = _031_ ? 1'h1 : 1'h0;
+ assign _033_ = $signed(32'd5) >= $signed({ 25'h0000000, mb });
+ assign _034_ = _033_ ? 1'h1 : 1'h0;
+ assign _035_ = $signed(32'd6) >= $signed({ 25'h0000000, mb });
+ assign _036_ = _035_ ? 1'h1 : 1'h0;
+ assign _037_ = $signed(32'd7) >= $signed({ 25'h0000000, mb });
+ assign _038_ = _037_ ? 1'h1 : 1'h0;
+ assign _039_ = $signed(32'd8) >= $signed({ 25'h0000000, mb });
+ assign _040_ = _039_ ? 1'h1 : 1'h0;
+ assign _041_ = $signed(32'd9) >= $signed({ 25'h0000000, mb });
+ assign _042_ = _041_ ? 1'h1 : 1'h0;
+ assign _043_ = $signed(32'd10) >= $signed({ 25'h0000000, mb });
+ assign _044_ = _043_ ? 1'h1 : 1'h0;
+ assign _045_ = $signed(32'd11) >= $signed({ 25'h0000000, mb });
+ assign _046_ = _045_ ? 1'h1 : 1'h0;
+ assign _047_ = $signed(32'd12) >= $signed({ 25'h0000000, mb });
+ assign _048_ = _047_ ? 1'h1 : 1'h0;
+ assign _049_ = $signed(32'd13) >= $signed({ 25'h0000000, mb });
+ assign _050_ = _049_ ? 1'h1 : 1'h0;
+ assign _051_ = $signed(32'd14) >= $signed({ 25'h0000000, mb });
+ assign _052_ = _051_ ? 1'h1 : 1'h0;
+ assign _053_ = $signed(32'd15) >= $signed({ 25'h0000000, mb });
+ assign _054_ = _053_ ? 1'h1 : 1'h0;
+ assign _055_ = $signed(32'd16) >= $signed({ 25'h0000000, mb });
+ assign _056_ = _055_ ? 1'h1 : 1'h0;
+ assign _057_ = $signed(32'd17) >= $signed({ 25'h0000000, mb });
+ assign _058_ = _057_ ? 1'h1 : 1'h0;
+ assign _059_ = $signed(32'd18) >= $signed({ 25'h0000000, mb });
+ assign _060_ = _059_ ? 1'h1 : 1'h0;
+ assign _061_ = $signed(32'd19) >= $signed({ 25'h0000000, mb });
+ assign _062_ = _061_ ? 1'h1 : 1'h0;
+ assign _063_ = $signed(32'd20) >= $signed({ 25'h0000000, mb });
+ assign _064_ = _063_ ? 1'h1 : 1'h0;
+ assign _065_ = $signed(32'd21) >= $signed({ 25'h0000000, mb });
+ assign _066_ = _065_ ? 1'h1 : 1'h0;
+ assign _067_ = $signed(32'd22) >= $signed({ 25'h0000000, mb });
+ assign _068_ = _067_ ? 1'h1 : 1'h0;
+ assign _069_ = $signed(32'd23) >= $signed({ 25'h0000000, mb });
+ assign _070_ = _069_ ? 1'h1 : 1'h0;
+ assign _071_ = $signed(32'd24) >= $signed({ 25'h0000000, mb });
+ assign _072_ = _071_ ? 1'h1 : 1'h0;
+ assign _073_ = $signed(32'd25) >= $signed({ 25'h0000000, mb });
+ assign _074_ = _073_ ? 1'h1 : 1'h0;
+ assign _075_ = $signed(32'd26) >= $signed({ 25'h0000000, mb });
+ assign _076_ = _075_ ? 1'h1 : 1'h0;
+ assign _077_ = $signed(32'd27) >= $signed({ 25'h0000000, mb });
+ assign _078_ = _077_ ? 1'h1 : 1'h0;
+ assign _079_ = $signed(32'd28) >= $signed({ 25'h0000000, mb });
+ assign _080_ = _079_ ? 1'h1 : 1'h0;
+ assign _081_ = $signed(32'd29) >= $signed({ 25'h0000000, mb });
+ assign _082_ = _081_ ? 1'h1 : 1'h0;
+ assign _083_ = $signed(32'd30) >= $signed({ 25'h0000000, mb });
+ assign _084_ = _083_ ? 1'h1 : 1'h0;
+ assign _085_ = $signed(32'd31) >= $signed({ 25'h0000000, mb });
+ assign _086_ = _085_ ? 1'h1 : 1'h0;
+ assign _087_ = $signed(32'd32) >= $signed({ 25'h0000000, mb });
+ assign _088_ = _087_ ? 1'h1 : 1'h0;
+ assign _089_ = $signed(32'd33) >= $signed({ 25'h0000000, mb });
+ assign _090_ = _089_ ? 1'h1 : 1'h0;
+ assign _091_ = $signed(32'd34) >= $signed({ 25'h0000000, mb });
+ assign _092_ = _091_ ? 1'h1 : 1'h0;
+ assign _093_ = $signed(32'd35) >= $signed({ 25'h0000000, mb });
+ assign _094_ = _093_ ? 1'h1 : 1'h0;
+ assign _095_ = $signed(32'd36) >= $signed({ 25'h0000000, mb });
+ assign _096_ = _095_ ? 1'h1 : 1'h0;
+ assign _097_ = $signed(32'd37) >= $signed({ 25'h0000000, mb });
+ assign _098_ = _097_ ? 1'h1 : 1'h0;
+ assign _099_ = $signed(32'd38) >= $signed({ 25'h0000000, mb });
+ assign _100_ = _099_ ? 1'h1 : 1'h0;
+ assign _101_ = $signed(32'd39) >= $signed({ 25'h0000000, mb });
+ assign _102_ = _101_ ? 1'h1 : 1'h0;
+ assign _103_ = $signed(32'd40) >= $signed({ 25'h0000000, mb });
+ assign _104_ = _103_ ? 1'h1 : 1'h0;
+ assign _105_ = $signed(32'd41) >= $signed({ 25'h0000000, mb });
+ assign _106_ = _105_ ? 1'h1 : 1'h0;
+ assign _107_ = $signed(32'd42) >= $signed({ 25'h0000000, mb });
+ assign _108_ = _107_ ? 1'h1 : 1'h0;
+ assign _109_ = $signed(32'd43) >= $signed({ 25'h0000000, mb });
+ assign _110_ = _109_ ? 1'h1 : 1'h0;
+ assign _111_ = $signed(32'd44) >= $signed({ 25'h0000000, mb });
+ assign _112_ = _111_ ? 1'h1 : 1'h0;
+ assign _113_ = $signed(32'd45) >= $signed({ 25'h0000000, mb });
+ assign _114_ = _113_ ? 1'h1 : 1'h0;
+ assign _115_ = $signed(32'd46) >= $signed({ 25'h0000000, mb });
+ assign _116_ = _115_ ? 1'h1 : 1'h0;
+ assign _117_ = $signed(32'd47) >= $signed({ 25'h0000000, mb });
+ assign _118_ = _117_ ? 1'h1 : 1'h0;
+ assign _119_ = $signed(32'd48) >= $signed({ 25'h0000000, mb });
+ assign _120_ = _119_ ? 1'h1 : 1'h0;
+ assign _121_ = $signed(32'd49) >= $signed({ 25'h0000000, mb });
+ assign _122_ = _121_ ? 1'h1 : 1'h0;
+ assign _123_ = $signed(32'd50) >= $signed({ 25'h0000000, mb });
+ assign _124_ = _123_ ? 1'h1 : 1'h0;
+ assign _125_ = $signed(32'd51) >= $signed({ 25'h0000000, mb });
+ assign _126_ = _125_ ? 1'h1 : 1'h0;
+ assign _127_ = $signed(32'd52) >= $signed({ 25'h0000000, mb });
+ assign _128_ = _127_ ? 1'h1 : 1'h0;
+ assign _129_ = $signed(32'd53) >= $signed({ 25'h0000000, mb });
+ assign _130_ = _129_ ? 1'h1 : 1'h0;
+ assign _131_ = $signed(32'd54) >= $signed({ 25'h0000000, mb });
+ assign _132_ = _131_ ? 1'h1 : 1'h0;
+ assign _133_ = $signed(32'd55) >= $signed({ 25'h0000000, mb });
+ assign _134_ = _133_ ? 1'h1 : 1'h0;
+ assign _135_ = $signed(32'd56) >= $signed({ 25'h0000000, mb });
+ assign _136_ = _135_ ? 1'h1 : 1'h0;
+ assign _137_ = $signed(32'd57) >= $signed({ 25'h0000000, mb });
+ assign _138_ = _137_ ? 1'h1 : 1'h0;
+ assign _139_ = $signed(32'd58) >= $signed({ 25'h0000000, mb });
+ assign _140_ = _139_ ? 1'h1 : 1'h0;
+ assign _141_ = $signed(32'd59) >= $signed({ 25'h0000000, mb });
+ assign _142_ = _141_ ? 1'h1 : 1'h0;
+ assign _143_ = $signed(32'd60) >= $signed({ 25'h0000000, mb });
+ assign _144_ = _143_ ? 1'h1 : 1'h0;
+ assign _145_ = $signed(32'd61) >= $signed({ 25'h0000000, mb });
+ assign _146_ = _145_ ? 1'h1 : 1'h0;
+ assign _147_ = $signed(32'd62) >= $signed({ 25'h0000000, mb });
+ assign _148_ = _147_ ? 1'h1 : 1'h0;
+ assign _149_ = $signed(32'd63) >= $signed({ 25'h0000000, mb });
+ assign _150_ = _149_ ? 1'h1 : 1'h0;
+ assign _151_ = ~ me[6];
+ assign _152_ = $signed(32'd0) <= $signed({ 25'h0000000, me });
+ assign _153_ = _152_ ? 1'h1 : 1'h0;
+ assign _154_ = $signed(32'd1) <= $signed({ 25'h0000000, me });
+ assign _155_ = _154_ ? 1'h1 : 1'h0;
+ assign _156_ = $signed(32'd2) <= $signed({ 25'h0000000, me });
+ assign _157_ = _156_ ? 1'h1 : 1'h0;
+ assign _158_ = $signed(32'd3) <= $signed({ 25'h0000000, me });
+ assign _159_ = _158_ ? 1'h1 : 1'h0;
+ assign _160_ = $signed(32'd4) <= $signed({ 25'h0000000, me });
+ assign _161_ = _160_ ? 1'h1 : 1'h0;
+ assign _162_ = $signed(32'd5) <= $signed({ 25'h0000000, me });
+ assign _163_ = _162_ ? 1'h1 : 1'h0;
+ assign _164_ = $signed(32'd6) <= $signed({ 25'h0000000, me });
+ assign _165_ = _164_ ? 1'h1 : 1'h0;
+ assign _166_ = $signed(32'd7) <= $signed({ 25'h0000000, me });
+ assign _167_ = _166_ ? 1'h1 : 1'h0;
+ assign _168_ = $signed(32'd8) <= $signed({ 25'h0000000, me });
+ assign _169_ = _168_ ? 1'h1 : 1'h0;
+ assign _170_ = $signed(32'd9) <= $signed({ 25'h0000000, me });
+ assign _171_ = _170_ ? 1'h1 : 1'h0;
+ assign _172_ = $signed(32'd10) <= $signed({ 25'h0000000, me });
+ assign _173_ = _172_ ? 1'h1 : 1'h0;
+ assign _174_ = $signed(32'd11) <= $signed({ 25'h0000000, me });
+ assign _175_ = _174_ ? 1'h1 : 1'h0;
+ assign _176_ = $signed(32'd12) <= $signed({ 25'h0000000, me });
+ assign _177_ = _176_ ? 1'h1 : 1'h0;
+ assign _178_ = $signed(32'd13) <= $signed({ 25'h0000000, me });
+ assign _179_ = _178_ ? 1'h1 : 1'h0;
+ assign _180_ = $signed(32'd14) <= $signed({ 25'h0000000, me });
+ assign _181_ = _180_ ? 1'h1 : 1'h0;
+ assign _182_ = $signed(32'd15) <= $signed({ 25'h0000000, me });
+ assign _183_ = _182_ ? 1'h1 : 1'h0;
+ assign _184_ = $signed(32'd16) <= $signed({ 25'h0000000, me });
+ assign _185_ = _184_ ? 1'h1 : 1'h0;
+ assign _186_ = $signed(32'd17) <= $signed({ 25'h0000000, me });
+ assign _187_ = _186_ ? 1'h1 : 1'h0;
+ assign _188_ = $signed(32'd18) <= $signed({ 25'h0000000, me });
+ assign _189_ = _188_ ? 1'h1 : 1'h0;
+ assign _190_ = $signed(32'd19) <= $signed({ 25'h0000000, me });
+ assign _191_ = _190_ ? 1'h1 : 1'h0;
+ assign _192_ = $signed(32'd20) <= $signed({ 25'h0000000, me });
+ assign _193_ = _192_ ? 1'h1 : 1'h0;
+ assign _194_ = $signed(32'd21) <= $signed({ 25'h0000000, me });
+ assign _195_ = _194_ ? 1'h1 : 1'h0;
+ assign _196_ = $signed(32'd22) <= $signed({ 25'h0000000, me });
+ assign _197_ = _196_ ? 1'h1 : 1'h0;
+ assign _198_ = $signed(32'd23) <= $signed({ 25'h0000000, me });
+ assign _199_ = _198_ ? 1'h1 : 1'h0;
+ assign _200_ = $signed(32'd24) <= $signed({ 25'h0000000, me });
+ assign _201_ = _200_ ? 1'h1 : 1'h0;
+ assign _202_ = $signed(32'd25) <= $signed({ 25'h0000000, me });
+ assign _203_ = _202_ ? 1'h1 : 1'h0;
+ assign _204_ = $signed(32'd26) <= $signed({ 25'h0000000, me });
+ assign _205_ = _204_ ? 1'h1 : 1'h0;
+ assign _206_ = $signed(32'd27) <= $signed({ 25'h0000000, me });
+ assign _207_ = _206_ ? 1'h1 : 1'h0;
+ assign _208_ = $signed(32'd28) <= $signed({ 25'h0000000, me });
+ assign _209_ = _208_ ? 1'h1 : 1'h0;
+ assign _210_ = $signed(32'd29) <= $signed({ 25'h0000000, me });
+ assign _211_ = _210_ ? 1'h1 : 1'h0;
+ assign _212_ = $signed(32'd30) <= $signed({ 25'h0000000, me });
+ assign _213_ = _212_ ? 1'h1 : 1'h0;
+ assign _214_ = $signed(32'd31) <= $signed({ 25'h0000000, me });
+ assign _215_ = _214_ ? 1'h1 : 1'h0;
+ assign _216_ = $signed(32'd32) <= $signed({ 25'h0000000, me });
+ assign _217_ = _216_ ? 1'h1 : 1'h0;
+ assign _218_ = $signed(32'd33) <= $signed({ 25'h0000000, me });
+ assign _219_ = _218_ ? 1'h1 : 1'h0;
+ assign _220_ = $signed(32'd34) <= $signed({ 25'h0000000, me });
+ assign _221_ = _220_ ? 1'h1 : 1'h0;
+ assign _222_ = $signed(32'd35) <= $signed({ 25'h0000000, me });
+ assign _223_ = _222_ ? 1'h1 : 1'h0;
+ assign _224_ = $signed(32'd36) <= $signed({ 25'h0000000, me });
+ assign _225_ = _224_ ? 1'h1 : 1'h0;
+ assign _226_ = $signed(32'd37) <= $signed({ 25'h0000000, me });
+ assign _227_ = _226_ ? 1'h1 : 1'h0;
+ assign _228_ = $signed(32'd38) <= $signed({ 25'h0000000, me });
+ assign _229_ = _228_ ? 1'h1 : 1'h0;
+ assign _230_ = $signed(32'd39) <= $signed({ 25'h0000000, me });
+ assign _231_ = _230_ ? 1'h1 : 1'h0;
+ assign _232_ = $signed(32'd40) <= $signed({ 25'h0000000, me });
+ assign _233_ = _232_ ? 1'h1 : 1'h0;
+ assign _234_ = $signed(32'd41) <= $signed({ 25'h0000000, me });
+ assign _235_ = _234_ ? 1'h1 : 1'h0;
+ assign _236_ = $signed(32'd42) <= $signed({ 25'h0000000, me });
+ assign _237_ = _236_ ? 1'h1 : 1'h0;
+ assign _238_ = $signed(32'd43) <= $signed({ 25'h0000000, me });
+ assign _239_ = _238_ ? 1'h1 : 1'h0;
+ assign _240_ = $signed(32'd44) <= $signed({ 25'h0000000, me });
+ assign _241_ = _240_ ? 1'h1 : 1'h0;
+ assign _242_ = $signed(32'd45) <= $signed({ 25'h0000000, me });
+ assign _243_ = _242_ ? 1'h1 : 1'h0;
+ assign _244_ = $signed(32'd46) <= $signed({ 25'h0000000, me });
+ assign _245_ = _244_ ? 1'h1 : 1'h0;
+ assign _246_ = $signed(32'd47) <= $signed({ 25'h0000000, me });
+ assign _247_ = _246_ ? 1'h1 : 1'h0;
+ assign _248_ = $signed(32'd48) <= $signed({ 25'h0000000, me });
+ assign _249_ = _248_ ? 1'h1 : 1'h0;
+ assign _250_ = $signed(32'd49) <= $signed({ 25'h0000000, me });
+ assign _251_ = _250_ ? 1'h1 : 1'h0;
+ assign _252_ = $signed(32'd50) <= $signed({ 25'h0000000, me });
+ assign _253_ = _252_ ? 1'h1 : 1'h0;
+ assign _254_ = $signed(32'd51) <= $signed({ 25'h0000000, me });
+ assign _255_ = _254_ ? 1'h1 : 1'h0;
+ assign _256_ = $signed(32'd52) <= $signed({ 25'h0000000, me });
+ assign _257_ = _256_ ? 1'h1 : 1'h0;
+ assign _258_ = $signed(32'd53) <= $signed({ 25'h0000000, me });
+ assign _259_ = _258_ ? 1'h1 : 1'h0;
+ assign _260_ = $signed(32'd54) <= $signed({ 25'h0000000, me });
+ assign _261_ = _260_ ? 1'h1 : 1'h0;
+ assign _262_ = $signed(32'd55) <= $signed({ 25'h0000000, me });
+ assign _263_ = _262_ ? 1'h1 : 1'h0;
+ assign _264_ = $signed(32'd56) <= $signed({ 25'h0000000, me });
+ assign _265_ = _264_ ? 1'h1 : 1'h0;
+ assign _266_ = $signed(32'd57) <= $signed({ 25'h0000000, me });
+ assign _267_ = _266_ ? 1'h1 : 1'h0;
+ assign _268_ = $signed(32'd58) <= $signed({ 25'h0000000, me });
+ assign _269_ = _268_ ? 1'h1 : 1'h0;
+ assign _270_ = $signed(32'd59) <= $signed({ 25'h0000000, me });
+ assign _271_ = _270_ ? 1'h1 : 1'h0;
+ assign _272_ = $signed(32'd60) <= $signed({ 25'h0000000, me });
+ assign _273_ = _272_ ? 1'h1 : 1'h0;
+ assign _274_ = $signed(32'd61) <= $signed({ 25'h0000000, me });
+ assign _275_ = _274_ ? 1'h1 : 1'h0;
+ assign _276_ = $signed(32'd62) <= $signed({ 25'h0000000, me });
+ assign _277_ = _276_ ? 1'h1 : 1'h0;
+ assign _278_ = $signed(32'd63) <= $signed({ 25'h0000000, me });
+ assign _279_ = _278_ ? 1'h1 : 1'h0;
+ assign ml = _151_ ? { _153_, _155_, _157_, _159_, _161_, _163_, _165_, _167_, _169_, _171_, _173_, _175_, _177_, _179_, _181_, _183_, _185_, _187_, _189_, _191_, _193_, _195_, _197_, _199_, _201_, _203_, _205_, _207_, _209_, _211_, _213_, _215_, _217_, _219_, _221_, _223_, _225_, _227_, _229_, _231_, _233_, _235_, _237_, _239_, _241_, _243_, _245_, _247_, _249_, _251_, _253_, _255_, _257_, _259_, _261_, _263_, _265_, _267_, _269_, _271_, _273_, _275_, _277_, _279_ } : 64'h0000000000000000;
+ assign _280_ = ~ clear_right;
+ assign _281_ = clear_left & _280_;
+ assign _282_ = _281_ | right_shift;
+ assign _283_ = arith & _001_[31];
+ assign _284_ = mb[5:0] > me[5:0];
+ assign _285_ = clear_right & _284_;
+ assign _286_ = _285_ ? 1'h1 : 1'h0;
+ assign output_mode = _282_ ? { 1'h1, _283_ } : { 1'h0, _286_ };
+ assign _287_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } & ml;
+ assign _288_ = rot & _287_;
+ assign _289_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } & ml;
+ assign _290_ = ~ _289_;
+ assign _291_ = ra & _290_;
+ assign _292_ = _288_ | _291_;
+ assign _293_ = output_mode == 2'h0;
+ assign _294_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } | ml;
+ assign _295_ = rot & _294_;
+ assign _296_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } | ml;
+ assign _297_ = ~ _296_;
+ assign _298_ = ra & _297_;
+ assign _299_ = _295_ | _298_;
+ assign _300_ = output_mode == 2'h1;
+ assign _301_ = rot & { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ };
+ assign _302_ = output_mode == 2'h2;
+ assign _303_ = ~ { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ };
+ assign _304_ = rot | _303_;
+ function [63:0] \21743 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \21743 = b[63:0];
+ 3'b?1?:
+ \21743 = b[127:64];
+ 3'b1??:
+ \21743 = b[191:128];
+ default:
+ \21743 = a;
+ endcase
+ endfunction
+ assign _305_ = \21743 (_304_, { _301_, _299_, _292_ }, { _302_, _300_, _293_ });
+ assign _306_ = output_mode == 2'h3;
+ assign _307_ = ~ ml;
+ assign _308_ = rs & _307_;
+ assign _309_ = | _308_;
+ assign _310_ = _306_ ? _309_ : 1'h0;
+ assign result = _305_;
+ assign carry_out = _310_;
+endmodule
+
+module soc_4096_50000000_0_0_4_0_4_0_c832069ef22b63469d396707bc38511cc2410ddb(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ rst, system_clk, wb_dram_out, wb_ext_io_out, ext_irq_eth, uart0_rxd, uart1_rxd, spi_flash_sdat_i, jtag_tck, jtag_tdi, jtag_tms, jtag_trst, alt_reset, wb_dram_in, wb_ext_io_in, wb_ext_is_dram_csr, wb_ext_is_dram_init, wb_ext_is_eth, uart0_txd, uart1_txd, spi_flash_sck, spi_flash_cs_n, spi_flash_sdat_o, spi_flash_sdat_oe, jtag_tdo);
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
+ wire [31:0] _000_;
+ wire [33:0] _001_;
+ wire _002_;
+ wire [1:0] _003_;
+ wire _004_;
+ wire [31:0] _005_;
+ wire [31:0] _006_;
+ wire _007_;
+ wire _008_;
+ wire [1:0] _009_;
+ wire _010_;
+ wire [26:0] _011_;
+ wire [35:0] _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire [1:0] _016_;
+ wire _017_;
+ wire [63:0] _018_;
+ wire [1:0] _019_;
+ wire [29:0] _020_;
+ wire [35:0] _021_;
+ wire [1:0] _022_;
+ wire _023_;
+ wire [1:0] _024_;
+ wire _025_;
+ wire [19:0] _026_;
+ wire _027_;
+ wire _028_;
+ wire [19:0] _029_;
+ wire _030_;
+ wire [19:0] _031_;
+ wire _032_;
+ wire [19:0] _033_;
+ wire _034_;
+ wire [19:0] _035_;
+ wire _036_;
+ wire [19:0] _037_;
+ wire _038_;
+ wire [19:0] _039_;
+ wire _040_;
+ wire [19:0] _041_;
+ wire _042_;
+ wire [19:0] _043_;
+ wire _044_;
+ wire [3:0] _045_;
+ wire [3:0] _046_;
+ wire [3:0] _047_;
+ wire [3:0] _048_;
+ wire [3:0] _049_;
+ wire [3:0] _050_;
+ wire [3:0] _051_;
+ wire [3:0] _052_;
+ wire [3:0] _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire [33:0] _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire [1:0] _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire [3:0] _103_;
+ wire [3:0] _104_;
+ wire _105_;
+ wire [7:0] _106_;
+ wire _107_;
+ wire [7:0] _108_;
+ wire _109_;
+ wire [1:0] _110_;
+ wire [1:0] _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire [3:0] _116_;
+ wire _117_;
+ wire [3:0] _118_;
+ wire _119_;
+ wire [3:0] _120_;
+ wire _121_;
+ wire [3:0] _122_;
+ wire _123_;
+ wire [3:0] _124_;
+ wire _125_;
+ wire [1:0] _126_;
+ wire [1:0] _127_;
+ wire [1:0] _128_;
+ wire [1:0] _129_;
+ wire [1:0] _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire [31:0] _141_;
+ wire [31:0] _142_;
+ wire _143_;
+ wire [35:0] _144_;
+ wire [1:0] _145_;
+ wire _146_;
+ wire [68:0] _147_;
+ wire [1:0] _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire [31:0] _154_;
+ wire [31:0] _155_;
+ wire [1:0] _156_;
+ wire _157_;
+ wire [35:0] _158_;
+ wire _159_;
+ wire _160_;
+ wire [1:0] _161_;
+ wire _162_;
+ wire [1:0] _163_;
+ wire _164_;
+ wire [37:0] _165_;
+ wire [1:0] _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ input alt_reset;
+ reg alt_reset_d;
+ wire core_ext_irq;
+ wire dmi_ack;
+ wire [7:0] dmi_addr;
+ wire dmi_core_ack;
+ wire [63:0] dmi_core_dout;
+ wire dmi_core_req;
+ wire [63:0] dmi_din;
+ wire [63:0] dmi_dout;
+ wire dmi_req;
+ wire dmi_wb_ack;
+ wire [63:0] dmi_wb_dout;
+ wire dmi_wb_req;
+ wire dmi_wr;
+ wire do_core_reset;
+ wire dram_at_0;
+ input ext_irq_eth;
+ wire [11:0] ics_to_icp;
+ input jtag_tck;
+ input jtag_tdi;
+ output jtag_tdo;
+ input jtag_tms;
+ input jtag_trst;
+ input rst;
+ reg rst_bram = 1'h1;
+ reg rst_core = 1'h1;
+ reg rst_dtm = 1'h1;
+ reg rst_spi = 1'h1;
+ reg rst_uart = 1'h1;
+ reg rst_wbar = 1'h1;
+ reg rst_wbdb = 1'h1;
+ reg rst_xics = 1'h1;
+ reg \slave_io_latch.has_top = 1'h0;
+ reg [1:0] \slave_io_latch.state = 2'h0;
+ output spi_flash_cs_n;
+ output spi_flash_sck;
+ input [3:0] spi_flash_sdat_i;
+ output [3:0] spi_flash_sdat_o;
+ output [3:0] spi_flash_sdat_oe;
+ input system_clk;
+ wire \uart0_16550.irq_l ;
+ wire [7:0] uart0_dat8;
+ reg uart0_irq;
+ input uart0_rxd;
+ output uart0_txd;
+ input uart1_rxd;
+ output uart1_txd;
+ wire [65:0] wb_bram_out;
+ output [106:0] wb_dram_in;
+ input [65:0] wb_dram_out;
+ output [68:0] wb_ext_io_in;
+ input [33:0] wb_ext_io_out;
+ output wb_ext_is_dram_csr;
+ output wb_ext_is_dram_init;
+ output wb_ext_is_eth;
+ reg [65:0] wb_io_out;
+ wire [65:0] wb_master_in;
+ wire [106:0] wb_master_out;
+ wire [197:0] wb_masters_in;
+ wire [33:0] wb_sio_in;
+ reg [68:0] wb_sio_out;
+ wire wb_spiflash_is_map;
+ wire wb_spiflash_is_reg;
+ wire [33:0] wb_spiflash_out;
+ wire [33:0] wb_syscon_out;
+ wire [33:0] wb_xics_icp_out;
+ wire [33:0] wb_xics_ics_out;
+ wire [106:0] wishbone_dcore_out;
+ wire [106:0] wishbone_debug_out;
+ wire [106:0] wishbone_icore_out;
+ assign _116_ = { wb_master_out[31:29], dram_at_0 } & 4'hf;
+ assign _117_ = _116_ == 4'h0;
+ assign _118_ = { wb_master_out[31:29], dram_at_0 } & 4'hf;
+ assign _119_ = _118_ == 4'h1;
+ assign _120_ = { wb_master_out[31:29], dram_at_0 } & 4'hc;
+ assign _121_ = _120_ == 4'h4;
+ assign _122_ = { wb_master_out[31:29], dram_at_0 } & 4'hc;
+ assign _123_ = _122_ == 4'h8;
+ assign _124_ = { wb_master_out[31:29], dram_at_0 } & 4'hc;
+ assign _125_ = _124_ == 4'hc;
+ assign _126_ = _125_ ? 2'h2 : 2'h3;
+ assign _127_ = _123_ ? 2'h0 : _126_;
+ assign _128_ = _121_ ? 2'h1 : _127_;
+ assign _129_ = _119_ ? 2'h1 : _128_;
+ assign _130_ = _117_ ? 2'h0 : _129_;
+ assign _131_ = _130_ == 2'h3;
+ assign _132_ = _130_ == 2'h0;
+ assign _133_ = _130_ == 2'h1;
+ assign _134_ = _130_ == 2'h2;
+ function [0:0] \161 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \161 = b[0:0];
+ 4'b??1?:
+ \161 = b[1:1];
+ 4'b?1??:
+ \161 = b[2:2];
+ 4'b1???:
+ \161 = b[3:3];
+ default:
+ \161 = a;
+ endcase
+ endfunction
+ assign _135_ = \161 (1'hx, { 1'h0, wb_master_out[104], 2'h0 }, { _134_, _133_, _132_, _131_ });
+ function [65:0] \164 ;
+ input [65:0] a;
+ input [263:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \164 = b[65:0];
+ 4'b??1?:
+ \164 = b[131:66];
+ 4'b?1??:
+ \164 = b[197:132];
+ 4'b1???:
+ \164 = b[263:198];
+ default:
+ \164 = a;
+ endcase
+ endfunction
+ assign wb_master_in = \164 (66'hxxxxxxxxxxxxxxxxx, { wb_io_out, wb_dram_out, wb_bram_out, 66'h00000000000000000 }, { _134_, _133_, _132_, _131_ });
+ function [0:0] \166 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \166 = b[0:0];
+ 4'b??1?:
+ \166 = b[1:1];
+ 4'b?1??:
+ \166 = b[2:2];
+ 4'b1???:
+ \166 = b[3:3];
+ default:
+ \166 = a;
+ endcase
+ endfunction
+ assign _136_ = \166 (1'hx, { wb_master_out[104], 3'h0 }, { _134_, _133_, _132_, _131_ });
+ function [0:0] \168 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \168 = b[0:0];
+ 4'b??1?:
+ \168 = b[1:1];
+ 4'b?1??:
+ \168 = b[2:2];
+ 4'b1???:
+ \168 = b[3:3];
+ default:
+ \168 = a;
+ endcase
+ endfunction
+ assign _137_ = \168 (1'hx, { 2'h0, wb_master_out[104], 1'h0 }, { _134_, _133_, _132_, _131_ });
+ assign _138_ = _136_ & wb_master_out[105];
+ assign _139_ = wb_master_out[103:100] != 4'h0;
+ assign _140_ = wb_master_out[99:96] != 4'h0;
+ assign _141_ = wb_master_out[106] ? wb_master_out[63:32] : wb_sio_out[61:30];
+ assign _142_ = wb_master_out[106] ? wb_master_out[95:64] : wb_sio_out[61:30];
+ assign _143_ = _140_ ? 1'h0 : 1'h1;
+ assign _144_ = _140_ ? { wb_master_out[99:96], _141_ } : { wb_master_out[103:100], _142_ };
+ assign _145_ = _140_ ? 2'h1 : 2'h2;
+ assign _146_ = _138_ ? 1'h1 : wb_io_out[65];
+ assign _147_ = _138_ ? { wb_master_out[106], 2'h3, _144_, wb_master_out[29:3], _143_, 2'h0 } : wb_sio_out;
+ assign _148_ = _138_ ? _145_ : \slave_io_latch.state ;
+ assign _149_ = _138_ ? _139_ : \slave_io_latch.has_top ;
+ assign _150_ = \slave_io_latch.state == 2'h0;
+ assign _151_ = ~ wb_sio_in[33];
+ assign _152_ = _151_ ? 1'h0 : wb_sio_out[67];
+ assign _153_ = ~ wb_sio_out[68];
+ assign _154_ = _162_ ? wb_sio_in[31:0] : wb_io_out[31:0];
+ assign _155_ = wb_master_out[106] ? wb_master_out[95:64] : wb_sio_out[61:30];
+ assign _156_ = \slave_io_latch.has_top ? wb_io_out[65:64] : 2'h1;
+ assign _157_ = _164_ ? 1'h1 : wb_sio_out[2];
+ assign _158_ = \slave_io_latch.has_top ? { wb_master_out[103:100], _155_ } : wb_sio_out[65:30];
+ assign _159_ = \slave_io_latch.has_top ? wb_sio_out[66] : 1'h0;
+ assign _160_ = \slave_io_latch.has_top ? 1'h1 : _152_;
+ assign _161_ = \slave_io_latch.has_top ? 2'h2 : 2'h0;
+ assign _162_ = wb_sio_in[32] & _153_;
+ assign _163_ = wb_sio_in[32] ? _156_ : wb_io_out[65:64];
+ assign _164_ = wb_sio_in[32] & \slave_io_latch.has_top ;
+ assign _165_ = wb_sio_in[32] ? { _160_, _159_, _158_ } : { _152_, wb_sio_out[66:30] };
+ assign _166_ = wb_sio_in[32] ? _161_ : \slave_io_latch.state ;
+ assign _167_ = \slave_io_latch.state == 2'h1;
+ assign _168_ = ~ wb_sio_in[33];
+ assign _169_ = _168_ ? 1'h0 : wb_sio_out[67];
+ assign _170_ = ~ wb_sio_out[68];
+ assign _000_ = _170_ ? wb_sio_in[31:0] : wb_io_out[63:32];
+ assign _001_ = wb_sio_in[32] ? { 2'h1, _000_ } : wb_io_out[65:32];
+ assign _002_ = wb_sio_in[32] ? 1'h0 : wb_sio_out[66];
+ assign _003_ = wb_sio_in[32] ? 2'h0 : \slave_io_latch.state ;
+ assign _004_ = \slave_io_latch.state == 2'h2;
+ function [31:0] \301 ;
+ input [31:0] a;
+ input [95:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \301 = b[31:0];
+ 3'b?1?:
+ \301 = b[63:32];
+ 3'b1??:
+ \301 = b[95:64];
+ default:
+ \301 = a;
+ endcase
+ endfunction
+ assign _005_ = \301 (32'hxxxxxxxx, { wb_io_out[31:0], _154_, wb_io_out[31:0] }, { _004_, _167_, _150_ });
+ function [31:0] \305 ;
+ input [31:0] a;
+ input [95:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \305 = b[31:0];
+ 3'b?1?:
+ \305 = b[63:32];
+ 3'b1??:
+ \305 = b[95:64];
+ default:
+ \305 = a;
+ endcase
+ endfunction
+ assign _006_ = \305 (32'hxxxxxxxx, { _001_[31:0], wb_io_out[63:32], wb_io_out[63:32] }, { _004_, _167_, _150_ });
+ function [0:0] \309 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \309 = b[0:0];
+ 3'b?1?:
+ \309 = b[1:1];
+ 3'b1??:
+ \309 = b[2:2];
+ default:
+ \309 = a;
+ endcase
+ endfunction
+ assign _007_ = \309 (1'hx, { _001_[32], _163_[0], 1'h0 }, { _004_, _167_, _150_ });
+ function [0:0] \313 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \313 = b[0:0];
+ 3'b?1?:
+ \313 = b[1:1];
+ 3'b1??:
+ \313 = b[2:2];
+ default:
+ \313 = a;
+ endcase
+ endfunction
+ assign _008_ = \313 (1'hx, { _001_[33], _163_[1], _146_ }, { _004_, _167_, _150_ });
+ function [1:0] \317 ;
+ input [1:0] a;
+ input [5:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \317 = b[1:0];
+ 3'b?1?:
+ \317 = b[3:2];
+ 3'b1??:
+ \317 = b[5:4];
+ default:
+ \317 = a;
+ endcase
+ endfunction
+ assign _009_ = \317 (2'hx, { wb_sio_out[1:0], wb_sio_out[1:0], _147_[1:0] }, { _004_, _167_, _150_ });
+ function [0:0] \321 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \321 = b[0:0];
+ 3'b?1?:
+ \321 = b[1:1];
+ 3'b1??:
+ \321 = b[2:2];
+ default:
+ \321 = a;
+ endcase
+ endfunction
+ assign _010_ = \321 (1'hx, { wb_sio_out[2], _157_, _147_[2] }, { _004_, _167_, _150_ });
+ function [26:0] \325 ;
+ input [26:0] a;
+ input [80:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \325 = b[26:0];
+ 3'b?1?:
+ \325 = b[53:27];
+ 3'b1??:
+ \325 = b[80:54];
+ default:
+ \325 = a;
+ endcase
+ endfunction
+ assign _011_ = \325 (27'hxxxxxxx, { wb_sio_out[29:3], wb_sio_out[29:3], _147_[29:3] }, { _004_, _167_, _150_ });
+ function [35:0] \330 ;
+ input [35:0] a;
+ input [107:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \330 = b[35:0];
+ 3'b?1?:
+ \330 = b[71:36];
+ 3'b1??:
+ \330 = b[107:72];
+ default:
+ \330 = a;
+ endcase
+ endfunction
+ assign _012_ = \330 (36'hxxxxxxxxx, { wb_sio_out[65:30], _165_[35:0], _147_[65:30] }, { _004_, _167_, _150_ });
+ function [0:0] \334 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \334 = b[0:0];
+ 3'b?1?:
+ \334 = b[1:1];
+ 3'b1??:
+ \334 = b[2:2];
+ default:
+ \334 = a;
+ endcase
+ endfunction
+ assign _013_ = \334 (1'hx, { _002_, _165_[36], _147_[66] }, { _004_, _167_, _150_ });
+ function [0:0] \338 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \338 = b[0:0];
+ 3'b?1?:
+ \338 = b[1:1];
+ 3'b1??:
+ \338 = b[2:2];
+ default:
+ \338 = a;
+ endcase
+ endfunction
+ assign _014_ = \338 (1'hx, { _169_, _165_[37], _147_[67] }, { _004_, _167_, _150_ });
+ function [0:0] \342 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \342 = b[0:0];
+ 3'b?1?:
+ \342 = b[1:1];
+ 3'b1??:
+ \342 = b[2:2];
+ default:
+ \342 = a;
+ endcase
+ endfunction
+ assign _015_ = \342 (1'hx, { wb_sio_out[68], wb_sio_out[68], _147_[68] }, { _004_, _167_, _150_ });
+ function [1:0] \344 ;
+ input [1:0] a;
+ input [5:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \344 = b[1:0];
+ 3'b?1?:
+ \344 = b[3:2];
+ 3'b1??:
+ \344 = b[5:4];
+ default:
+ \344 = a;
+ endcase
+ endfunction
+ assign _016_ = \344 (2'hx, { _003_, _166_, _148_ }, { _004_, _167_, _150_ });
+ function [0:0] \346 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \346 = b[0:0];
+ 3'b?1?:
+ \346 = b[1:1];
+ 3'b1??:
+ \346 = b[2:2];
+ default:
+ \346 = a;
+ endcase
+ endfunction
+ assign _017_ = \346 (1'hx, { \slave_io_latch.has_top , \slave_io_latch.has_top , _149_ }, { _004_, _167_, _150_ });
+ assign _018_ = rst ? wb_io_out[63:0] : { _006_, _005_ };
+ assign _019_ = rst ? 2'h0 : { _008_, _007_ };
+ assign _020_ = rst ? 30'h00000000 : { _011_, _010_, _009_ };
+ assign _021_ = rst ? wb_sio_out[65:30] : _012_;
+ assign _022_ = rst ? 2'h0 : { _014_, _013_ };
+ assign _023_ = rst ? wb_sio_out[68] : _015_;
+ assign _024_ = rst ? 2'h0 : _016_;
+ assign _025_ = rst ? 1'h0 : _017_;
+ always @(posedge system_clk)
+ wb_io_out <= { _019_, _018_ };
+ always @(posedge system_clk)
+ wb_sio_out <= { _023_, _022_, _021_, _020_ };
+ always @(posedge system_clk)
+ \slave_io_latch.state <= _024_;
+ always @(posedge system_clk)
+ \slave_io_latch.has_top <= _025_;
+ assign _026_ = { 2'h3, wb_sio_out[29:12] } & 20'hff000;
+ assign _027_ = _026_ == 20'hff000;
+ assign _028_ = _027_ & 1'h1;
+ assign _029_ = { 2'h3, wb_sio_out[29:12] } & 20'hf0000;
+ assign _030_ = _029_ == 20'hf0000;
+ assign _031_ = { 2'h3, wb_sio_out[29:12] } & 20'hfffff;
+ assign _032_ = _031_ == 20'hc0000;
+ assign _033_ = { 2'h3, wb_sio_out[29:12] } & 20'hfffff;
+ assign _034_ = _033_ == 20'hc0002;
+ assign _035_ = { 2'h3, wb_sio_out[29:12] } & 20'hfffff;
+ assign _036_ = _035_ == 20'hc0003;
+ assign _037_ = { 2'h3, wb_sio_out[29:12] } & 20'hff000;
+ assign _038_ = _037_ == 20'hc8000;
+ assign _039_ = { 2'h3, wb_sio_out[29:12] } & 20'hfffff;
+ assign _040_ = _039_ == 20'hc0004;
+ assign _041_ = { 2'h3, wb_sio_out[29:12] } & 20'hfffff;
+ assign _042_ = _041_ == 20'hc0005;
+ assign _043_ = { 2'h3, wb_sio_out[29:12] } & 20'hfffff;
+ assign _044_ = _043_ == 20'hc0006;
+ assign _045_ = _044_ ? 4'h5 : 4'h8;
+ assign _046_ = _042_ ? 4'h3 : _045_;
+ assign _047_ = _040_ ? 4'h2 : _046_;
+ assign _048_ = _038_ ? 4'h7 : _047_;
+ assign _049_ = _036_ ? 4'h4 : _048_;
+ assign _050_ = _034_ ? 4'h1 : _049_;
+ assign _051_ = _032_ ? 4'h0 : _050_;
+ assign _052_ = _030_ ? 4'h6 : _051_;
+ assign _053_ = _028_ ? 4'h7 : _052_;
+ assign _054_ = wb_sio_out[67] & wb_sio_out[66];
+ assign _055_ = wb_sio_out[29] & 1'h1;
+ assign _056_ = wb_sio_out[23:16] == 8'h00;
+ assign _057_ = _056_ & 1'h1;
+ assign _058_ = wb_sio_out[23:16] == 8'h02;
+ assign _059_ = _058_ & 1'h1;
+ assign _060_ = wb_sio_out[23:16] == 8'h03;
+ assign _061_ = _060_ & 1'h1;
+ assign _062_ = _061_ ? 1'h1 : 1'h0;
+ assign _063_ = _061_ ? 1'h1 : 1'h0;
+ assign _064_ = _059_ ? 1'h1 : _062_;
+ assign _065_ = _059_ ? 1'h1 : _063_;
+ assign _066_ = _057_ ? 1'h1 : 1'h0;
+ assign _067_ = _057_ ? 1'h0 : _064_;
+ assign _068_ = _057_ ? 1'h1 : _065_;
+ assign _069_ = _055_ ? 1'h0 : _066_;
+ assign _070_ = _055_ ? 1'h1 : 1'h0;
+ assign _071_ = _055_ ? 1'h0 : _067_;
+ assign _072_ = _055_ ? 1'h1 : _068_;
+ assign _073_ = _072_ ? wb_sio_out[66] : 1'h0;
+ assign _074_ = _072_ ? wb_ext_io_out : { 1'h0, _054_, 32'hffffffff };
+ assign _075_ = _053_ == 4'h7;
+ assign _076_ = _053_ == 4'h0;
+ assign _077_ = _053_ == 4'h1;
+ assign _078_ = _053_ == 4'h2;
+ assign _079_ = _053_ == 4'h3;
+ assign _080_ = _053_ == 4'h4;
+ assign _081_ = _053_ == 4'h6;
+ assign _082_ = _053_ == 4'h5;
+ function [0:0] \560 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \560 = b[0:0];
+ 8'b??????1?:
+ \560 = b[1:1];
+ 8'b?????1??:
+ \560 = b[2:2];
+ 8'b????1???:
+ \560 = b[3:3];
+ 8'b???1????:
+ \560 = b[4:4];
+ 8'b??1?????:
+ \560 = b[5:5];
+ 8'b?1??????:
+ \560 = b[6:6];
+ 8'b1???????:
+ \560 = b[7:7];
+ default:
+ \560 = a;
+ endcase
+ endfunction
+ assign _083_ = \560 (1'h0, { 7'h00, _073_ }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \562 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \562 = b[0:0];
+ 8'b??????1?:
+ \562 = b[1:1];
+ 8'b?????1??:
+ \562 = b[2:2];
+ 8'b????1???:
+ \562 = b[3:3];
+ 8'b???1????:
+ \562 = b[4:4];
+ 8'b??1?????:
+ \562 = b[5:5];
+ 8'b?1??????:
+ \562 = b[6:6];
+ 8'b1???????:
+ \562 = b[7:7];
+ default:
+ \562 = a;
+ endcase
+ endfunction
+ assign _084_ = \562 (1'h0, { 7'h00, _069_ }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \565 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \565 = b[0:0];
+ 8'b??????1?:
+ \565 = b[1:1];
+ 8'b?????1??:
+ \565 = b[2:2];
+ 8'b????1???:
+ \565 = b[3:3];
+ 8'b???1????:
+ \565 = b[4:4];
+ 8'b??1?????:
+ \565 = b[5:5];
+ 8'b?1??????:
+ \565 = b[6:6];
+ 8'b1???????:
+ \565 = b[7:7];
+ default:
+ \565 = a;
+ endcase
+ endfunction
+ assign _085_ = \565 (1'h0, { 7'h00, _070_ }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \568 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \568 = b[0:0];
+ 8'b??????1?:
+ \568 = b[1:1];
+ 8'b?????1??:
+ \568 = b[2:2];
+ 8'b????1???:
+ \568 = b[3:3];
+ 8'b???1????:
+ \568 = b[4:4];
+ 8'b??1?????:
+ \568 = b[5:5];
+ 8'b?1??????:
+ \568 = b[6:6];
+ 8'b1???????:
+ \568 = b[7:7];
+ default:
+ \568 = a;
+ endcase
+ endfunction
+ assign _086_ = \568 (1'h0, { 7'h00, _071_ }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [33:0] \571 ;
+ input [33:0] a;
+ input [271:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \571 = b[33:0];
+ 8'b??????1?:
+ \571 = b[67:34];
+ 8'b?????1??:
+ \571 = b[101:68];
+ 8'b????1???:
+ \571 = b[135:102];
+ 8'b???1????:
+ \571 = b[169:136];
+ 8'b??1?????:
+ \571 = b[203:170];
+ 8'b?1??????:
+ \571 = b[237:204];
+ 8'b1???????:
+ \571 = b[271:238];
+ default:
+ \571 = a;
+ endcase
+ endfunction
+ assign wb_sio_in = \571 ({ 1'h0, _054_, 32'hffffffff }, { wb_spiflash_out, wb_spiflash_out, 1'h0, _100_, 32'h00000000, wb_xics_ics_out, wb_xics_icp_out, _099_, _095_, 24'h000000, uart0_dat8, wb_syscon_out, _074_ }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \572 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \572 = b[0:0];
+ 8'b??????1?:
+ \572 = b[1:1];
+ 8'b?????1??:
+ \572 = b[2:2];
+ 8'b????1???:
+ \572 = b[3:3];
+ 8'b???1????:
+ \572 = b[4:4];
+ 8'b??1?????:
+ \572 = b[5:5];
+ 8'b?1??????:
+ \572 = b[6:6];
+ 8'b1???????:
+ \572 = b[7:7];
+ default:
+ \572 = a;
+ endcase
+ endfunction
+ assign _087_ = \572 (1'h0, { 6'h00, wb_sio_out[66], 1'h0 }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \573 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \573 = b[0:0];
+ 8'b??????1?:
+ \573 = b[1:1];
+ 8'b?????1??:
+ \573 = b[2:2];
+ 8'b????1???:
+ \573 = b[3:3];
+ 8'b???1????:
+ \573 = b[4:4];
+ 8'b??1?????:
+ \573 = b[5:5];
+ 8'b?1??????:
+ \573 = b[6:6];
+ 8'b1???????:
+ \573 = b[7:7];
+ default:
+ \573 = a;
+ endcase
+ endfunction
+ assign _088_ = \573 (1'h0, { 5'h00, wb_sio_out[66], 2'h0 }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \574 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \574 = b[0:0];
+ 8'b??????1?:
+ \574 = b[1:1];
+ 8'b?????1??:
+ \574 = b[2:2];
+ 8'b????1???:
+ \574 = b[3:3];
+ 8'b???1????:
+ \574 = b[4:4];
+ 8'b??1?????:
+ \574 = b[5:5];
+ 8'b?1??????:
+ \574 = b[6:6];
+ 8'b1???????:
+ \574 = b[7:7];
+ default:
+ \574 = a;
+ endcase
+ endfunction
+ assign _089_ = \574 (1'h0, { 2'h0, wb_sio_out[66], 5'h00 }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [1:0] \576 ;
+ input [1:0] a;
+ input [15:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \576 = b[1:0];
+ 8'b??????1?:
+ \576 = b[3:2];
+ 8'b?????1??:
+ \576 = b[5:4];
+ 8'b????1???:
+ \576 = b[7:6];
+ 8'b???1????:
+ \576 = b[9:8];
+ 8'b??1?????:
+ \576 = b[11:10];
+ 8'b?1??????:
+ \576 = b[13:12];
+ 8'b1???????:
+ \576 = b[15:14];
+ default:
+ \576 = a;
+ endcase
+ endfunction
+ assign _090_ = \576 (wb_sio_out[29:28], { wb_sio_out[29:28], 2'h0, wb_sio_out[29:28], wb_sio_out[29:28], wb_sio_out[29:28], wb_sio_out[29:28], wb_sio_out[29:28], wb_sio_out[29:28] }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \577 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \577 = b[0:0];
+ 8'b??????1?:
+ \577 = b[1:1];
+ 8'b?????1??:
+ \577 = b[2:2];
+ 8'b????1???:
+ \577 = b[3:3];
+ 8'b???1????:
+ \577 = b[4:4];
+ 8'b??1?????:
+ \577 = b[5:5];
+ 8'b?1??????:
+ \577 = b[6:6];
+ 8'b1???????:
+ \577 = b[7:7];
+ default:
+ \577 = a;
+ endcase
+ endfunction
+ assign _091_ = \577 (1'h0, { wb_sio_out[66], wb_sio_out[66], 6'h00 }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \582 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \582 = b[0:0];
+ 8'b??????1?:
+ \582 = b[1:1];
+ 8'b?????1??:
+ \582 = b[2:2];
+ 8'b????1???:
+ \582 = b[3:3];
+ 8'b???1????:
+ \582 = b[4:4];
+ 8'b??1?????:
+ \582 = b[5:5];
+ 8'b?1??????:
+ \582 = b[6:6];
+ 8'b1???????:
+ \582 = b[7:7];
+ default:
+ \582 = a;
+ endcase
+ endfunction
+ assign wb_spiflash_is_reg = \582 (1'h0, 8'h80, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \586 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \586 = b[0:0];
+ 8'b??????1?:
+ \586 = b[1:1];
+ 8'b?????1??:
+ \586 = b[2:2];
+ 8'b????1???:
+ \586 = b[3:3];
+ 8'b???1????:
+ \586 = b[4:4];
+ 8'b??1?????:
+ \586 = b[5:5];
+ 8'b?1??????:
+ \586 = b[6:6];
+ 8'b1???????:
+ \586 = b[7:7];
+ default:
+ \586 = a;
+ endcase
+ endfunction
+ assign wb_spiflash_is_map = \586 (1'h0, 8'h40, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \588 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \588 = b[0:0];
+ 8'b??????1?:
+ \588 = b[1:1];
+ 8'b?????1??:
+ \588 = b[2:2];
+ 8'b????1???:
+ \588 = b[3:3];
+ 8'b???1????:
+ \588 = b[4:4];
+ 8'b??1?????:
+ \588 = b[5:5];
+ 8'b?1??????:
+ \588 = b[6:6];
+ 8'b1???????:
+ \588 = b[7:7];
+ default:
+ \588 = a;
+ endcase
+ endfunction
+ assign _092_ = \588 (1'h0, { 4'h0, wb_sio_out[66], 3'h0 }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ function [0:0] \589 ;
+ input [0:0] a;
+ input [7:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \589 = b[0:0];
+ 8'b??????1?:
+ \589 = b[1:1];
+ 8'b?????1??:
+ \589 = b[2:2];
+ 8'b????1???:
+ \589 = b[3:3];
+ 8'b???1????:
+ \589 = b[4:4];
+ 8'b??1?????:
+ \589 = b[5:5];
+ 8'b?1??????:
+ \589 = b[6:6];
+ 8'b1???????:
+ \589 = b[7:7];
+ default:
+ \589 = a;
+ endcase
+ endfunction
+ assign _093_ = \589 (1'h0, { 3'h0, wb_sio_out[66], 4'h0 }, { _082_, _081_, _080_, _079_, _078_, _077_, _076_, _075_ });
+ always @(posedge system_clk)
+ uart0_irq <= \uart0_16550.irq_l ;
+ assign _099_ = ~ _095_;
+ assign _100_ = _089_ & wb_sio_out[67];
+ assign _106_ = dmi_addr & 8'hfc;
+ assign _107_ = _106_ == 8'h00;
+ assign _108_ = dmi_addr & 8'hf0;
+ assign _109_ = _108_ == 8'h10;
+ assign _110_ = _109_ ? 2'h1 : 2'h2;
+ assign _111_ = _107_ ? 2'h0 : _110_;
+ assign _112_ = _111_ == 2'h0;
+ assign _113_ = _111_ == 2'h1;
+ function [63:0] \667 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \667 = b[63:0];
+ 2'b1?:
+ \667 = b[127:64];
+ default:
+ \667 = a;
+ endcase
+ endfunction
+ assign dmi_din = \667 (64'hffffffffffffffff, { dmi_core_dout, dmi_wb_dout }, { _113_, _112_ });
+ function [0:0] \668 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \668 = b[0:0];
+ 2'b1?:
+ \668 = b[1:1];
+ default:
+ \668 = a;
+ endcase
+ endfunction
+ assign dmi_ack = \668 (dmi_req, { dmi_core_ack, dmi_wb_ack }, { _113_, _112_ });
+ function [0:0] \670 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \670 = b[0:0];
+ 2'b1?:
+ \670 = b[1:1];
+ default:
+ \670 = a;
+ endcase
+ endfunction
+ assign dmi_wb_req = \670 (1'h0, { 1'h0, dmi_req }, { _113_, _112_ });
+ function [0:0] \673 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \673 = b[0:0];
+ 2'b1?:
+ \673 = b[1:1];
+ default:
+ \673 = a;
+ endcase
+ endfunction
+ assign dmi_core_req = \673 (1'h0, { dmi_req, 1'h0 }, { _113_, _112_ });
+ assign _114_ = rst | do_core_reset;
+ always @(posedge system_clk)
+ rst_core <= _114_;
+ always @(posedge system_clk)
+ rst_uart <= rst;
+ always @(posedge system_clk)
+ rst_xics <= rst;
+ always @(posedge system_clk)
+ rst_spi <= rst;
+ always @(posedge system_clk)
+ rst_bram <= rst;
+ always @(posedge system_clk)
+ rst_dtm <= rst;
+ always @(posedge system_clk)
+ rst_wbar <= rst;
+ always @(posedge system_clk)
+ rst_wbdb <= rst;
+ always @(posedge system_clk)
+ alt_reset_d <= alt_reset;
+ wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 \bram.bram0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .clk(system_clk),
+ .rst(rst_bram),
+ .wishbone_in({ wb_master_out[106:105], _137_, wb_master_out[103:0] }),
+ .wishbone_out(wb_bram_out)
+ );
+ dmi_dtm_jtag_8_64 \dmi_jtag.dtm (
+ .dmi_ack(dmi_ack),
+ .dmi_addr(dmi_addr),
+ .dmi_din(dmi_din),
+ .dmi_dout(dmi_dout),
+ .dmi_req(dmi_req),
+ .dmi_wr(dmi_wr),
+ .jtag_tck(jtag_tck),
+ .jtag_tdi(jtag_tdi),
+ .jtag_tdo(_105_),
+ .jtag_tms(jtag_tms),
+ .jtag_trst(jtag_trst),
+ .sys_clk(system_clk),
+ .sys_reset(rst_dtm)
+ );
+ core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e processor (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .alt_reset(alt_reset_d),
+ .clk(system_clk),
+ .dmi_ack(dmi_core_ack),
+ .dmi_addr(dmi_addr[3:0]),
+ .dmi_din(dmi_dout),
+ .dmi_dout(dmi_core_dout),
+ .dmi_req(dmi_core_req),
+ .dmi_wr(dmi_wr),
+ .ext_irq(core_ext_irq),
+ .rst(rst_core),
+ .terminated_out(_115_),
+ .wishbone_data_in(wb_masters_in[197:132]),
+ .wishbone_data_out(wishbone_dcore_out),
+ .wishbone_insn_in(wb_masters_in[131:66]),
+ .wishbone_insn_out(wishbone_icore_out)
+ );
+ spi_flash_ctrl_4_4_1489f923c4dca729178b3e3233458550d8dddf29 \spiflash_gen.spiflash (
+ .clk(system_clk),
+ .cs_n(_102_),
+ .rst(rst_spi),
+ .sck(_101_),
+ .sdat_i(spi_flash_sdat_i),
+ .sdat_o(_103_),
+ .sdat_oe(_104_),
+ .wb_in({ wb_sio_out[68:67], _091_, wb_sio_out[65:30], _090_, wb_sio_out[27:0] }),
+ .wb_out(wb_spiflash_out),
+ .wb_sel_map(wb_spiflash_is_map),
+ .wb_sel_reg(wb_spiflash_is_reg)
+ );
+ syscon_50000000_4096_0_0_0_d1a6c63d707d362dd5f27f0b0ee5a7d91add1255 syscon0 (
+ .clk(system_clk),
+ .core_reset(do_core_reset),
+ .dram_at_0(dram_at_0),
+ .rst(rst),
+ .soc_reset(_094_),
+ .wishbone_in({ wb_sio_out[68:67], _087_, wb_sio_out[65:0] }),
+ .wishbone_out(wb_syscon_out)
+ );
+ uart_top \uart0_16550.uart0 (
+ .cts_pad_i(1'h1),
+ .dcd_pad_i(1'h1),
+ .dsr_pad_i(1'h1),
+ .dtr_pad_o(_098_),
+ .int_o(\uart0_16550.irq_l ),
+ .ri_pad_i(1'h0),
+ .rts_pad_o(_097_),
+ .srx_pad_i(uart0_rxd),
+ .stx_pad_o(_096_),
+ .wb_ack_o(_095_),
+ .wb_adr_i(wb_sio_out[4:2]),
+ .wb_clk_i(system_clk),
+ .wb_cyc_i(_088_),
+ .wb_dat_i(wb_sio_out[37:30]),
+ .wb_dat_o(uart0_dat8),
+ .wb_rst_i(rst_uart),
+ .wb_stb_i(wb_sio_out[67]),
+ .wb_we_i(wb_sio_out[68])
+ );
+ wishbone_arbiter_3 wishbone_arbiter_0 (
+ .clk(system_clk),
+ .rst(rst_wbar),
+ .wb_masters_in({ wishbone_dcore_out, wishbone_icore_out, wishbone_debug_out }),
+ .wb_masters_out(wb_masters_in),
+ .wb_slave_in(wb_master_in),
+ .wb_slave_out(wb_master_out)
+ );
+ wishbone_debug_master wishbone_debug (
+ .clk(system_clk),
+ .dmi_ack(dmi_wb_ack),
+ .dmi_addr(dmi_addr[1:0]),
+ .dmi_din(dmi_dout),
+ .dmi_dout(dmi_wb_dout),
+ .dmi_req(dmi_wb_req),
+ .dmi_wr(dmi_wr),
+ .rst(rst_wbdb),
+ .wb_in(wb_masters_in[65:0]),
+ .wb_out(wishbone_debug_out)
+ );
+ xics_icp xics_icp (
+ .clk(system_clk),
+ .core_irq_out(core_ext_irq),
+ .ics_in(ics_to_icp),
+ .rst(rst_xics),
+ .wb_in({ wb_sio_out[68:67], _092_, wb_sio_out[65:30], 22'h000000, wb_sio_out[7:0] }),
+ .wb_out(wb_xics_icp_out)
+ );
+ xics_ics_16_3 xics_ics (
+ .clk(system_clk),
+ .icp_out(ics_to_icp),
+ .int_level_in({ 14'h0000, ext_irq_eth, uart0_irq }),
+ .rst(rst_xics),
+ .wb_in({ wb_sio_out[68:67], _093_, wb_sio_out[65:30], 18'h00000, wb_sio_out[11:0] }),
+ .wb_out(wb_xics_ics_out)
+ );
+ assign wb_dram_in = { wb_master_out[106:105], _135_, wb_master_out[103:0] };
+ assign wb_ext_io_in = { wb_sio_out[68:67], _083_, wb_sio_out[65:0] };
+ assign wb_ext_is_dram_csr = _084_;
+ assign wb_ext_is_dram_init = _085_;
+ assign wb_ext_is_eth = _086_;
+ assign uart0_txd = _096_;
+ assign uart1_txd = 1'hz;
+ assign spi_flash_sck = _101_;
+ assign spi_flash_cs_n = _102_;
+ assign spi_flash_sdat_o = _103_;
+ assign spi_flash_sdat_oe = _104_;
+ assign jtag_tdo = _105_;
+endmodule
+
+module spi_flash_ctrl_4_4_1489f923c4dca729178b3e3233458550d8dddf29(clk, rst, wb_in, wb_sel_reg, wb_sel_map, sdat_i, wb_out, sck, cs_n, sdat_o, sdat_oe);
+ wire _000_;
+ wire [3:0] _001_;
+ wire [3:0] _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire [2:0] _013_;
+ wire [2:0] _014_;
+ wire [2:0] _015_;
+ wire [2:0] _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire [68:0] _025_;
+ wire _026_;
+ wire [65:0] _027_;
+ wire [1:0] _028_;
+ wire _029_;
+ wire _030_;
+ wire [68:0] _031_;
+ wire _032_;
+ wire [68:0] _033_;
+ wire [31:0] _034_;
+ wire [1:0] _035_;
+ wire [68:0] _036_;
+ wire [61:0] _037_;
+ wire [6:0] _038_;
+ reg [33:0] _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire [31:0] _052_;
+ wire [32:0] _053_;
+ wire _054_;
+ wire [33:0] _055_;
+ wire [31:0] _056_;
+ wire [1:0] _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire [31:0] _062_;
+ wire [31:0] _063_;
+ wire [31:0] _064_;
+ wire [5:0] _065_;
+ wire [4:0] _066_;
+ wire [31:0] _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire [31:0] _071_;
+ wire [5:0] _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire [5:0] _082_;
+ wire _083_;
+ wire [4:0] _084_;
+ wire [5:0] _085_;
+ wire _086_;
+ wire [4:0] _087_;
+ wire _088_;
+ wire _089_;
+ wire [4:0] _090_;
+ wire _091_;
+ wire [4:0] _092_;
+ wire [4:0] _093_;
+ wire _094_;
+ wire [4:0] _095_;
+ wire _096_;
+ wire [4:0] _097_;
+ wire _098_;
+ wire [4:0] _099_;
+ wire _100_;
+ wire _101_;
+ wire [4:0] _102_;
+ wire [4:0] _103_;
+ wire _104_;
+ wire [4:0] _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire [2:0] _109_;
+ wire [2:0] _110_;
+ wire [4:0] _111_;
+ wire _112_;
+ wire [7:0] _113_;
+ wire [4:0] _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire [2:0] _118_;
+ wire [2:0] _119_;
+ wire [4:0] _120_;
+ wire _121_;
+ wire [7:0] _122_;
+ wire [4:0] _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire [2:0] _127_;
+ wire [2:0] _128_;
+ wire [4:0] _129_;
+ wire _130_;
+ wire [7:0] _131_;
+ wire [4:0] _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire [2:0] _136_;
+ wire [2:0] _137_;
+ wire [4:0] _138_;
+ wire _139_;
+ wire [7:0] _140_;
+ wire [4:0] _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire [5:0] _151_;
+ wire [4:0] _152_;
+ wire [5:0] _153_;
+ wire [4:0] _154_;
+ wire _155_;
+ wire _156_;
+ wire [4:0] _157_;
+ wire _158_;
+ wire _159_;
+ wire [2:0] _160_;
+ wire [7:0] _161_;
+ wire [2:0] _162_;
+ wire [7:0] _163_;
+ wire [7:0] _164_;
+ wire [7:0] _165_;
+ wire [7:0] _166_;
+ wire [5:0] _167_;
+ wire _168_;
+ wire [4:0] _169_;
+ wire _170_;
+ wire _171_;
+ wire [3:0] _172_;
+ wire [7:0] _173_;
+ wire [29:0] _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire [15:0] _196_;
+ wire _197_;
+ wire _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire [29:0] _228_;
+ wire [15:0] _229_;
+ wire _230_;
+ wire auto_ack;
+ reg [29:0] auto_cfg_reg = 30'h00000000;
+ wire [2:0] auto_cmd_mode;
+ wire auto_cmd_valid;
+ reg [5:0] auto_cnt = 6'h00;
+ wire [5:0] auto_cnt_next;
+ wire auto_cs;
+ wire [2:0] auto_d_clks;
+ wire [7:0] auto_d_txd;
+ reg [31:0] auto_data = 32'd0;
+ wire [31:0] auto_data_next;
+ wire [31:0] auto_lad_next;
+ reg [31:0] auto_last_addr;
+ wire auto_latch_adr;
+ wire [4:0] auto_next;
+ reg [4:0] auto_state = 5'h00;
+ wire bus_idle;
+ input clk;
+ wire [7:0] cmd_clk_div;
+ wire [2:0] cmd_mode;
+ wire cmd_ready;
+ wire cmd_valid;
+ output cs_n;
+ reg [15:0] ctrl_reg = 16'h0000;
+ wire d_ack;
+ wire [2:0] d_clks;
+ wire [7:0] d_rx;
+ wire [7:0] d_tx;
+ reg pending_read;
+ input rst;
+ output sck;
+ input [3:0] sdat_i;
+ output [3:0] sdat_o;
+ output [3:0] sdat_oe;
+ input [68:0] wb_in;
+ wire wb_map_valid;
+ output [33:0] wb_out;
+ wire [2:0] wb_reg;
+ wire wb_reg_dat_v;
+ wire wb_reg_valid;
+ reg [68:0] wb_req;
+ input wb_sel_map;
+ input wb_sel_reg;
+ reg [68:0] wb_stash;
+ wire wb_valid;
+ assign wb_valid = wb_req[67] & wb_req[66];
+ assign wb_reg_valid = wb_valid & wb_sel_reg;
+ assign wb_map_valid = wb_valid & wb_sel_map;
+ assign wb_reg = wb_reg_valid ? wb_req[4:2] : 3'h7;
+ assign _003_ = wb_reg == 3'h0;
+ assign wb_reg_dat_v = _003_ ? 1'h1 : 1'h0;
+ assign _004_ = cmd_valid & cmd_ready;
+ assign _005_ = ~ wb_req[68];
+ assign _006_ = bus_idle ? 1'h0 : pending_read;
+ assign _007_ = _004_ ? _005_ : _006_;
+ always @(posedge clk)
+ pending_read <= _007_;
+ assign _008_ = pending_read & wb_req[68];
+ assign _009_ = ~ _008_;
+ assign _010_ = wb_reg_dat_v & _009_;
+ assign _011_ = wb_req[65:62] == 4'h2;
+ assign _012_ = wb_req[65:62] == 4'h4;
+ assign _013_ = _012_ ? { 2'h3, wb_req[68] } : { 2'h1, wb_req[68] };
+ assign _014_ = _012_ ? 3'h1 : 3'h7;
+ assign _015_ = _011_ ? { 2'h2, wb_req[68] } : _013_;
+ assign _016_ = _011_ ? 3'h3 : _014_;
+ assign _017_ = ~ ctrl_reg[1];
+ assign _018_ = ~ auto_cs;
+ assign _019_ = ctrl_reg[1] ? _017_ : _018_;
+ assign cmd_valid = ctrl_reg[1] ? _010_ : auto_cmd_valid;
+ assign cmd_clk_div = ctrl_reg[1] ? ctrl_reg[15:8] : auto_cfg_reg[23:16];
+ assign cmd_mode = ctrl_reg[1] ? _015_ : auto_cmd_mode;
+ assign d_clks = ctrl_reg[1] ? _016_ : auto_d_clks;
+ assign d_tx = ctrl_reg[1] ? wb_req[37:30] : auto_d_txd;
+ assign _020_ = ~ _039_[33];
+ assign _021_ = _061_ & _020_;
+ assign _022_ = _021_ & wb_in[66];
+ assign _023_ = _022_ & wb_in[67];
+ assign _024_ = _023_ ? 1'h1 : _061_;
+ assign _025_ = _023_ ? wb_in : wb_stash;
+ assign _026_ = ~ _061_;
+ assign _027_ = wb_in[66] ? wb_in[65:0] : wb_req[65:0];
+ assign _028_ = wb_in[66] ? wb_in[67:66] : wb_in[67:66];
+ assign _029_ = wb_in[66] ? wb_in[68] : wb_req[68];
+ assign _030_ = _032_ ? 1'h0 : _024_;
+ assign _031_ = _039_[33] ? wb_stash : { _029_, _028_, _027_ };
+ assign _032_ = _026_ & _039_[33];
+ assign _033_ = _026_ ? _031_ : wb_req;
+ assign _034_ = rst ? _039_[31:0] : _062_;
+ assign _035_ = rst ? 2'h0 : { _030_, _060_ };
+ assign _036_ = rst ? wb_req : _033_;
+ assign _037_ = rst ? wb_stash[61:0] : _025_[61:0];
+ assign _038_ = rst ? 7'h00 : _025_[68:62];
+ always @(posedge clk)
+ _039_ <= { _035_, _034_ };
+ always @(posedge clk)
+ wb_req <= _036_;
+ always @(posedge clk)
+ wb_stash <= { _038_, _037_ };
+ assign _040_ = ~ auto_ack;
+ assign _041_ = wb_reg == 3'h0;
+ assign _042_ = ctrl_reg[1] & _041_;
+ assign _043_ = wb_req[68] & pending_read;
+ assign _044_ = wb_req[68] & cmd_ready;
+ assign _045_ = ~ cmd_ready;
+ assign _046_ = _043_ ? 1'h0 : _044_;
+ assign _047_ = _043_ ? 1'h1 : _045_;
+ assign _048_ = auto_state == 5'h01;
+ assign _049_ = _048_ & bus_idle;
+ assign _050_ = wb_reg == 3'h1;
+ assign _051_ = wb_reg == 3'h2;
+ function [31:0] \5381 ;
+ input [31:0] a;
+ input [63:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \5381 = b[31:0];
+ 2'b1?:
+ \5381 = b[63:32];
+ default:
+ \5381 = a;
+ endcase
+ endfunction
+ assign _052_ = \5381 ({ 8'h00, d_rx, d_rx, d_rx }, { 2'h0, auto_cfg_reg, 16'h0000, ctrl_reg }, { _051_, _050_ });
+ assign _053_ = _049_ ? { 1'h1, _052_ } : { 9'h000, d_rx, d_rx, d_rx };
+ assign _054_ = _049_ ? 1'h0 : 1'h1;
+ assign _055_ = wb_reg_valid ? { _054_, _053_ } : { 10'h000, d_rx, d_rx, d_rx };
+ assign _056_ = _042_ ? { 8'h00, d_rx, d_rx, d_rx } : _055_[31:0];
+ assign _057_ = _042_ ? { _047_, _046_ } : _055_[33:32];
+ assign _058_ = ctrl_reg[1] & d_ack;
+ assign _059_ = wb_map_valid ? auto_ack : _057_[0];
+ assign _060_ = _058_ ? 1'h1 : _059_;
+ assign _061_ = wb_map_valid ? _040_ : _057_[1];
+ assign _062_ = wb_map_valid ? auto_data : _056_;
+ assign _063_ = auto_latch_adr ? auto_lad_next : auto_last_addr;
+ assign _064_ = rst ? auto_data : auto_data_next;
+ assign _065_ = rst ? auto_cnt : auto_cnt_next;
+ assign _066_ = rst ? 5'h00 : auto_next;
+ assign _067_ = rst ? 32'd0 : _063_;
+ always @(posedge clk)
+ auto_data <= _064_;
+ always @(posedge clk)
+ auto_cnt <= _065_;
+ always @(posedge clk)
+ auto_state <= _066_;
+ always @(posedge clk)
+ auto_last_addr <= _067_;
+ assign auto_lad_next = { 2'h0, wb_req[29:2], 2'h0 } + 32'd4;
+ assign _068_ = { 2'h0, wb_req[29:2], 2'h0 } == auto_last_addr;
+ assign _069_ = rst | ctrl_reg[0];
+ assign _070_ = { 26'h0000000, auto_cnt } != 32'd0;
+ assign _071_ = { 26'h0000000, auto_cnt } - 32'd1;
+ assign _072_ = _070_ ? _071_[5:0] : auto_cnt;
+ assign _073_ = auto_state != 5'h01;
+ assign _074_ = auto_state != 5'h13;
+ assign _075_ = _073_ & _074_;
+ assign _076_ = auto_state != 5'h00;
+ assign _077_ = _075_ & _076_;
+ assign _078_ = _077_ ? 1'h1 : 1'h0;
+ assign _079_ = auto_state == 5'h00;
+ assign _080_ = ~ ctrl_reg[1];
+ assign _081_ = wb_map_valid & _080_;
+ assign _082_ = wb_req[68] ? _072_ : 6'h01;
+ assign _083_ = wb_req[68] ? 1'h1 : 1'h0;
+ assign _084_ = wb_req[68] ? auto_state : 5'h02;
+ assign _085_ = _081_ ? _082_ : _072_;
+ assign _086_ = _081_ ? _083_ : 1'h0;
+ assign _087_ = _081_ ? _084_ : auto_state;
+ assign _088_ = auto_state == 5'h01;
+ assign _089_ = { 26'h0000000, auto_cnt } == 32'd0;
+ assign _090_ = _089_ ? 5'h03 : auto_state;
+ assign _091_ = auto_state == 5'h02;
+ assign _092_ = auto_cfg_reg[13] ? 5'h07 : 5'h06;
+ assign _093_ = cmd_ready ? _092_ : auto_state;
+ assign _094_ = auto_state == 5'h03;
+ assign _095_ = cmd_ready ? 5'h06 : auto_state;
+ assign _096_ = auto_state == 5'h07;
+ assign _097_ = cmd_ready ? 5'h05 : auto_state;
+ assign _098_ = auto_state == 5'h06;
+ assign _099_ = cmd_ready ? 5'h04 : auto_state;
+ assign _100_ = auto_state == 5'h05;
+ assign _101_ = auto_cfg_reg[10:8] == 3'h0;
+ assign _102_ = _101_ ? 5'h09 : 5'h08;
+ assign _103_ = cmd_ready ? _102_ : auto_state;
+ assign _104_ = auto_state == 5'h04;
+ assign _105_ = cmd_ready ? 5'h09 : auto_state;
+ assign _106_ = auto_state == 5'h08;
+ assign _107_ = auto_cfg_reg[12:11] == 2'h3;
+ assign _108_ = auto_cfg_reg[12:11] == 2'h2;
+ assign _109_ = _108_ ? 3'h3 : 3'h7;
+ assign _110_ = _107_ ? 3'h1 : _109_;
+ assign _111_ = cmd_ready ? 5'h0d : auto_state;
+ assign _112_ = auto_state == 5'h09;
+ assign _113_ = d_ack ? d_rx : auto_data[7:0];
+ assign _114_ = d_ack ? 5'h0a : auto_state;
+ assign _115_ = auto_state == 5'h0d;
+ assign _116_ = auto_cfg_reg[12:11] == 2'h3;
+ assign _117_ = auto_cfg_reg[12:11] == 2'h2;
+ assign _118_ = _117_ ? 3'h3 : 3'h7;
+ assign _119_ = _116_ ? 3'h1 : _118_;
+ assign _120_ = cmd_ready ? 5'h0e : auto_state;
+ assign _121_ = auto_state == 5'h0a;
+ assign _122_ = d_ack ? d_rx : auto_data[15:8];
+ assign _123_ = d_ack ? 5'h0b : auto_state;
+ assign _124_ = auto_state == 5'h0e;
+ assign _125_ = auto_cfg_reg[12:11] == 2'h3;
+ assign _126_ = auto_cfg_reg[12:11] == 2'h2;
+ assign _127_ = _126_ ? 3'h3 : 3'h7;
+ assign _128_ = _125_ ? 3'h1 : _127_;
+ assign _129_ = cmd_ready ? 5'h0f : auto_state;
+ assign _130_ = auto_state == 5'h0b;
+ assign _131_ = d_ack ? d_rx : auto_data[23:16];
+ assign _132_ = d_ack ? 5'h0c : auto_state;
+ assign _133_ = auto_state == 5'h0f;
+ assign _134_ = auto_cfg_reg[12:11] == 2'h3;
+ assign _135_ = auto_cfg_reg[12:11] == 2'h2;
+ assign _136_ = _135_ ? 3'h3 : 3'h7;
+ assign _137_ = _134_ ? 3'h1 : _136_;
+ assign _138_ = cmd_ready ? 5'h10 : auto_state;
+ assign _139_ = auto_state == 5'h0c;
+ assign _140_ = d_ack ? d_rx : auto_data[31:24];
+ assign _141_ = d_ack ? 5'h11 : auto_state;
+ assign _142_ = d_ack ? 1'h1 : 1'h0;
+ assign _143_ = auto_state == 5'h10;
+ assign _144_ = auto_state == 5'h11;
+ assign _145_ = wb_map_valid & _068_;
+ assign _146_ = ~ wb_req[68];
+ assign _147_ = _145_ & _146_;
+ assign _148_ = wb_map_valid | wb_reg_valid;
+ assign _149_ = { 26'h0000000, auto_cnt } == 32'd0;
+ assign _150_ = _148_ | _149_;
+ assign _151_ = _150_ ? 6'h0a : _072_;
+ assign _152_ = _150_ ? 5'h13 : auto_state;
+ assign _153_ = _147_ ? _072_ : _151_;
+ assign _154_ = _147_ ? 5'h09 : _152_;
+ assign _155_ = auto_state == 5'h12;
+ assign _156_ = { 26'h0000000, auto_cnt } == 32'd0;
+ assign _157_ = _156_ ? 5'h01 : auto_state;
+ assign _158_ = auto_state == 5'h13;
+ function [0:0] \5689 ;
+ input [0:0] a;
+ input [19:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5689 = b[0:0];
+ 20'b??????????????????1?:
+ \5689 = b[1:1];
+ 20'b?????????????????1??:
+ \5689 = b[2:2];
+ 20'b????????????????1???:
+ \5689 = b[3:3];
+ 20'b???????????????1????:
+ \5689 = b[4:4];
+ 20'b??????????????1?????:
+ \5689 = b[5:5];
+ 20'b?????????????1??????:
+ \5689 = b[6:6];
+ 20'b????????????1???????:
+ \5689 = b[7:7];
+ 20'b???????????1????????:
+ \5689 = b[8:8];
+ 20'b??????????1?????????:
+ \5689 = b[9:9];
+ 20'b?????????1??????????:
+ \5689 = b[10:10];
+ 20'b????????1???????????:
+ \5689 = b[11:11];
+ 20'b???????1????????????:
+ \5689 = b[12:12];
+ 20'b??????1?????????????:
+ \5689 = b[13:13];
+ 20'b?????1??????????????:
+ \5689 = b[14:14];
+ 20'b????1???????????????:
+ \5689 = b[15:15];
+ 20'b???1????????????????:
+ \5689 = b[16:16];
+ 20'b??1?????????????????:
+ \5689 = b[17:17];
+ 20'b?1??????????????????:
+ \5689 = b[18:18];
+ 20'b1???????????????????:
+ \5689 = b[19:19];
+ default:
+ \5689 = a;
+ endcase
+ endfunction
+ assign _159_ = \5689 (1'hx, 20'h0abf8, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [2:0] \5692 ;
+ input [2:0] a;
+ input [59:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5692 = b[2:0];
+ 20'b??????????????????1?:
+ \5692 = b[5:3];
+ 20'b?????????????????1??:
+ \5692 = b[8:6];
+ 20'b????????????????1???:
+ \5692 = b[11:9];
+ 20'b???????????????1????:
+ \5692 = b[14:12];
+ 20'b??????????????1?????:
+ \5692 = b[17:15];
+ 20'b?????????????1??????:
+ \5692 = b[20:18];
+ 20'b????????????1???????:
+ \5692 = b[23:21];
+ 20'b???????????1????????:
+ \5692 = b[26:24];
+ 20'b??????????1?????????:
+ \5692 = b[29:27];
+ 20'b?????????1??????????:
+ \5692 = b[32:30];
+ 20'b????????1???????????:
+ \5692 = b[35:33];
+ 20'b???????1????????????:
+ \5692 = b[38:36];
+ 20'b??????1?????????????:
+ \5692 = b[41:39];
+ 20'b?????1??????????????:
+ \5692 = b[44:42];
+ 20'b????1???????????????:
+ \5692 = b[47:45];
+ 20'b???1????????????????:
+ \5692 = b[50:48];
+ 20'b??1?????????????????:
+ \5692 = b[53:51];
+ 20'b?1??????????????????:
+ \5692 = b[56:54];
+ 20'b1???????????????????:
+ \5692 = b[59:57];
+ default:
+ \5692 = a;
+ endcase
+ endfunction
+ assign _160_ = \5692 (3'hx, { 12'h249, auto_cfg_reg[12:11], 4'h1, auto_cfg_reg[12:11], 4'h1, auto_cfg_reg[12:11], 4'h1, auto_cfg_reg[12:11], 28'h1249249 }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [7:0] \5695 ;
+ input [7:0] a;
+ input [159:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5695 = b[7:0];
+ 20'b??????????????????1?:
+ \5695 = b[15:8];
+ 20'b?????????????????1??:
+ \5695 = b[23:16];
+ 20'b????????????????1???:
+ \5695 = b[31:24];
+ 20'b???????????????1????:
+ \5695 = b[39:32];
+ 20'b??????????????1?????:
+ \5695 = b[47:40];
+ 20'b?????????????1??????:
+ \5695 = b[55:48];
+ 20'b????????????1???????:
+ \5695 = b[63:56];
+ 20'b???????????1????????:
+ \5695 = b[71:64];
+ 20'b??????????1?????????:
+ \5695 = b[79:72];
+ 20'b?????????1??????????:
+ \5695 = b[87:80];
+ 20'b????????1???????????:
+ \5695 = b[95:88];
+ 20'b???????1????????????:
+ \5695 = b[103:96];
+ 20'b??????1?????????????:
+ \5695 = b[111:104];
+ 20'b?????1??????????????:
+ \5695 = b[119:112];
+ 20'b????1???????????????:
+ \5695 = b[127:120];
+ 20'b???1????????????????:
+ \5695 = b[135:128];
+ 20'b??1?????????????????:
+ \5695 = b[143:136];
+ 20'b?1??????????????????:
+ \5695 = b[151:144];
+ 20'b1???????????????????:
+ \5695 = b[159:152];
+ default:
+ \5695 = a;
+ endcase
+ endfunction
+ assign _161_ = \5695 (8'hxx, { 96'h000000000000000000000000, wb_req[7:2], 2'h0, wb_req[15:8], wb_req[23:16], 2'h0, wb_req[29:24], auto_cfg_reg[7:0], 24'h000000 }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [2:0] \5698 ;
+ input [2:0] a;
+ input [59:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5698 = b[2:0];
+ 20'b??????????????????1?:
+ \5698 = b[5:3];
+ 20'b?????????????????1??:
+ \5698 = b[8:6];
+ 20'b????????????????1???:
+ \5698 = b[11:9];
+ 20'b???????????????1????:
+ \5698 = b[14:12];
+ 20'b??????????????1?????:
+ \5698 = b[17:15];
+ 20'b?????????????1??????:
+ \5698 = b[20:18];
+ 20'b????????????1???????:
+ \5698 = b[23:21];
+ 20'b???????????1????????:
+ \5698 = b[26:24];
+ 20'b??????????1?????????:
+ \5698 = b[29:27];
+ 20'b?????????1??????????:
+ \5698 = b[32:30];
+ 20'b????????1???????????:
+ \5698 = b[35:33];
+ 20'b???????1????????????:
+ \5698 = b[38:36];
+ 20'b??????1?????????????:
+ \5698 = b[41:39];
+ 20'b?????1??????????????:
+ \5698 = b[44:42];
+ 20'b????1???????????????:
+ \5698 = b[47:45];
+ 20'b???1????????????????:
+ \5698 = b[50:48];
+ 20'b??1?????????????????:
+ \5698 = b[53:51];
+ 20'b?1??????????????????:
+ \5698 = b[56:54];
+ 20'b1???????????????????:
+ \5698 = b[59:57];
+ default:
+ \5698 = a;
+ endcase
+ endfunction
+ assign _162_ = \5698 (3'hx, { 12'hfff, _137_, 3'h7, _128_, 3'h7, _119_, 3'h7, _110_, auto_cfg_reg[10:8], 24'hffffff }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [7:0] \5701 ;
+ input [7:0] a;
+ input [159:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5701 = b[7:0];
+ 20'b??????????????????1?:
+ \5701 = b[15:8];
+ 20'b?????????????????1??:
+ \5701 = b[23:16];
+ 20'b????????????????1???:
+ \5701 = b[31:24];
+ 20'b???????????????1????:
+ \5701 = b[39:32];
+ 20'b??????????????1?????:
+ \5701 = b[47:40];
+ 20'b?????????????1??????:
+ \5701 = b[55:48];
+ 20'b????????????1???????:
+ \5701 = b[63:56];
+ 20'b???????????1????????:
+ \5701 = b[71:64];
+ 20'b??????????1?????????:
+ \5701 = b[79:72];
+ 20'b?????????1??????????:
+ \5701 = b[87:80];
+ 20'b????????1???????????:
+ \5701 = b[95:88];
+ 20'b???????1????????????:
+ \5701 = b[103:96];
+ 20'b??????1?????????????:
+ \5701 = b[111:104];
+ 20'b?????1??????????????:
+ \5701 = b[119:112];
+ 20'b????1???????????????:
+ \5701 = b[127:120];
+ 20'b???1????????????????:
+ \5701 = b[135:128];
+ 20'b??1?????????????????:
+ \5701 = b[143:136];
+ 20'b?1??????????????????:
+ \5701 = b[151:144];
+ 20'b1???????????????????:
+ \5701 = b[159:152];
+ default:
+ \5701 = a;
+ endcase
+ endfunction
+ assign _163_ = \5701 (8'hxx, { auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], _113_, auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0], auto_data[7:0] }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [7:0] \5704 ;
+ input [7:0] a;
+ input [159:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5704 = b[7:0];
+ 20'b??????????????????1?:
+ \5704 = b[15:8];
+ 20'b?????????????????1??:
+ \5704 = b[23:16];
+ 20'b????????????????1???:
+ \5704 = b[31:24];
+ 20'b???????????????1????:
+ \5704 = b[39:32];
+ 20'b??????????????1?????:
+ \5704 = b[47:40];
+ 20'b?????????????1??????:
+ \5704 = b[55:48];
+ 20'b????????????1???????:
+ \5704 = b[63:56];
+ 20'b???????????1????????:
+ \5704 = b[71:64];
+ 20'b??????????1?????????:
+ \5704 = b[79:72];
+ 20'b?????????1??????????:
+ \5704 = b[87:80];
+ 20'b????????1???????????:
+ \5704 = b[95:88];
+ 20'b???????1????????????:
+ \5704 = b[103:96];
+ 20'b??????1?????????????:
+ \5704 = b[111:104];
+ 20'b?????1??????????????:
+ \5704 = b[119:112];
+ 20'b????1???????????????:
+ \5704 = b[127:120];
+ 20'b???1????????????????:
+ \5704 = b[135:128];
+ 20'b??1?????????????????:
+ \5704 = b[143:136];
+ 20'b?1??????????????????:
+ \5704 = b[151:144];
+ 20'b1???????????????????:
+ \5704 = b[159:152];
+ default:
+ \5704 = a;
+ endcase
+ endfunction
+ assign _164_ = \5704 (8'hxx, { auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], _122_, auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8], auto_data[15:8] }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [7:0] \5707 ;
+ input [7:0] a;
+ input [159:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5707 = b[7:0];
+ 20'b??????????????????1?:
+ \5707 = b[15:8];
+ 20'b?????????????????1??:
+ \5707 = b[23:16];
+ 20'b????????????????1???:
+ \5707 = b[31:24];
+ 20'b???????????????1????:
+ \5707 = b[39:32];
+ 20'b??????????????1?????:
+ \5707 = b[47:40];
+ 20'b?????????????1??????:
+ \5707 = b[55:48];
+ 20'b????????????1???????:
+ \5707 = b[63:56];
+ 20'b???????????1????????:
+ \5707 = b[71:64];
+ 20'b??????????1?????????:
+ \5707 = b[79:72];
+ 20'b?????????1??????????:
+ \5707 = b[87:80];
+ 20'b????????1???????????:
+ \5707 = b[95:88];
+ 20'b???????1????????????:
+ \5707 = b[103:96];
+ 20'b??????1?????????????:
+ \5707 = b[111:104];
+ 20'b?????1??????????????:
+ \5707 = b[119:112];
+ 20'b????1???????????????:
+ \5707 = b[127:120];
+ 20'b???1????????????????:
+ \5707 = b[135:128];
+ 20'b??1?????????????????:
+ \5707 = b[143:136];
+ 20'b?1??????????????????:
+ \5707 = b[151:144];
+ 20'b1???????????????????:
+ \5707 = b[159:152];
+ default:
+ \5707 = a;
+ endcase
+ endfunction
+ assign _165_ = \5707 (8'hxx, { auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], _131_, auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16], auto_data[23:16] }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [7:0] \5710 ;
+ input [7:0] a;
+ input [159:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5710 = b[7:0];
+ 20'b??????????????????1?:
+ \5710 = b[15:8];
+ 20'b?????????????????1??:
+ \5710 = b[23:16];
+ 20'b????????????????1???:
+ \5710 = b[31:24];
+ 20'b???????????????1????:
+ \5710 = b[39:32];
+ 20'b??????????????1?????:
+ \5710 = b[47:40];
+ 20'b?????????????1??????:
+ \5710 = b[55:48];
+ 20'b????????????1???????:
+ \5710 = b[63:56];
+ 20'b???????????1????????:
+ \5710 = b[71:64];
+ 20'b??????????1?????????:
+ \5710 = b[79:72];
+ 20'b?????????1??????????:
+ \5710 = b[87:80];
+ 20'b????????1???????????:
+ \5710 = b[95:88];
+ 20'b???????1????????????:
+ \5710 = b[103:96];
+ 20'b??????1?????????????:
+ \5710 = b[111:104];
+ 20'b?????1??????????????:
+ \5710 = b[119:112];
+ 20'b????1???????????????:
+ \5710 = b[127:120];
+ 20'b???1????????????????:
+ \5710 = b[135:128];
+ 20'b??1?????????????????:
+ \5710 = b[143:136];
+ 20'b?1??????????????????:
+ \5710 = b[151:144];
+ 20'b1???????????????????:
+ \5710 = b[159:152];
+ default:
+ \5710 = a;
+ endcase
+ endfunction
+ assign _166_ = \5710 (8'hxx, { auto_data[31:24], auto_data[31:24], auto_data[31:24], _140_, auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24], auto_data[31:24] }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [5:0] \5712 ;
+ input [5:0] a;
+ input [119:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5712 = b[5:0];
+ 20'b??????????????????1?:
+ \5712 = b[11:6];
+ 20'b?????????????????1??:
+ \5712 = b[17:12];
+ 20'b????????????????1???:
+ \5712 = b[23:18];
+ 20'b???????????????1????:
+ \5712 = b[29:24];
+ 20'b??????????????1?????:
+ \5712 = b[35:30];
+ 20'b?????????????1??????:
+ \5712 = b[41:36];
+ 20'b????????????1???????:
+ \5712 = b[47:42];
+ 20'b???????????1????????:
+ \5712 = b[53:48];
+ 20'b??????????1?????????:
+ \5712 = b[59:54];
+ 20'b?????????1??????????:
+ \5712 = b[65:60];
+ 20'b????????1???????????:
+ \5712 = b[71:66];
+ 20'b???????1????????????:
+ \5712 = b[77:72];
+ 20'b??????1?????????????:
+ \5712 = b[83:78];
+ 20'b?????1??????????????:
+ \5712 = b[89:84];
+ 20'b????1???????????????:
+ \5712 = b[95:90];
+ 20'b???1????????????????:
+ \5712 = b[101:96];
+ 20'b??1?????????????????:
+ \5712 = b[107:102];
+ 20'b?1??????????????????:
+ \5712 = b[113:108];
+ 20'b1???????????????????:
+ \5712 = b[119:114];
+ default:
+ \5712 = a;
+ endcase
+ endfunction
+ assign _167_ = \5712 (6'hxx, { _072_, _153_, auto_cfg_reg[29:24], _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _072_, _085_, _072_ }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [0:0] \5716 ;
+ input [0:0] a;
+ input [19:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5716 = b[0:0];
+ 20'b??????????????????1?:
+ \5716 = b[1:1];
+ 20'b?????????????????1??:
+ \5716 = b[2:2];
+ 20'b????????????????1???:
+ \5716 = b[3:3];
+ 20'b???????????????1????:
+ \5716 = b[4:4];
+ 20'b??????????????1?????:
+ \5716 = b[5:5];
+ 20'b?????????????1??????:
+ \5716 = b[6:6];
+ 20'b????????????1???????:
+ \5716 = b[7:7];
+ 20'b???????????1????????:
+ \5716 = b[8:8];
+ 20'b??????????1?????????:
+ \5716 = b[9:9];
+ 20'b?????????1??????????:
+ \5716 = b[10:10];
+ 20'b????????1???????????:
+ \5716 = b[11:11];
+ 20'b???????1????????????:
+ \5716 = b[12:12];
+ 20'b??????1?????????????:
+ \5716 = b[13:13];
+ 20'b?????1??????????????:
+ \5716 = b[14:14];
+ 20'b????1???????????????:
+ \5716 = b[15:15];
+ 20'b???1????????????????:
+ \5716 = b[16:16];
+ 20'b??1?????????????????:
+ \5716 = b[17:17];
+ 20'b?1??????????????????:
+ \5716 = b[18:18];
+ 20'b1???????????????????:
+ \5716 = b[19:19];
+ default:
+ \5716 = a;
+ endcase
+ endfunction
+ assign _168_ = \5716 (1'hx, { 18'h08000, _086_, 1'h0 }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [4:0] \5720 ;
+ input [4:0] a;
+ input [99:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5720 = b[4:0];
+ 20'b??????????????????1?:
+ \5720 = b[9:5];
+ 20'b?????????????????1??:
+ \5720 = b[14:10];
+ 20'b????????????????1???:
+ \5720 = b[19:15];
+ 20'b???????????????1????:
+ \5720 = b[24:20];
+ 20'b??????????????1?????:
+ \5720 = b[29:25];
+ 20'b?????????????1??????:
+ \5720 = b[34:30];
+ 20'b????????????1???????:
+ \5720 = b[39:35];
+ 20'b???????????1????????:
+ \5720 = b[44:40];
+ 20'b??????????1?????????:
+ \5720 = b[49:45];
+ 20'b?????????1??????????:
+ \5720 = b[54:50];
+ 20'b????????1???????????:
+ \5720 = b[59:55];
+ 20'b???????1????????????:
+ \5720 = b[64:60];
+ 20'b??????1?????????????:
+ \5720 = b[69:65];
+ 20'b?????1??????????????:
+ \5720 = b[74:70];
+ 20'b????1???????????????:
+ \5720 = b[79:75];
+ 20'b???1????????????????:
+ \5720 = b[84:80];
+ 20'b??1?????????????????:
+ \5720 = b[89:85];
+ 20'b?1??????????????????:
+ \5720 = b[94:90];
+ 20'b1???????????????????:
+ \5720 = b[99:95];
+ default:
+ \5720 = a;
+ endcase
+ endfunction
+ assign _169_ = \5720 (5'hxx, { _157_, _154_, 5'h12, _141_, _138_, _132_, _129_, _123_, _120_, _114_, _111_, _105_, _103_, _099_, _097_, _095_, _093_, _090_, _087_, 5'h01 }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ function [0:0] \5723 ;
+ input [0:0] a;
+ input [19:0] b;
+ input [19:0] s;
+ (* parallel_case *)
+ casez (s)
+ 20'b???????????????????1:
+ \5723 = b[0:0];
+ 20'b??????????????????1?:
+ \5723 = b[1:1];
+ 20'b?????????????????1??:
+ \5723 = b[2:2];
+ 20'b????????????????1???:
+ \5723 = b[3:3];
+ 20'b???????????????1????:
+ \5723 = b[4:4];
+ 20'b??????????????1?????:
+ \5723 = b[5:5];
+ 20'b?????????????1??????:
+ \5723 = b[6:6];
+ 20'b????????????1???????:
+ \5723 = b[7:7];
+ 20'b???????????1????????:
+ \5723 = b[8:8];
+ 20'b??????????1?????????:
+ \5723 = b[9:9];
+ 20'b?????????1??????????:
+ \5723 = b[10:10];
+ 20'b????????1???????????:
+ \5723 = b[11:11];
+ 20'b???????1????????????:
+ \5723 = b[12:12];
+ 20'b??????1?????????????:
+ \5723 = b[13:13];
+ 20'b?????1??????????????:
+ \5723 = b[14:14];
+ 20'b????1???????????????:
+ \5723 = b[15:15];
+ 20'b???1????????????????:
+ \5723 = b[16:16];
+ 20'b??1?????????????????:
+ \5723 = b[17:17];
+ 20'b?1??????????????????:
+ \5723 = b[18:18];
+ 20'b1???????????????????:
+ \5723 = b[19:19];
+ default:
+ \5723 = a;
+ endcase
+ endfunction
+ assign _170_ = \5723 (1'hx, { 3'h0, _142_, 16'h0000 }, { _158_, _155_, _144_, _143_, _139_, _133_, _130_, _124_, _121_, _115_, _112_, _106_, _104_, _100_, _098_, _096_, _094_, _091_, _088_, _079_ });
+ assign auto_cs = _069_ ? 1'h0 : _078_;
+ assign auto_cmd_valid = _069_ ? 1'h0 : _159_;
+ assign auto_cmd_mode = _069_ ? 3'h1 : _160_;
+ assign auto_d_txd = _069_ ? 8'h00 : _161_;
+ assign auto_d_clks = _069_ ? 3'h7 : _162_;
+ assign auto_data_next = _069_ ? auto_data : { _166_, _165_, _164_, _163_ };
+ assign auto_cnt_next = _069_ ? 6'h00 : _167_;
+ assign auto_ack = _069_ ? 1'h0 : _168_;
+ assign auto_next = _069_ ? 5'h00 : _169_;
+ assign auto_latch_adr = _069_ ? 1'h0 : _170_;
+ assign _171_ = rst | ctrl_reg[0];
+ assign _172_ = _171_ ? 4'h0 : ctrl_reg[3:0];
+ assign _173_ = _171_ ? 8'h04 : ctrl_reg[15:8];
+ assign _174_ = _171_ ? 30'h20040003 : auto_cfg_reg;
+ assign _175_ = wb_reg_valid & wb_req[68];
+ assign _176_ = auto_state == 5'h01;
+ assign _177_ = _175_ & _176_;
+ assign _178_ = _177_ & bus_idle;
+ assign _179_ = wb_reg == 3'h1;
+ assign _180_ = wb_req[63] ? wb_req[45] : ctrl_reg[15];
+ assign _181_ = wb_req[63] ? wb_req[44] : ctrl_reg[14];
+ assign _182_ = wb_req[63] ? wb_req[43] : ctrl_reg[13];
+ assign _183_ = wb_req[63] ? wb_req[42] : ctrl_reg[12];
+ assign _184_ = wb_req[63] ? wb_req[41] : ctrl_reg[11];
+ assign _185_ = wb_req[63] ? wb_req[40] : ctrl_reg[10];
+ assign _186_ = wb_req[63] ? wb_req[39] : ctrl_reg[9];
+ assign _187_ = wb_req[63] ? wb_req[38] : ctrl_reg[8];
+ assign _188_ = wb_req[62] ? wb_req[37] : ctrl_reg[7];
+ assign _189_ = wb_req[62] ? wb_req[36] : ctrl_reg[6];
+ assign _190_ = wb_req[62] ? wb_req[35] : ctrl_reg[5];
+ assign _191_ = wb_req[62] ? wb_req[34] : ctrl_reg[4];
+ assign _192_ = wb_req[62] ? wb_req[33] : ctrl_reg[3];
+ assign _193_ = wb_req[62] ? wb_req[32] : ctrl_reg[2];
+ assign _194_ = wb_req[62] ? wb_req[31] : ctrl_reg[1];
+ assign _195_ = wb_req[62] ? wb_req[30] : ctrl_reg[0];
+ assign _196_ = _179_ ? { _180_, _181_, _182_, _183_, _184_, _185_, _186_, _187_, _188_, _189_, _190_, _191_, _192_, _193_, _194_, _195_ } : { _173_, ctrl_reg[7:4], _172_ };
+ assign _197_ = wb_reg == 3'h2;
+ assign _198_ = wb_req[65] ? wb_req[59] : auto_cfg_reg[29];
+ assign _199_ = wb_req[65] ? wb_req[58] : auto_cfg_reg[28];
+ assign _200_ = wb_req[65] ? wb_req[57] : auto_cfg_reg[27];
+ assign _201_ = wb_req[65] ? wb_req[56] : auto_cfg_reg[26];
+ assign _202_ = wb_req[65] ? wb_req[55] : auto_cfg_reg[25];
+ assign _203_ = wb_req[65] ? wb_req[54] : auto_cfg_reg[24];
+ assign _204_ = wb_req[64] ? wb_req[53] : auto_cfg_reg[23];
+ assign _205_ = wb_req[64] ? wb_req[52] : auto_cfg_reg[22];
+ assign _206_ = wb_req[64] ? wb_req[51] : auto_cfg_reg[21];
+ assign _207_ = wb_req[64] ? wb_req[50] : auto_cfg_reg[20];
+ assign _208_ = wb_req[64] ? wb_req[49] : auto_cfg_reg[19];
+ assign _209_ = wb_req[64] ? wb_req[48] : auto_cfg_reg[18];
+ assign _210_ = wb_req[64] ? wb_req[47] : auto_cfg_reg[17];
+ assign _211_ = wb_req[64] ? wb_req[46] : auto_cfg_reg[16];
+ assign _212_ = wb_req[63] ? wb_req[45] : auto_cfg_reg[15];
+ assign _213_ = wb_req[63] ? wb_req[44] : auto_cfg_reg[14];
+ assign _214_ = wb_req[63] ? wb_req[43] : auto_cfg_reg[13];
+ assign _215_ = wb_req[63] ? wb_req[42] : auto_cfg_reg[12];
+ assign _216_ = wb_req[63] ? wb_req[41] : auto_cfg_reg[11];
+ assign _217_ = wb_req[63] ? wb_req[40] : auto_cfg_reg[10];
+ assign _218_ = wb_req[63] ? wb_req[39] : auto_cfg_reg[9];
+ assign _219_ = wb_req[63] ? wb_req[38] : auto_cfg_reg[8];
+ assign _220_ = wb_req[62] ? wb_req[37] : auto_cfg_reg[7];
+ assign _221_ = wb_req[62] ? wb_req[36] : auto_cfg_reg[6];
+ assign _222_ = wb_req[62] ? wb_req[35] : auto_cfg_reg[5];
+ assign _223_ = wb_req[62] ? wb_req[34] : auto_cfg_reg[4];
+ assign _224_ = wb_req[62] ? wb_req[33] : auto_cfg_reg[3];
+ assign _225_ = wb_req[62] ? wb_req[32] : auto_cfg_reg[2];
+ assign _226_ = wb_req[62] ? wb_req[31] : auto_cfg_reg[1];
+ assign _227_ = wb_req[62] ? wb_req[30] : auto_cfg_reg[0];
+ assign _228_ = _230_ ? { _198_, _199_, _200_, _201_, _202_, _203_, _204_, _205_, _206_, _207_, _208_, _209_, _210_, _211_, _212_, _213_, _214_, _215_, _216_, _217_, _218_, _219_, _220_, _221_, _222_, _223_, _224_, _225_, _226_, _227_ } : _174_;
+ assign _229_ = _178_ ? _196_ : { _173_, ctrl_reg[7:4], _172_ };
+ assign _230_ = _178_ & _197_;
+ always @(posedge clk)
+ ctrl_reg <= _229_;
+ always @(posedge clk)
+ auto_cfg_reg <= _228_;
+ spi_rxtx_4_1 spi_rxtx (
+ .bus_idle_o(bus_idle),
+ .clk(clk),
+ .clk_div_i(cmd_clk_div),
+ .cmd_clks_i(d_clks),
+ .cmd_mode_i(cmd_mode),
+ .cmd_ready_o(cmd_ready),
+ .cmd_txd_i(d_tx),
+ .cmd_valid_i(cmd_valid),
+ .d_ack_o(d_ack),
+ .d_rxd_o(d_rx),
+ .rst(rst),
+ .sck(_000_),
+ .sdat_i(sdat_i),
+ .sdat_o(_001_),
+ .sdat_oe(_002_)
+ );
+ assign wb_out = _039_;
+ assign sck = _000_;
+ assign cs_n = _019_;
+ assign sdat_o = _001_;
+ assign sdat_oe = _002_;
+endmodule
+
+module spi_rxtx_4_1(clk, rst, clk_div_i, cmd_valid_i, cmd_mode_i, cmd_clks_i, cmd_txd_i, sdat_i, cmd_ready_o, d_rxd_o, d_ack_o, bus_idle_o, sck, sdat_o, sdat_oe);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [31:0] _03_;
+ wire _04_;
+ wire [7:0] _05_;
+ wire _06_;
+ wire _07_;
+ wire [7:0] _08_;
+ wire _09_;
+ wire [7:0] _10_;
+ wire _11_;
+ wire _12_;
+ wire [7:0] _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire [2:0] _26_;
+ wire _27_;
+ wire [2:0] _28_;
+ wire _29_;
+ wire _30_;
+ wire [2:0] _31_;
+ wire [2:0] _32_;
+ wire [2:0] _33_;
+ wire [2:0] _34_;
+ wire [2:0] _35_;
+ wire _36_;
+ wire _37_;
+ wire [7:0] _38_;
+ wire [7:0] _39_;
+ wire [7:0] _40_;
+ wire [7:0] _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire _62_;
+ wire _63_;
+ wire _64_;
+ wire _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ wire _70_;
+ wire _71_;
+ wire _72_;
+ wire _73_;
+ wire _74_;
+ wire _75_;
+ wire _76_;
+ wire _77_;
+ wire [7:0] _78_;
+ wire [7:0] _79_;
+ reg _80_ = 1'h0;
+ wire [7:0] _81_;
+ reg [2:0] bit_count;
+ output bus_idle_o;
+ input clk;
+ reg [7:0] clk_div;
+ input [7:0] clk_div_i;
+ input [2:0] cmd_clks_i;
+ reg [2:0] cmd_mode;
+ input [2:0] cmd_mode_i;
+ output cmd_ready_o;
+ input [7:0] cmd_txd_i;
+ input cmd_valid_i;
+ output d_ack_o;
+ output [7:0] d_rxd_o;
+ reg dat_ack_l;
+ reg [3:0] dat_i_l;
+ wire end_cmd;
+ reg [7:0] ireg = 8'h00;
+ wire next_cmd;
+ reg [7:0] oreg;
+ input rst;
+ output sck;
+ reg sck_0;
+ reg sck_1;
+ reg [7:0] \sck_gen.counter = 8'h00;
+ reg sck_recv;
+ reg sck_recv_d = 1'h0;
+ reg sck_send;
+ input [3:0] sdat_i;
+ output [3:0] sdat_o;
+ output [3:0] sdat_oe;
+ wire start_cmd;
+ reg state = 1'h0;
+ assign _00_ = { 24'h000000, \sck_gen.counter } == { 24'h000000, clk_div };
+ assign _01_ = ~ sck_0;
+ assign _02_ = ~ sck_0;
+ assign _03_ = { 24'h000000, \sck_gen.counter } + 32'd1;
+ assign _04_ = _00_ ? _01_ : sck_0;
+ assign _05_ = _00_ ? clk_div_i : clk_div;
+ assign _06_ = _00_ ? sck_0 : 1'h0;
+ assign _07_ = _00_ ? _02_ : 1'h0;
+ assign _08_ = _00_ ? 8'h00 : _03_[7:0];
+ assign _09_ = rst ? 1'h1 : _04_;
+ assign _10_ = rst ? 8'h00 : _05_;
+ assign _11_ = rst ? 1'h0 : _06_;
+ assign _12_ = rst ? 1'h0 : _07_;
+ assign _13_ = rst ? 8'h00 : _08_;
+ assign _14_ = state == 1'h1;
+ assign _15_ = ~ end_cmd;
+ assign _16_ = _14_ & _15_;
+ assign _17_ = next_cmd & cmd_valid_i;
+ assign _18_ = _16_ | _17_;
+ assign _19_ = _18_ ? sck_0 : 1'h1;
+ always @(posedge clk)
+ sck_0 <= _09_;
+ always @(posedge clk)
+ sck_1 <= _19_;
+ always @(posedge clk)
+ clk_div <= _10_;
+ always @(posedge clk)
+ sck_send <= _11_;
+ always @(posedge clk)
+ sck_recv <= _12_;
+ always @(posedge clk)
+ \sck_gen.counter <= _13_;
+ assign _20_ = bit_count == 3'h7;
+ assign _21_ = sck_send & _20_;
+ assign next_cmd = _21_ ? 1'h1 : 1'h0;
+ assign start_cmd = next_cmd & cmd_valid_i;
+ assign _22_ = ~ cmd_valid_i;
+ assign end_cmd = next_cmd & _22_;
+ assign _23_ = state == 1'h0;
+ assign _24_ = _23_ ? 1'h1 : 1'h0;
+ assign _25_ = end_cmd ? 1'h0 : state;
+ assign _26_ = start_cmd ? cmd_mode_i : cmd_mode;
+ assign _27_ = start_cmd ? 1'h1 : _25_;
+ assign _28_ = rst ? 3'h0 : _26_;
+ assign _29_ = rst ? 1'h0 : _27_;
+ always @(posedge clk)
+ cmd_mode <= _28_;
+ always @(posedge clk)
+ state <= _29_;
+ assign _30_ = state != 1'h1;
+ assign _31_ = bit_count - 3'h1;
+ assign _32_ = sck_recv ? _31_ : bit_count;
+ assign _33_ = _30_ ? 3'h7 : _32_;
+ assign _34_ = start_cmd ? cmd_clks_i : _33_;
+ assign _35_ = rst ? 3'h0 : _34_;
+ always @(posedge clk)
+ bit_count <= _35_;
+ assign _36_ = ~ cmd_mode[2];
+ assign _37_ = cmd_mode[2:1] == 2'h2;
+ assign _38_ = _37_ ? { oreg[5:0], 2'h0 } : { oreg[3:0], 4'h0 };
+ assign _39_ = _36_ ? { oreg[6:0], 1'h0 } : _38_;
+ assign _40_ = sck_send ? _39_ : oreg;
+ assign _41_ = start_cmd ? cmd_txd_i : _40_;
+ always @(posedge clk)
+ oreg <= _41_;
+ assign _42_ = state == 1'h1;
+ assign _43_ = cmd_mode[2:1] == 2'h3;
+ assign _44_ = 1'h1 & _43_;
+ assign _45_ = _44_ & cmd_mode[0];
+ assign _46_ = _47_ ? 1'h1 : 1'h0;
+ assign _47_ = _42_ & _45_;
+ assign _48_ = state == 1'h1;
+ assign _49_ = cmd_mode[2:1] == 2'h3;
+ assign _50_ = 1'h1 & _49_;
+ assign _51_ = _50_ & cmd_mode[0];
+ assign _52_ = _53_ ? 1'h1 : 1'h0;
+ assign _53_ = _48_ & _51_;
+ assign _54_ = state == 1'h1;
+ assign _55_ = cmd_mode[2:1] == 2'h2;
+ assign _56_ = 1'h1 & _55_;
+ assign _57_ = _56_ & cmd_mode[0];
+ assign _58_ = _57_ ? 1'h1 : 1'h0;
+ assign _59_ = cmd_mode[2:1] == 2'h3;
+ assign _60_ = 1'h1 & _59_;
+ assign _61_ = _60_ & cmd_mode[0];
+ assign _62_ = _61_ ? 1'h1 : _58_;
+ assign _63_ = _54_ ? _62_ : 1'h0;
+ assign _64_ = state == 1'h1;
+ assign _65_ = ~ cmd_mode[2];
+ assign _66_ = _65_ | cmd_mode[0];
+ assign _67_ = 1'h1 & _66_;
+ assign _68_ = _69_ ? 1'h1 : 1'h0;
+ assign _69_ = _64_ & _67_;
+ always @(negedge clk)
+ dat_i_l <= sdat_i;
+ assign _70_ = state == 1'h1;
+ assign _71_ = _70_ ? sck_recv : 1'h0;
+ assign _72_ = bit_count == 3'h0;
+ assign _73_ = _72_ & sck_recv;
+ assign _74_ = ~ cmd_mode[0];
+ assign _75_ = _73_ ? _74_ : 1'h0;
+ assign _76_ = cmd_mode[2:1] == 2'h2;
+ assign _77_ = cmd_mode[2:1] == 2'h3;
+ assign _78_ = _77_ ? { ireg[3:0], dat_i_l } : { ireg[6:0], dat_i_l[1] };
+ assign _79_ = _76_ ? { ireg[5:0], dat_i_l[1:0] } : _78_;
+ always @(posedge clk)
+ _80_ <= dat_ack_l;
+ always @(posedge clk)
+ dat_ack_l <= _75_;
+ always @(posedge clk)
+ sck_recv_d <= _71_;
+ assign _81_ = sck_recv_d ? _79_ : ireg;
+ always @(posedge clk)
+ ireg <= _81_;
+ assign cmd_ready_o = next_cmd;
+ assign d_rxd_o = ireg;
+ assign d_ack_o = _80_;
+ assign bus_idle_o = _24_;
+ assign sck = sck_1;
+ assign sdat_o = { oreg[4], oreg[5], oreg[6], oreg[7] };
+ assign sdat_oe = { _46_, _52_, _63_, _68_ };
+endmodule
+
+module syscon_50000000_4096_0_0_0_d1a6c63d707d362dd5f27f0b0ee5a7d91add1255(clk, rst, wishbone_in, wishbone_out, dram_at_0, core_reset, soc_reset);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [31:0] _12_;
+ reg [33:0] _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire [2:0] _25_;
+ input clk;
+ output core_reset;
+ output dram_at_0;
+ wire info_has_bram;
+ wire info_has_dram;
+ wire info_has_leth;
+ wire info_has_spif;
+ wire info_has_uart;
+ wire info_has_urt1;
+ reg [2:0] reg_ctrl;
+ wire [63:0] reg_dramiinfo;
+ wire [63:0] reg_draminfo;
+ wire [63:0] reg_out;
+ input rst;
+ output soc_reset;
+ wire uinfo_16550;
+ input [68:0] wishbone_in;
+ output [33:0] wishbone_out;
+ assign _00_ = 1'h0 ? 1'h1 : reg_ctrl[0];
+ assign info_has_uart = 1'h1 ? 1'h1 : 1'h0;
+ assign info_has_dram = 1'h1 ? 1'h1 : 1'h0;
+ assign info_has_bram = 1'h1 ? 1'h1 : 1'h0;
+ assign info_has_spif = 1'h1 ? 1'h1 : 1'h0;
+ assign info_has_leth = 1'h1 ? 1'h1 : 1'h0;
+ assign info_has_urt1 = 1'h0 ? 1'h1 : 1'h0;
+ assign reg_draminfo = 1'h1 ? 64'h0000000000000000 : 64'h0000000000000000;
+ assign reg_dramiinfo = 1'h1 ? 64'h0000000000000000 : 64'h0000000000000000;
+ assign uinfo_16550 = 1'h1 ? 1'h1 : 1'h0;
+ assign _01_ = wishbone_in[66] & wishbone_in[67];
+ assign _02_ = wishbone_in[8:3] == 6'h00;
+ assign _03_ = wishbone_in[8:3] == 6'h01;
+ assign _04_ = wishbone_in[8:3] == 6'h02;
+ assign _05_ = wishbone_in[8:3] == 6'h03;
+ assign _06_ = wishbone_in[8:3] == 6'h06;
+ assign _07_ = wishbone_in[8:3] == 6'h04;
+ assign _08_ = wishbone_in[8:3] == 6'h05;
+ assign _09_ = wishbone_in[8:3] == 6'h07;
+ assign _10_ = wishbone_in[8:3] == 6'h08;
+ assign _11_ = wishbone_in[8:3] == 6'h09;
+ function [63:0] \5122 ;
+ input [63:0] a;
+ input [639:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \5122 = b[63:0];
+ 10'b????????1?:
+ \5122 = b[127:64];
+ 10'b???????1??:
+ \5122 = b[191:128];
+ 10'b??????1???:
+ \5122 = b[255:192];
+ 10'b?????1????:
+ \5122 = b[319:256];
+ 10'b????1?????:
+ \5122 = b[383:320];
+ 10'b???1??????:
+ \5122 = b[447:384];
+ 10'b??1???????:
+ \5122 = b[511:448];
+ 10'b?1????????:
+ \5122 = b[575:512];
+ 10'b1?????????:
+ \5122 = b[639:576];
+ default:
+ \5122 = a;
+ endcase
+ endfunction
+ assign reg_out = \5122 (64'h0000000000000000, { 95'h00000000817d784000000000, uinfo_16550, 157'h005f5e1000000000000000000000000000000000, reg_ctrl, 64'h0000000002faf080, reg_dramiinfo, reg_draminfo, 121'h0000000000000200000000000000000, info_has_urt1, 1'h1, info_has_leth, info_has_spif, info_has_bram, info_has_dram, info_has_uart, 64'hf00daa5500010001 }, { _11_, _10_, _09_, _08_, _07_, _06_, _05_, _04_, _03_, _02_ });
+ assign _12_ = wishbone_in[2] ? reg_out[63:32] : reg_out[31:0];
+ always @(posedge clk)
+ _13_ <= { 1'h0, _01_, _12_ };
+ assign _14_ = wishbone_in[66] & wishbone_in[67];
+ assign _15_ = _14_ & wishbone_in[68];
+ assign _16_ = wishbone_in[8:3] == 6'h05;
+ assign _17_ = ~ wishbone_in[2];
+ assign _18_ = _16_ & _17_;
+ assign _19_ = _15_ & _18_;
+ assign _20_ = _19_ ? wishbone_in[32] : reg_ctrl[2];
+ assign _21_ = reg_ctrl[2] ? 1'h0 : _20_;
+ assign _22_ = _19_ ? wishbone_in[31] : reg_ctrl[1];
+ assign _23_ = reg_ctrl[1] ? 1'h0 : _22_;
+ assign _24_ = _19_ ? wishbone_in[30] : reg_ctrl[0];
+ assign _25_ = rst ? 3'h0 : { _21_, _23_, _24_ };
+ always @(posedge clk)
+ reg_ctrl <= _25_;
+ assign wishbone_out = _13_;
+ assign dram_at_0 = _00_;
+ assign core_reset = reg_ctrl[1];
+ assign soc_reset = reg_ctrl[2];
+endmodule
+
+module microwatt(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ ext_clk, ext_rst, uart0_rxd, uart1_rxd, spi_flash_sdat_i, jtag_tck, jtag_tdi, jtag_tms, jtag_trst, ib_data, ib_pty, gpio_in, alt_reset, uart0_txd, uart1_txd, spi_flash_cs_n, spi_flash_clk, spi_flash_sdat_o, spi_flash_sdat_oe, jtag_tdo, oib_clk, ob_data, ob_pty, gpio_out);
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [3:0] _03_;
+ wire [3:0] _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire [7:0] _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [31:0] _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ input alt_reset;
+ input ext_clk;
+ input ext_rst;
+ input [31:0] gpio_in;
+ output [31:0] gpio_out;
+ input [7:0] ib_data;
+ input ib_pty;
+ input jtag_tck;
+ input jtag_tdi;
+ output jtag_tdo;
+ input jtag_tms;
+ input jtag_trst;
+ output [7:0] ob_data;
+ output ob_pty;
+ output oib_clk;
+ output spi_flash_clk;
+ output spi_flash_cs_n;
+ input [3:0] spi_flash_sdat_i;
+ output [3:0] spi_flash_sdat_o;
+ output [3:0] spi_flash_sdat_oe;
+ wire system_rst;
+ input uart0_rxd;
+ output uart0_txd;
+ input uart1_rxd;
+ output uart1_txd;
+ wire [106:0] wb_dram_out;
+ wire [68:0] wb_ext_io_in;
+ wire wb_ext_is_eth;
+ wire [33:0] wb_logic_analyzer_out;
+ wire wb_mc_ack;
+ wire [63:0] wb_mc_dat_i;
+ wire wb_mc_stall;
+ assign _00_ = ~ ext_rst;
+ assign system_rst = 1'h1 ? _00_ : ext_rst;
+ assign _13_ = wb_ext_io_in[66] & wb_ext_is_eth;
+ logic_analyzer_32_32 logic_analyzer (
+ .clk(ext_clk),
+ .io_in(gpio_in),
+ .io_out(_12_),
+ .rst(system_rst),
+ .wb_in({ wb_ext_io_in[68:67], _13_, wb_ext_io_in[65:0] }),
+ .wb_out(wb_logic_analyzer_out)
+ );
+ mc_32_64_8_2_6fe71f186fa9a2db88063728b6660dc449d010db mc0 (
+ .clk(ext_clk),
+ .err(_10_),
+ .ib_data(ib_data),
+ .ib_pty(ib_pty),
+ .\int (_11_),
+ .ob_data(_08_),
+ .ob_pty(_09_),
+ .oib_clk(_07_),
+ .rst(system_rst),
+ .wb_ack(wb_mc_ack),
+ .wb_addr(wb_dram_out[31:0]),
+ .wb_cyc(wb_dram_out[104]),
+ .wb_err(_06_),
+ .wb_rd_data(wb_mc_dat_i),
+ .wb_sel(wb_dram_out[103:96]),
+ .wb_stall(wb_mc_stall),
+ .wb_stb(wb_dram_out[105]),
+ .wb_we(wb_dram_out[106]),
+ .wb_wr_data(wb_dram_out[95:32])
+ );
+ soc_4096_50000000_0_0_4_0_4_0_c832069ef22b63469d396707bc38511cc2410ddb soc0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .alt_reset(alt_reset),
+ .ext_irq_eth(1'h0),
+ .jtag_tck(jtag_tck),
+ .jtag_tdi(jtag_tdi),
+ .jtag_tdo(_05_),
+ .jtag_tms(jtag_tms),
+ .jtag_trst(jtag_trst),
+ .rst(system_rst),
+ .spi_flash_cs_n(_02_),
+ .spi_flash_sck(_01_),
+ .spi_flash_sdat_i(spi_flash_sdat_i),
+ .spi_flash_sdat_o(_03_),
+ .spi_flash_sdat_oe(_04_),
+ .system_clk(ext_clk),
+ .uart0_rxd(uart0_rxd),
+ .uart0_txd(_16_),
+ .uart1_rxd(uart1_rxd),
+ .uart1_txd(_17_),
+ .wb_dram_in(wb_dram_out),
+ .wb_dram_out({ wb_mc_stall, wb_mc_ack, wb_mc_dat_i }),
+ .wb_ext_io_in(wb_ext_io_in),
+ .wb_ext_io_out(wb_logic_analyzer_out),
+ .wb_ext_is_dram_csr(_14_),
+ .wb_ext_is_dram_init(_15_),
+ .wb_ext_is_eth(wb_ext_is_eth)
+ );
+ assign uart0_txd = _16_;
+ assign uart1_txd = _17_;
+ assign spi_flash_cs_n = _02_;
+ assign spi_flash_clk = _01_;
+ assign spi_flash_sdat_o = _03_;
+ assign spi_flash_sdat_oe = _04_;
+ assign jtag_tdo = _05_;
+ assign oib_clk = _07_;
+ assign ob_data = _08_;
+ assign ob_pty = _09_;
+ assign gpio_out = _12_;
+endmodule
+
+module wishbone_arbiter_3(clk, rst, wb_masters_in, wb_slave_in, wb_masters_out, wb_slave_out);
+ wire [1:0] _00_;
+ wire _01_;
+ wire [1:0] _02_;
+ wire [1:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire [1:0] _16_;
+ wire [1:0] _17_;
+ wire _18_;
+ wire [1:0] _19_;
+ wire [1:0] _20_;
+ wire [106:0] _21_;
+ wire [106:0] _22_;
+ wire [106:0] _23_;
+ wire [106:0] _24_;
+ wire [1:0] candidate;
+ input clk;
+ input rst;
+ reg [1:0] selected;
+ input [320:0] wb_masters_in;
+ output [197:0] wb_masters_out;
+ input [65:0] wb_slave_in;
+ output [106:0] wb_slave_out;
+ assign _00_ = 2'h2 - selected;
+ assign _01_ = ~ _22_[104];
+ assign _02_ = _01_ ? candidate : selected;
+ assign _03_ = 2'h2 - _02_;
+ assign _04_ = { 30'h00000000, _02_ } == 32'd0;
+ assign _05_ = _04_ ? wb_slave_in[64] : 1'h0;
+ assign _06_ = { 30'h00000000, _02_ } == 32'd0;
+ assign _07_ = _06_ ? wb_slave_in[65] : 1'h1;
+ assign _08_ = { 30'h00000000, _02_ } == 32'd1;
+ assign _09_ = _08_ ? wb_slave_in[64] : 1'h0;
+ assign _10_ = { 30'h00000000, _02_ } == 32'd1;
+ assign _11_ = _10_ ? wb_slave_in[65] : 1'h1;
+ assign _12_ = { 30'h00000000, _02_ } == 32'd2;
+ assign _13_ = _12_ ? wb_slave_in[64] : 1'h0;
+ assign _14_ = { 30'h00000000, _02_ } == 32'd2;
+ assign _15_ = _14_ ? wb_slave_in[65] : 1'h1;
+ assign _16_ = wb_masters_in[104] ? 2'h2 : selected;
+ assign _17_ = wb_masters_in[211] ? 2'h1 : _16_;
+ assign candidate = wb_masters_in[318] ? 2'h0 : _17_;
+ assign _18_ = ~ _22_[104];
+ assign _19_ = _18_ ? candidate : selected;
+ assign _20_ = rst ? 2'h0 : _19_;
+ always @(posedge clk)
+ selected <= _20_;
+ assign _21_ = _00_[0] ? wb_masters_in[213:107] : wb_masters_in[106:0];
+ assign _22_ = _00_[1] ? wb_masters_in[320:214] : _21_;
+ assign _23_ = _03_[0] ? wb_masters_in[213:107] : wb_masters_in[106:0];
+ assign _24_ = _03_[1] ? wb_masters_in[320:214] : _23_;
+ assign wb_masters_out = { _07_, _05_, wb_slave_in[63:0], _11_, _09_, wb_slave_in[63:0], _15_, _13_, wb_slave_in[63:0] };
+ assign wb_slave_out = _24_;
+endmodule
+
+module wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, rst, wishbone_in, wishbone_out);
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
+ wire [63:0] _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ reg ack;
+ reg ack_buf;
+ input clk;
+ wire ram_re;
+ wire ram_we;
+ input rst;
+ input [106:0] wishbone_in;
+ output [65:0] wishbone_out;
+ assign _01_ = wishbone_in[105] & wishbone_in[104];
+ assign ram_we = _01_ & wishbone_in[106];
+ assign _02_ = wishbone_in[105] & wishbone_in[104];
+ assign _03_ = ~ wishbone_in[106];
+ assign ram_re = _02_ & _03_;
+ assign _04_ = ~ wishbone_in[104];
+ assign _05_ = rst | _04_;
+ assign _06_ = ~ ack;
+ assign _07_ = ram_we & _06_;
+ assign _08_ = _07_ ? ack : wishbone_in[105];
+ assign _09_ = _07_ ? 1'h1 : ack;
+ assign _10_ = _05_ ? 1'h0 : _08_;
+ assign _11_ = _05_ ? 1'h0 : _09_;
+ always @(posedge clk)
+ ack <= _10_;
+ always @(posedge clk)
+ ack_buf <= _11_;
+ main_bram_64_10_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 ram_0 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .addr(wishbone_in[12:3]),
+ .clk(clk),
+ .di(wishbone_in[95:32]),
+ .\do (_00_),
+ .re(ram_re),
+ .sel(wishbone_in[103:96]),
+ .we(ram_we)
+ );
+ assign wishbone_out = { 1'h0, ack_buf, _00_ };
+endmodule
+
+module wishbone_debug_master(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, wb_in, dmi_dout, dmi_ack, wb_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [63:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire [3:0] _08_;
+ wire [63:0] _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire [10:0] _13_;
+ wire [63:0] _14_;
+ wire [10:0] _15_;
+ wire _16_;
+ wire [10:0] _17_;
+ wire [63:0] _18_;
+ wire [10:0] _19_;
+ wire [63:0] _20_;
+ wire [10:0] _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire [63:0] _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire [1:0] _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire [1:0] _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire [1:0] _45_;
+ wire _46_;
+ wire _47_;
+ wire [1:0] _48_;
+ wire _49_;
+ wire _50_;
+ wire [1:0] _51_;
+ wire _52_;
+ reg _53_;
+ input clk;
+ reg [63:0] data_latch;
+ output dmi_ack;
+ input [1:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ input dmi_req;
+ input dmi_wr;
+ reg do_inc;
+ reg [63:0] reg_addr;
+ reg [10:0] reg_ctrl;
+ input rst;
+ reg [1:0] state;
+ input [65:0] wb_in;
+ output [106:0] wb_out;
+ assign _00_ = dmi_addr == 2'h0;
+ assign _01_ = dmi_addr == 2'h1;
+ assign _02_ = dmi_addr == 2'h2;
+ function [63:0] \7094 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \7094 = b[63:0];
+ 3'b?1?:
+ \7094 = b[127:64];
+ 3'b1??:
+ \7094 = b[191:128];
+ default:
+ \7094 = a;
+ endcase
+ endfunction
+ assign _03_ = \7094 (64'h0000000000000000, { 53'h00000000000000, reg_ctrl, data_latch, reg_addr }, { _02_, _01_, _00_ });
+ assign _04_ = reg_ctrl[10:9] == 2'h0;
+ assign _05_ = reg_ctrl[10:9] == 2'h1;
+ assign _06_ = reg_ctrl[10:9] == 2'h2;
+ assign _07_ = reg_ctrl[10:9] == 2'h3;
+ function [3:0] \7117 ;
+ input [3:0] a;
+ input [15:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \7117 = b[3:0];
+ 4'b??1?:
+ \7117 = b[7:4];
+ 4'b?1??:
+ \7117 = b[11:8];
+ 4'b1???:
+ \7117 = b[15:12];
+ default:
+ \7117 = a;
+ endcase
+ endfunction
+ assign _08_ = \7117 (4'h8, 16'h8421, { _07_, _06_, _05_, _04_ });
+ assign _09_ = reg_addr + { 60'h000000000000000, _08_ };
+ assign _10_ = dmi_req & dmi_wr;
+ assign _11_ = dmi_addr == 2'h0;
+ assign _12_ = dmi_addr == 2'h2;
+ assign _13_ = _12_ ? dmi_din[10:0] : reg_ctrl;
+ assign _14_ = _16_ ? dmi_din : reg_addr;
+ assign _15_ = _11_ ? reg_ctrl : _13_;
+ assign _16_ = _10_ & _11_;
+ assign _17_ = _10_ ? _15_ : reg_ctrl;
+ assign _18_ = do_inc ? _09_ : _14_;
+ assign _19_ = do_inc ? reg_ctrl : _17_;
+ assign _20_ = rst ? 64'h0000000000000000 : _18_;
+ assign _21_ = rst ? 11'h000 : _19_;
+ always @(posedge clk)
+ reg_addr <= _20_;
+ always @(posedge clk)
+ reg_ctrl <= _21_;
+ assign _22_ = dmi_addr != 2'h1;
+ assign _23_ = state == 2'h2;
+ assign _24_ = _22_ | _23_;
+ assign _25_ = _24_ ? dmi_req : 1'h0;
+ assign _26_ = state == 2'h1;
+ assign _27_ = _26_ ? 1'h1 : 1'h0;
+ assign _28_ = state == 2'h1;
+ assign _29_ = _28_ & wb_in[64];
+ assign _30_ = ~ dmi_wr;
+ assign _31_ = _29_ & _30_;
+ assign _32_ = _31_ ? wb_in[63:0] : data_latch;
+ always @(posedge clk)
+ data_latch <= _32_;
+ assign _33_ = dmi_addr == 2'h1;
+ assign _34_ = dmi_req & _33_;
+ assign _35_ = _34_ ? 1'h1 : _53_;
+ assign _36_ = _34_ ? 2'h1 : state;
+ assign _37_ = state == 2'h0;
+ assign _38_ = ~ wb_in[65];
+ assign _39_ = _38_ ? 1'h0 : _53_;
+ assign _40_ = wb_in[64] ? 1'h0 : _39_;
+ assign _41_ = wb_in[64] ? 2'h2 : state;
+ assign _42_ = wb_in[64] ? reg_ctrl[8] : do_inc;
+ assign _43_ = state == 2'h1;
+ assign _44_ = ~ dmi_req;
+ assign _45_ = _44_ ? 2'h0 : state;
+ assign _46_ = state == 2'h2;
+ function [0:0] \7206 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \7206 = b[0:0];
+ 3'b?1?:
+ \7206 = b[1:1];
+ 3'b1??:
+ \7206 = b[2:2];
+ default:
+ \7206 = a;
+ endcase
+ endfunction
+ assign _47_ = \7206 (1'hx, { _53_, _40_, _35_ }, { _46_, _43_, _37_ });
+ function [1:0] \7208 ;
+ input [1:0] a;
+ input [5:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \7208 = b[1:0];
+ 3'b?1?:
+ \7208 = b[3:2];
+ 3'b1??:
+ \7208 = b[5:4];
+ default:
+ \7208 = a;
+ endcase
+ endfunction
+ assign _48_ = \7208 (2'hx, { _45_, _41_, _36_ }, { _46_, _43_, _37_ });
+ function [0:0] \7211 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \7211 = b[0:0];
+ 3'b?1?:
+ \7211 = b[1:1];
+ 3'b1??:
+ \7211 = b[2:2];
+ default:
+ \7211 = a;
+ endcase
+ endfunction
+ assign _49_ = \7211 (1'hx, { 1'h0, _42_, do_inc }, { _46_, _43_, _37_ });
+ assign _50_ = rst ? 1'h0 : _47_;
+ assign _51_ = rst ? 2'h0 : _48_;
+ assign _52_ = rst ? 1'h0 : _49_;
+ always @(posedge clk)
+ _53_ <= _50_;
+ always @(posedge clk)
+ state <= _51_;
+ always @(posedge clk)
+ do_inc <= _52_;
+ assign dmi_dout = _03_;
+ assign dmi_ack = _25_;
+ assign wb_out = { dmi_wr, _53_, _27_, reg_ctrl[7:0], dmi_din, reg_addr[31:0] };
+endmodule
+
+module writeback(clk, e_in, l_in, fp_in, w_out, c_out, complete_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [71:0] _03_;
+ wire [5:0] _04_;
+ wire [71:0] _05_;
+ wire [71:0] _06_;
+ wire [8:0] _07_;
+ wire [8:0] _08_;
+ wire [8:0] _09_;
+ wire [3:0] _10_;
+ wire [3:0] _11_;
+ wire [3:0] _12_;
+ wire [27:0] _13_;
+ wire [27:0] _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire [8:0] _27_;
+ wire [3:0] _28_;
+ wire [71:0] _29_;
+ wire [46:0] _30_;
+ output [46:0] c_out;
+ input clk;
+ output complete_out;
+ input [193:0] e_in;
+ input [113:0] fp_in;
+ input [79:0] l_in;
+ output [71:0] w_out;
+ assign _00_ = e_in[0] | l_in[0];
+ assign _01_ = _00_ | fp_in[0];
+ assign _02_ = _01_ ? 1'h1 : 1'h0;
+ assign _03_ = e_in[3] ? { 1'h1, e_in[74:4] } : 72'h000000000000000000;
+ assign _04_ = e_in[116] ? { e_in[121:117], 1'h1 } : 6'h00;
+ assign _05_ = fp_in[1] ? { 1'h1, fp_in[72:2] } : _03_;
+ assign _06_ = l_in[1] ? { 1'h1, l_in[72:2] } : _05_;
+ assign _07_ = e_in[75] ? { e_in[83:76], 1'h1 } : 9'h000;
+ assign _08_ = fp_in[73] ? { fp_in[81:74], 1'h1 } : _07_;
+ assign _09_ = l_in[78] ? 9'h101 : _08_;
+ assign _10_ = e_in[75] ? e_in[115:112] : 4'h0;
+ assign _11_ = fp_in[73] ? fp_in[113:110] : _10_;
+ assign _12_ = l_in[78] ? { 2'h0, l_in[79], l_in[77] } : _11_;
+ assign _13_ = e_in[75] ? e_in[111:84] : 28'h0000000;
+ assign _14_ = fp_in[73] ? fp_in[109:82] : _13_;
+ assign _15_ = e_in[1] & e_in[3];
+ assign _16_ = | e_in[42:11];
+ assign _17_ = ~ _16_;
+ assign _18_ = ~ e_in[2];
+ assign _19_ = | e_in[74:43];
+ assign _20_ = ~ _19_;
+ assign _21_ = _17_ & _20_;
+ assign _22_ = _18_ ? _21_ : _17_;
+ assign _23_ = _18_ ? e_in[74] : e_in[42];
+ assign _24_ = ~ _23_;
+ assign _25_ = ~ _22_;
+ assign _26_ = _24_ & _25_;
+ assign _27_ = _15_ ? 9'h101 : _09_;
+ assign _28_ = _15_ ? { _23_, _26_, _22_, e_in[121] } : _12_;
+ assign _29_ = e_in[122] ? { 1'h1, e_in[193:123] } : _06_;
+ assign _30_ = e_in[122] ? 47'h000000000000 : { _04_, _28_, _14_, _27_ };
+ assign w_out = _29_;
+ assign c_out = _30_;
+ assign complete_out = _02_;
+endmodule
+
+module xics_icp(clk, rst, wb_in, ics_in, wb_out, core_irq_out);
+ reg _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire [7:0] _05_;
+ wire [7:0] _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire [23:0] _13_;
+ wire [7:0] _14_;
+ wire _15_;
+ wire [31:0] _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire [31:0] _20_;
+ wire _21_;
+ wire [23:0] _22_;
+ wire [7:0] _23_;
+ wire _24_;
+ wire [23:0] _25_;
+ wire [7:0] _26_;
+ wire [7:0] _27_;
+ wire [7:0] _28_;
+ wire [7:0] _29_;
+ wire _30_;
+ wire _31_;
+ input clk;
+ output core_irq_out;
+ input [11:0] ics_in;
+ reg [73:0] r;
+ wire [73:0] r_next;
+ input rst;
+ input [68:0] wb_in;
+ output [33:0] wb_out;
+ always @(posedge clk)
+ _00_ <= r[40];
+ always @(posedge clk)
+ r <= r_next;
+ assign _01_ = wb_in[66] & wb_in[67];
+ assign _02_ = wb_in[7:0] == 8'h00;
+ assign _03_ = wb_in[7:0] == 8'h04;
+ assign _04_ = wb_in[7:0] == 8'h0c;
+ function [7:0] \6110 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \6110 = b[7:0];
+ 3'b?1?:
+ \6110 = b[15:8];
+ 3'b1??:
+ \6110 = b[23:16];
+ default:
+ \6110 = a;
+ endcase
+ endfunction
+ assign _05_ = \6110 (r[31:24], { r[31:24], wb_in[37:30], wb_in[37:30] }, { _04_, _03_, _02_ });
+ function [7:0] \6112 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \6112 = b[7:0];
+ 3'b?1?:
+ \6112 = b[15:8];
+ 3'b1??:
+ \6112 = b[23:16];
+ default:
+ \6112 = a;
+ endcase
+ endfunction
+ assign _06_ = \6112 (r[39:32], { wb_in[37:30], r[39:32], r[39:32] }, { _04_, _03_, _02_ });
+ assign _07_ = wb_in[7:0] == 8'h00;
+ assign _08_ = wb_in[65:62] == 4'hf;
+ assign _09_ = _08_ ? 1'h1 : 1'h0;
+ assign _10_ = wb_in[7:0] == 8'h04;
+ assign _11_ = wb_in[7:0] == 8'h0c;
+ function [0:0] \6135 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \6135 = b[0:0];
+ 3'b?1?:
+ \6135 = b[1:1];
+ 3'b1??:
+ \6135 = b[2:2];
+ default:
+ \6135 = a;
+ endcase
+ endfunction
+ assign _12_ = \6135 (1'h0, { 1'h0, _09_, 1'h0 }, { _11_, _10_, _07_ });
+ function [23:0] \6139 ;
+ input [23:0] a;
+ input [71:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \6139 = b[23:0];
+ 3'b?1?:
+ \6139 = b[47:24];
+ 3'b1??:
+ \6139 = b[71:48];
+ default:
+ \6139 = a;
+ endcase
+ endfunction
+ assign _13_ = \6139 (24'h000000, { 24'h000000, r[23:0], r[23:0] }, { _11_, _10_, _07_ });
+ function [7:0] \6143 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \6143 = b[7:0];
+ 3'b?1?:
+ \6143 = b[15:8];
+ 3'b1??:
+ \6143 = b[23:16];
+ default:
+ \6143 = a;
+ endcase
+ endfunction
+ assign _14_ = \6143 (8'h00, { r[39:24], r[31:24] }, { _11_, _10_, _07_ });
+ assign _15_ = wb_in[68] ? 1'h0 : _12_;
+ assign _16_ = wb_in[68] ? 32'd0 : { _14_, _13_ };
+ assign _17_ = _01_ & wb_in[68];
+ assign _18_ = _01_ ? 1'h1 : 1'h0;
+ assign _19_ = _01_ ? _15_ : 1'h0;
+ assign _20_ = _01_ ? _16_ : 32'd0;
+ assign _21_ = ics_in[11:4] != 8'hff;
+ assign _22_ = _21_ ? { 20'h00001, ics_in[3:0] } : 24'h000000;
+ assign _23_ = _21_ ? ics_in[11:4] : 8'hff;
+ assign _24_ = r[39:32] < _23_;
+ assign _25_ = _24_ ? 24'h000002 : _22_;
+ assign _26_ = _24_ ? r[39:32] : _23_;
+ assign _27_ = _17_ ? _05_ : r[31:24];
+ assign _28_ = _19_ ? _26_ : _27_;
+ assign _29_ = _17_ ? _06_ : r[39:32];
+ assign _30_ = _26_ < _28_;
+ assign _31_ = _30_ ? 1'h1 : 1'h0;
+ assign r_next = rst ? 74'h000000000ff00000000 : { _18_, _20_[7:0], _20_[15:8], _20_[23:16], _20_[31:24], _31_, _29_, _28_, _25_ };
+ assign wb_out = { 1'h0, r[73:41] };
+ assign core_irq_out = _00_;
+endmodule
+
+module xics_ics_16_3(clk, rst, wb_in, int_level_in, wb_out, icp_out);
+ wire _000_;
+ wire _001_;
+ wire [3:0] _002_;
+ wire _003_;
+ wire [7:0] _004_;
+ wire [31:0] _005_;
+ wire [31:0] _006_;
+ wire [31:0] _007_;
+ reg [32:0] _008_;
+ wire _009_;
+ wire [3:0] _010_;
+ wire [47:0] _011_;
+ wire _012_;
+ wire [47:0] _013_;
+ reg [11:0] _014_;
+ wire _015_;
+ wire _016_;
+ wire [2:0] _017_;
+ wire _018_;
+ wire _019_;
+ wire [3:0] _020_;
+ wire [2:0] _021_;
+ wire _022_;
+ wire _023_;
+ wire [3:0] _024_;
+ wire [2:0] _025_;
+ wire _026_;
+ wire _027_;
+ wire [3:0] _028_;
+ wire [2:0] _029_;
+ wire _030_;
+ wire _031_;
+ wire [3:0] _032_;
+ wire [2:0] _033_;
+ wire _034_;
+ wire _035_;
+ wire [3:0] _036_;
+ wire [2:0] _037_;
+ wire _038_;
+ wire _039_;
+ wire [3:0] _040_;
+ wire [2:0] _041_;
+ wire _042_;
+ wire _043_;
+ wire [3:0] _044_;
+ wire [2:0] _045_;
+ wire _046_;
+ wire _047_;
+ wire [3:0] _048_;
+ wire [2:0] _049_;
+ wire _050_;
+ wire _051_;
+ wire [3:0] _052_;
+ wire [2:0] _053_;
+ wire _054_;
+ wire _055_;
+ wire [3:0] _056_;
+ wire [2:0] _057_;
+ wire _058_;
+ wire _059_;
+ wire [3:0] _060_;
+ wire [2:0] _061_;
+ wire _062_;
+ wire _063_;
+ wire [3:0] _064_;
+ wire [2:0] _065_;
+ wire _066_;
+ wire _067_;
+ wire [3:0] _068_;
+ wire [2:0] _069_;
+ wire _070_;
+ wire _071_;
+ wire [3:0] _072_;
+ wire [2:0] _073_;
+ wire _074_;
+ wire _075_;
+ wire [3:0] _076_;
+ wire [2:0] _077_;
+ wire _078_;
+ wire [7:0] _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire [2:0] _090_;
+ wire [2:0] _091_;
+ wire [2:0] _092_;
+ wire [2:0] _093_;
+ wire [2:0] _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire [2:0] _127_;
+ wire [2:0] _128_;
+ wire [2:0] _129_;
+ wire [2:0] _130_;
+ wire [2:0] _131_;
+ wire [2:0] _132_;
+ wire [2:0] _133_;
+ wire [2:0] _134_;
+ wire [2:0] _135_;
+ wire [2:0] _136_;
+ wire [2:0] _137_;
+ wire [2:0] _138_;
+ wire [2:0] _139_;
+ wire [2:0] _140_;
+ wire [2:0] _141_;
+ wire [2:0] _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire [2:0] _153_;
+ wire [2:0] _154_;
+ wire [2:0] _155_;
+ wire [2:0] _156_;
+ wire [2:0] _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire [2:0] _168_;
+ wire [2:0] _169_;
+ wire [2:0] _170_;
+ wire [2:0] _171_;
+ wire [2:0] _172_;
+ input clk;
+ output [11:0] icp_out;
+ input [15:0] int_level_in;
+ reg [15:0] int_level_l;
+ wire reg_is_config;
+ wire reg_is_debug;
+ input rst;
+ input [68:0] wb_in;
+ output [33:0] wb_out;
+ wire wb_valid;
+ reg [47:0] xives;
+ assign _143_ = wb_in[2] ? int_level_l[1] : int_level_l[0];
+ assign _144_ = wb_in[2] ? int_level_l[5] : int_level_l[4];
+ assign _145_ = wb_in[2] ? int_level_l[9] : int_level_l[8];
+ assign _146_ = wb_in[2] ? int_level_l[13] : int_level_l[12];
+ assign _147_ = wb_in[4] ? _081_ : _080_;
+ assign _148_ = wb_in[2] ? int_level_l[1] : int_level_l[0];
+ assign _149_ = wb_in[2] ? int_level_l[5] : int_level_l[4];
+ assign _150_ = wb_in[2] ? int_level_l[9] : int_level_l[8];
+ assign _151_ = wb_in[2] ? int_level_l[13] : int_level_l[12];
+ assign _152_ = wb_in[4] ? _086_ : _085_;
+ assign _153_ = _002_[0] ? xives[5:3] : xives[2:0];
+ assign _154_ = _002_[0] ? xives[17:15] : xives[14:12];
+ assign _155_ = _002_[0] ? xives[29:27] : xives[26:24];
+ assign _156_ = _002_[0] ? xives[41:39] : xives[38:36];
+ assign _157_ = _002_[2] ? _091_ : _090_;
+ assign _158_ = wb_in[2] ? int_level_l[3] : int_level_l[2];
+ assign _159_ = wb_in[2] ? int_level_l[7] : int_level_l[6];
+ assign _160_ = wb_in[2] ? int_level_l[11] : int_level_l[10];
+ assign _161_ = wb_in[2] ? int_level_l[15] : int_level_l[14];
+ assign _162_ = wb_in[4] ? _083_ : _082_;
+ assign _163_ = wb_in[2] ? int_level_l[3] : int_level_l[2];
+ assign _164_ = wb_in[2] ? int_level_l[7] : int_level_l[6];
+ assign _165_ = wb_in[2] ? int_level_l[11] : int_level_l[10];
+ assign _166_ = wb_in[2] ? int_level_l[15] : int_level_l[14];
+ assign _167_ = wb_in[4] ? _088_ : _087_;
+ assign _168_ = _002_[0] ? xives[11:9] : xives[8:6];
+ assign _169_ = _002_[0] ? xives[23:21] : xives[20:18];
+ assign _170_ = _002_[0] ? xives[35:33] : xives[32:30];
+ assign _171_ = _002_[0] ? xives[47:45] : xives[44:42];
+ assign _172_ = _002_[2] ? _093_ : _092_;
+ assign _080_ = wb_in[3] ? _158_ : _143_;
+ assign _081_ = wb_in[3] ? _159_ : _144_;
+ assign _082_ = wb_in[3] ? _160_ : _145_;
+ assign _083_ = wb_in[3] ? _161_ : _146_;
+ assign _084_ = wb_in[5] ? _162_ : _147_;
+ assign _085_ = wb_in[3] ? _163_ : _148_;
+ assign _086_ = wb_in[3] ? _164_ : _149_;
+ assign _087_ = wb_in[3] ? _165_ : _150_;
+ assign _088_ = wb_in[3] ? _166_ : _151_;
+ assign _089_ = wb_in[5] ? _167_ : _152_;
+ assign _090_ = _002_[1] ? _168_ : _153_;
+ assign _091_ = _002_[1] ? _169_ : _154_;
+ assign _092_ = _002_[1] ? _170_ : _155_;
+ assign _093_ = _002_[1] ? _171_ : _156_;
+ assign _094_ = _002_[3] ? _172_ : _157_;
+ assign _000_ = wb_in[11:0] == 12'h000;
+ assign reg_is_config = _000_ ? 1'h1 : 1'h0;
+ assign _001_ = wb_in[11:0] == 12'h004;
+ assign reg_is_debug = _001_ ? 1'h1 : 1'h0;
+ always @(posedge clk)
+ int_level_l <= int_level_in;
+ assign wb_valid = wb_in[66] & wb_in[67];
+ assign _002_ = 4'hf - wb_in[5:2];
+ assign _003_ = _094_ == 3'h7;
+ assign _004_ = _003_ ? 8'hff : { 5'h00, _094_ };
+ assign _005_ = reg_is_debug ? { 20'h00000, _076_, _079_ } : 32'd0;
+ assign _006_ = reg_is_config ? 32'd50331664 : _005_;
+ assign _007_ = wb_in[11] ? { _084_, 1'h0, _089_, 21'h000000, _004_ } : _006_;
+ always @(posedge clk)
+ _008_ <= { wb_valid, _007_[7:0], _007_[15:8], _007_[23:16], _007_[31:24] };
+ assign _009_ = wb_valid & wb_in[68];
+ assign _010_ = 4'hf - wb_in[5:2];
+ assign _011_ = _012_ ? { _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_ } : xives;
+ assign _012_ = _009_ & wb_in[11];
+ assign _013_ = rst ? 48'hffffffffffff : _011_;
+ always @(posedge clk)
+ xives <= _013_;
+ always @(posedge clk)
+ _014_ <= { _079_, _076_ };
+ assign _015_ = xives[47:45] < 3'h7;
+ assign _016_ = int_level_l[0] & _015_;
+ assign _017_ = _016_ ? xives[47:45] : 3'h7;
+ assign _018_ = xives[44:42] < _017_;
+ assign _019_ = int_level_l[1] & _018_;
+ assign _020_ = _019_ ? 4'h1 : 4'h0;
+ assign _021_ = _019_ ? xives[44:42] : _017_;
+ assign _022_ = xives[41:39] < _021_;
+ assign _023_ = int_level_l[2] & _022_;
+ assign _024_ = _023_ ? 4'h2 : _020_;
+ assign _025_ = _023_ ? xives[41:39] : _021_;
+ assign _026_ = xives[38:36] < _025_;
+ assign _027_ = int_level_l[3] & _026_;
+ assign _028_ = _027_ ? 4'h3 : _024_;
+ assign _029_ = _027_ ? xives[38:36] : _025_;
+ assign _030_ = xives[35:33] < _029_;
+ assign _031_ = int_level_l[4] & _030_;
+ assign _032_ = _031_ ? 4'h4 : _028_;
+ assign _033_ = _031_ ? xives[35:33] : _029_;
+ assign _034_ = xives[32:30] < _033_;
+ assign _035_ = int_level_l[5] & _034_;
+ assign _036_ = _035_ ? 4'h5 : _032_;
+ assign _037_ = _035_ ? xives[32:30] : _033_;
+ assign _038_ = xives[29:27] < _037_;
+ assign _039_ = int_level_l[6] & _038_;
+ assign _040_ = _039_ ? 4'h6 : _036_;
+ assign _041_ = _039_ ? xives[29:27] : _037_;
+ assign _042_ = xives[26:24] < _041_;
+ assign _043_ = int_level_l[7] & _042_;
+ assign _044_ = _043_ ? 4'h7 : _040_;
+ assign _045_ = _043_ ? xives[26:24] : _041_;
+ assign _046_ = xives[23:21] < _045_;
+ assign _047_ = int_level_l[8] & _046_;
+ assign _048_ = _047_ ? 4'h8 : _044_;
+ assign _049_ = _047_ ? xives[23:21] : _045_;
+ assign _050_ = xives[20:18] < _049_;
+ assign _051_ = int_level_l[9] & _050_;
+ assign _052_ = _051_ ? 4'h9 : _048_;
+ assign _053_ = _051_ ? xives[20:18] : _049_;
+ assign _054_ = xives[17:15] < _053_;
+ assign _055_ = int_level_l[10] & _054_;
+ assign _056_ = _055_ ? 4'ha : _052_;
+ assign _057_ = _055_ ? xives[17:15] : _053_;
+ assign _058_ = xives[14:12] < _057_;
+ assign _059_ = int_level_l[11] & _058_;
+ assign _060_ = _059_ ? 4'hb : _056_;
+ assign _061_ = _059_ ? xives[14:12] : _057_;
+ assign _062_ = xives[11:9] < _061_;
+ assign _063_ = int_level_l[12] & _062_;
+ assign _064_ = _063_ ? 4'hc : _060_;
+ assign _065_ = _063_ ? xives[11:9] : _061_;
+ assign _066_ = xives[8:6] < _065_;
+ assign _067_ = int_level_l[13] & _066_;
+ assign _068_ = _067_ ? 4'hd : _064_;
+ assign _069_ = _067_ ? xives[8:6] : _065_;
+ assign _070_ = xives[5:3] < _069_;
+ assign _071_ = int_level_l[14] & _070_;
+ assign _072_ = _071_ ? 4'he : _068_;
+ assign _073_ = _071_ ? xives[5:3] : _069_;
+ assign _074_ = xives[2:0] < _073_;
+ assign _075_ = int_level_l[15] & _074_;
+ assign _076_ = _075_ ? 4'hf : _072_;
+ assign _077_ = _075_ ? xives[2:0] : _073_;
+ assign _078_ = _077_ == 3'h7;
+ assign _079_ = _078_ ? 8'hff : { 5'h00, _077_ };
+ assign _095_ = ~ _010_[3];
+ assign _096_ = ~ _010_[2];
+ assign _097_ = _095_ & _096_;
+ assign _098_ = _095_ & _010_[2];
+ assign _099_ = _010_[3] & _096_;
+ assign _100_ = _010_[3] & _010_[2];
+ assign _101_ = ~ _010_[1];
+ assign _102_ = _097_ & _101_;
+ assign _103_ = _097_ & _010_[1];
+ assign _104_ = _098_ & _101_;
+ assign _105_ = _098_ & _010_[1];
+ assign _106_ = _099_ & _101_;
+ assign _107_ = _099_ & _010_[1];
+ assign _108_ = _100_ & _101_;
+ assign _109_ = _100_ & _010_[1];
+ assign _110_ = ~ _010_[0];
+ assign _111_ = _102_ & _110_;
+ assign _112_ = _102_ & _010_[0];
+ assign _113_ = _103_ & _110_;
+ assign _114_ = _103_ & _010_[0];
+ assign _115_ = _104_ & _110_;
+ assign _116_ = _104_ & _010_[0];
+ assign _117_ = _105_ & _110_;
+ assign _118_ = _105_ & _010_[0];
+ assign _119_ = _106_ & _110_;
+ assign _120_ = _106_ & _010_[0];
+ assign _121_ = _107_ & _110_;
+ assign _122_ = _107_ & _010_[0];
+ assign _123_ = _108_ & _110_;
+ assign _124_ = _108_ & _010_[0];
+ assign _125_ = _109_ & _110_;
+ assign _126_ = _109_ & _010_[0];
+ assign _127_ = _111_ ? wb_in[56:54] : xives[2:0];
+ assign _128_ = _112_ ? wb_in[56:54] : xives[5:3];
+ assign _129_ = _113_ ? wb_in[56:54] : xives[8:6];
+ assign _130_ = _114_ ? wb_in[56:54] : xives[11:9];
+ assign _131_ = _115_ ? wb_in[56:54] : xives[14:12];
+ assign _132_ = _116_ ? wb_in[56:54] : xives[17:15];
+ assign _133_ = _117_ ? wb_in[56:54] : xives[20:18];
+ assign _134_ = _118_ ? wb_in[56:54] : xives[23:21];
+ assign _135_ = _119_ ? wb_in[56:54] : xives[26:24];
+ assign _136_ = _120_ ? wb_in[56:54] : xives[29:27];
+ assign _137_ = _121_ ? wb_in[56:54] : xives[32:30];
+ assign _138_ = _122_ ? wb_in[56:54] : xives[35:33];
+ assign _139_ = _123_ ? wb_in[56:54] : xives[38:36];
+ assign _140_ = _124_ ? wb_in[56:54] : xives[41:39];
+ assign _141_ = _125_ ? wb_in[56:54] : xives[44:42];
+ assign _142_ = _126_ ? wb_in[56:54] : xives[47:45];
+ assign wb_out = { 1'h0, _008_ };
+ assign icp_out = _014_;
+endmodule
+
+module zero_counter(clk, rs, count_right, is_32bit, result);
+ wire _000_;
+ wire _001_;
+ wire [63:0] _002_;
+ wire _003_;
+ wire [31:0] _004_;
+ wire [63:0] _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ input clk;
+ input count_right;
+ wire [63:0] inp;
+ input is_32bit;
+ reg msb_r;
+ wire [63:0] onehot;
+ reg [63:0] onehot_r;
+ output [63:0] result;
+ input [63:0] rs;
+ wire [64:0] sum;
+ always @(posedge clk)
+ msb_r <= sum[64];
+ always @(posedge clk)
+ onehot_r <= onehot;
+ assign _000_ = ~ is_32bit;
+ assign _001_ = ~ count_right;
+ assign _002_ = _001_ ? { rs[0], rs[1], rs[2], rs[3], rs[4], rs[5], rs[6], rs[7], rs[8], rs[9], rs[10], rs[11], rs[12], rs[13], rs[14], rs[15], rs[16], rs[17], rs[18], rs[19], rs[20], rs[21], rs[22], rs[23], rs[24], rs[25], rs[26], rs[27], rs[28], rs[29], rs[30], rs[31], rs[32], rs[33], rs[34], rs[35], rs[36], rs[37], rs[38], rs[39], rs[40], rs[41], rs[42], rs[43], rs[44], rs[45], rs[46], rs[47], rs[48], rs[49], rs[50], rs[51], rs[52], rs[53], rs[54], rs[55], rs[56], rs[57], rs[58], rs[59], rs[60], rs[61], rs[62], rs[63] } : rs;
+ assign _003_ = ~ count_right;
+ assign _004_ = _003_ ? { rs[0], rs[1], rs[2], rs[3], rs[4], rs[5], rs[6], rs[7], rs[8], rs[9], rs[10], rs[11], rs[12], rs[13], rs[14], rs[15], rs[16], rs[17], rs[18], rs[19], rs[20], rs[21], rs[22], rs[23], rs[24], rs[25], rs[26], rs[27], rs[28], rs[29], rs[30], rs[31] } : rs[31:0];
+ assign inp = _000_ ? _002_ : { 32'hffffffff, _004_ };
+ assign _005_ = ~ inp;
+ assign sum = { 1'h0, _005_ } + 65'h00000000000000001;
+ assign onehot = sum[63:0] & inp;
+ assign _006_ = | onehot_r[1];
+ assign _007_ = 1'h0 | _006_;
+ assign _008_ = | onehot_r[3];
+ assign _009_ = _007_ | _008_;
+ assign _010_ = | onehot_r[5];
+ assign _011_ = _009_ | _010_;
+ assign _012_ = | onehot_r[7];
+ assign _013_ = _011_ | _012_;
+ assign _014_ = | onehot_r[9];
+ assign _015_ = _013_ | _014_;
+ assign _016_ = | onehot_r[11];
+ assign _017_ = _015_ | _016_;
+ assign _018_ = | onehot_r[13];
+ assign _019_ = _017_ | _018_;
+ assign _020_ = | onehot_r[15];
+ assign _021_ = _019_ | _020_;
+ assign _022_ = | onehot_r[17];
+ assign _023_ = _021_ | _022_;
+ assign _024_ = | onehot_r[19];
+ assign _025_ = _023_ | _024_;
+ assign _026_ = | onehot_r[21];
+ assign _027_ = _025_ | _026_;
+ assign _028_ = | onehot_r[23];
+ assign _029_ = _027_ | _028_;
+ assign _030_ = | onehot_r[25];
+ assign _031_ = _029_ | _030_;
+ assign _032_ = | onehot_r[27];
+ assign _033_ = _031_ | _032_;
+ assign _034_ = | onehot_r[29];
+ assign _035_ = _033_ | _034_;
+ assign _036_ = | onehot_r[31];
+ assign _037_ = _035_ | _036_;
+ assign _038_ = | onehot_r[33];
+ assign _039_ = _037_ | _038_;
+ assign _040_ = | onehot_r[35];
+ assign _041_ = _039_ | _040_;
+ assign _042_ = | onehot_r[37];
+ assign _043_ = _041_ | _042_;
+ assign _044_ = | onehot_r[39];
+ assign _045_ = _043_ | _044_;
+ assign _046_ = | onehot_r[41];
+ assign _047_ = _045_ | _046_;
+ assign _048_ = | onehot_r[43];
+ assign _049_ = _047_ | _048_;
+ assign _050_ = | onehot_r[45];
+ assign _051_ = _049_ | _050_;
+ assign _052_ = | onehot_r[47];
+ assign _053_ = _051_ | _052_;
+ assign _054_ = | onehot_r[49];
+ assign _055_ = _053_ | _054_;
+ assign _056_ = | onehot_r[51];
+ assign _057_ = _055_ | _056_;
+ assign _058_ = | onehot_r[53];
+ assign _059_ = _057_ | _058_;
+ assign _060_ = | onehot_r[55];
+ assign _061_ = _059_ | _060_;
+ assign _062_ = | onehot_r[57];
+ assign _063_ = _061_ | _062_;
+ assign _064_ = | onehot_r[59];
+ assign _065_ = _063_ | _064_;
+ assign _066_ = | onehot_r[61];
+ assign _067_ = _065_ | _066_;
+ assign _068_ = | onehot_r[63];
+ assign _069_ = _067_ | _068_;
+ assign _070_ = | onehot_r[3:2];
+ assign _071_ = 1'h0 | _070_;
+ assign _072_ = | onehot_r[7:6];
+ assign _073_ = _071_ | _072_;
+ assign _074_ = | onehot_r[11:10];
+ assign _075_ = _073_ | _074_;
+ assign _076_ = | onehot_r[15:14];
+ assign _077_ = _075_ | _076_;
+ assign _078_ = | onehot_r[19:18];
+ assign _079_ = _077_ | _078_;
+ assign _080_ = | onehot_r[23:22];
+ assign _081_ = _079_ | _080_;
+ assign _082_ = | onehot_r[27:26];
+ assign _083_ = _081_ | _082_;
+ assign _084_ = | onehot_r[31:30];
+ assign _085_ = _083_ | _084_;
+ assign _086_ = | onehot_r[35:34];
+ assign _087_ = _085_ | _086_;
+ assign _088_ = | onehot_r[39:38];
+ assign _089_ = _087_ | _088_;
+ assign _090_ = | onehot_r[43:42];
+ assign _091_ = _089_ | _090_;
+ assign _092_ = | onehot_r[47:46];
+ assign _093_ = _091_ | _092_;
+ assign _094_ = | onehot_r[51:50];
+ assign _095_ = _093_ | _094_;
+ assign _096_ = | onehot_r[55:54];
+ assign _097_ = _095_ | _096_;
+ assign _098_ = | onehot_r[59:58];
+ assign _099_ = _097_ | _098_;
+ assign _100_ = | onehot_r[63:62];
+ assign _101_ = _099_ | _100_;
+ assign _102_ = | onehot_r[7:4];
+ assign _103_ = 1'h0 | _102_;
+ assign _104_ = | onehot_r[15:12];
+ assign _105_ = _103_ | _104_;
+ assign _106_ = | onehot_r[23:20];
+ assign _107_ = _105_ | _106_;
+ assign _108_ = | onehot_r[31:28];
+ assign _109_ = _107_ | _108_;
+ assign _110_ = | onehot_r[39:36];
+ assign _111_ = _109_ | _110_;
+ assign _112_ = | onehot_r[47:44];
+ assign _113_ = _111_ | _112_;
+ assign _114_ = | onehot_r[55:52];
+ assign _115_ = _113_ | _114_;
+ assign _116_ = | onehot_r[63:60];
+ assign _117_ = _115_ | _116_;
+ assign _118_ = | onehot_r[15:8];
+ assign _119_ = 1'h0 | _118_;
+ assign _120_ = | onehot_r[31:24];
+ assign _121_ = _119_ | _120_;
+ assign _122_ = | onehot_r[47:40];
+ assign _123_ = _121_ | _122_;
+ assign _124_ = | onehot_r[63:56];
+ assign _125_ = _123_ | _124_;
+ assign _126_ = | onehot_r[31:16];
+ assign _127_ = 1'h0 | _126_;
+ assign _128_ = | onehot_r[63:48];
+ assign _129_ = _127_ | _128_;
+ assign _130_ = | onehot_r[63:32];
+ assign _131_ = 1'h0 | _130_;
+ assign result = { 57'h000000000000000, msb_r, _131_, _129_, _125_, _117_, _101_, _069_ };
+endmodule
diff --git a/verilog/rtl/multiply_4.v b/verilog/rtl/multiply_4.v
new file mode 100644
index 0000000..ea40cde
--- /dev/null
+++ b/verilog/rtl/multiply_4.v
@@ -0,0 +1,51 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+module multiply_4(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, m_in, m_out);
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ wire [127:0] _00_;
+ wire [127:0] _01_;
+ wire [127:0] _02_;
+ wire [127:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ input clk;
+ reg [258:0] m = 259'h00000000000000000000000000000000000000000000000000000000000000000;
+ input [258:0] m_in;
+ output [129:0] m_out;
+ reg overflow;
+ wire ovf_in;
+ reg [523:0] r = 524'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ always @(posedge clk)
+ m <= m_in;
+ always @(posedge clk)
+ r <= { m[258:257], _01_, m[0], r[523:131] };
+ always @(posedge clk)
+ overflow <= ovf_in;
+ assign _00_ = $signed({ 64'h0000000000000000, m[64:1] }) * $signed({ 64'h0000000000000000, m[128:65] });
+ assign _01_ = _00_ + m[256:129];
+ assign _02_ = ~ r[259:132];
+ assign _03_ = r[261] ? _02_ : r[259:132];
+ assign _04_ = | _03_[63:31];
+ assign _05_ = & _03_[63:31];
+ assign _06_ = ~ _05_;
+ assign _07_ = _04_ & _06_;
+ assign _08_ = | _03_[127:63];
+ assign _09_ = & _03_[127:63];
+ assign _10_ = ~ _09_;
+ assign _11_ = _08_ & _10_;
+ assign ovf_in = r[260] ? _07_ : _11_;
+ assign m_out = { overflow, _03_, r[131] };
+endmodule
diff --git a/verilog/rtl/raminfr.v b/verilog/rtl/raminfr.v
new file mode 100644
index 0000000..090f751
--- /dev/null
+++ b/verilog/rtl/raminfr.v
@@ -0,0 +1,111 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// raminfr.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// Inferrable Distributed RAM for FIFOs ////
+//// ////
+//// Known problems (limits): ////
+//// None . ////
+//// ////
+//// To Do: ////
+//// Nothing so far. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// ////
+//// Created: 2002/07/22 ////
+//// Last Updated: 2002/07/22 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+
+//Following is the Verilog code for a dual-port RAM with asynchronous read.
+module raminfr
+ (clk, we, a, dpra, di, dpo);
+
+parameter addr_width = 4;
+parameter data_width = 8;
+parameter depth = 16;
+
+input clk;
+input we;
+input [addr_width-1:0] a;
+input [addr_width-1:0] dpra;
+input [data_width-1:0] di;
+//output [data_width-1:0] spo;
+output [data_width-1:0] dpo;
+reg [data_width-1:0] ram [depth-1:0];
+
+wire [data_width-1:0] dpo;
+wire [data_width-1:0] di;
+wire [addr_width-1:0] a;
+wire [addr_width-1:0] dpra;
+
+ always @(posedge clk) begin
+ if (we)
+ ram[a] <= di;
+ end
+// assign spo = ram[a];
+ assign dpo = ram[dpra];
+endmodule
+
diff --git a/verilog/rtl/register_file.v b/verilog/rtl/register_file.v
new file mode 100644
index 0000000..0dd97da
--- /dev/null
+++ b/verilog/rtl/register_file.v
@@ -0,0 +1,111 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+module register_file(
+`ifdef USE_POWER_PINS
+ vccd1, vssd1,
+`endif
+ clk, d_in, w_in, d_out);
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ wire _00_;
+ wire [4095:0] _01_;
+ wire [63:0] _02_;
+ wire [4095:0] _03_;
+ wire [63:0] _04_;
+ wire [63:0] _05_;
+ wire _06_;
+ wire [63:0] _07_;
+ wire _08_;
+ wire [63:0] _09_;
+ wire [191:0] _10_;
+ wire [4095:0] _11_;
+ wire [63:0] _12_;
+ input clk;
+ input [23:0] d_in;
+ output [191:0] d_out;
+ input [71:0] w_in;
+ reg [63:0] \$mem$\88 [63:0];
+ reg [63:0] \88 [63:0];
+ initial begin
+ \88 [0] = 64'h0000000000000000;
+ \88 [1] = 64'h0000000000000000;
+ \88 [2] = 64'h0000000000000000;
+ \88 [3] = 64'h0000000000000000;
+ \88 [4] = 64'h0000000000000000;
+ \88 [5] = 64'h0000000000000000;
+ \88 [6] = 64'h0000000000000000;
+ \88 [7] = 64'h0000000000000000;
+ \88 [8] = 64'h0000000000000000;
+ \88 [9] = 64'h0000000000000000;
+ \88 [10] = 64'h0000000000000000;
+ \88 [11] = 64'h0000000000000000;
+ \88 [12] = 64'h0000000000000000;
+ \88 [13] = 64'h0000000000000000;
+ \88 [14] = 64'h0000000000000000;
+ \88 [15] = 64'h0000000000000000;
+ \88 [16] = 64'h0000000000000000;
+ \88 [17] = 64'h0000000000000000;
+ \88 [18] = 64'h0000000000000000;
+ \88 [19] = 64'h0000000000000000;
+ \88 [20] = 64'h0000000000000000;
+ \88 [21] = 64'h0000000000000000;
+ \88 [22] = 64'h0000000000000000;
+ \88 [23] = 64'h0000000000000000;
+ \88 [24] = 64'h0000000000000000;
+ \88 [25] = 64'h0000000000000000;
+ \88 [26] = 64'h0000000000000000;
+ \88 [27] = 64'h0000000000000000;
+ \88 [28] = 64'h0000000000000000;
+ \88 [29] = 64'h0000000000000000;
+ \88 [30] = 64'h0000000000000000;
+ \88 [31] = 64'h0000000000000000;
+ \88 [32] = 64'h0000000000000000;
+ \88 [33] = 64'h0000000000000000;
+ \88 [34] = 64'h0000000000000000;
+ \88 [35] = 64'h0000000000000000;
+ \88 [36] = 64'h0000000000000000;
+ \88 [37] = 64'h0000000000000000;
+ \88 [38] = 64'h0000000000000000;
+ \88 [39] = 64'h0000000000000000;
+ \88 [40] = 64'h0000000000000000;
+ \88 [41] = 64'h0000000000000000;
+ \88 [42] = 64'h0000000000000000;
+ \88 [43] = 64'h0000000000000000;
+ \88 [44] = 64'h0000000000000000;
+ \88 [45] = 64'h0000000000000000;
+ \88 [46] = 64'h0000000000000000;
+ \88 [47] = 64'h0000000000000000;
+ \88 [48] = 64'h0000000000000000;
+ \88 [49] = 64'h0000000000000000;
+ \88 [50] = 64'h0000000000000000;
+ \88 [51] = 64'h0000000000000000;
+ \88 [52] = 64'h0000000000000000;
+ \88 [53] = 64'h0000000000000000;
+ \88 [54] = 64'h0000000000000000;
+ \88 [55] = 64'h0000000000000000;
+ \88 [56] = 64'h0000000000000000;
+ \88 [57] = 64'h0000000000000000;
+ \88 [58] = 64'h0000000000000000;
+ \88 [59] = 64'h0000000000000000;
+ \88 [60] = 64'h0000000000000000;
+ \88 [61] = 64'h0000000000000000;
+ \88 [62] = 64'h0000000000000000;
+ \88 [63] = 64'h0000000000000000;
+ end
+ always @(posedge clk) begin
+ if (w_in[71]) \88 [w_in[5:0]] <= w_in[70:7];
+ end
+ assign _12_ = \88 [d_in[22:17]];
+ assign _02_ = \88 [d_in[14:9]];
+ assign _04_ = \88 [d_in[6:1]];
+ assign _00_ = { 1'h0, d_in[6:1] } == { 1'h0, w_in[5:0] };
+ assign _05_ = _00_ ? w_in[70:7] : _04_;
+ assign _06_ = { 1'h0, d_in[14:9] } == { 1'h0, w_in[5:0] };
+ assign _07_ = _06_ ? w_in[70:7] : _02_;
+ assign _08_ = { 1'h0, d_in[22:17] } == { 1'h0, w_in[5:0] };
+ assign _09_ = _08_ ? w_in[70:7] : _12_;
+ assign _10_ = w_in[71] ? { _09_, _07_, _05_ } : { _12_, _02_, _04_ };
+ assign d_out = _10_;
+endmodule
diff --git a/verilog/rtl/tap_top.v b/verilog/rtl/tap_top.v
new file mode 100644
index 0000000..4a0e2ab
--- /dev/null
+++ b/verilog/rtl/tap_top.v
@@ -0,0 +1,636 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/01/18 09:27:39 simons
+// Blocking non blocking assignmenst fixed.
+//
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// Top module
+module tap_top #(parameter
+ IDCODE_VALUE = 32'h14d57049,
+ IR_LENGTH = 6)
+ (
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+//Internal constants
+localparam EXTEST = 6'b000000;
+localparam SAMPLE_PRELOAD = 6'b000001;
+localparam IDCODE = 6'b001001;
+localparam DEBUG = 6'b000011;
+localparam MBIST = 6'b001010;
+localparam BYPASS = 6'b111111;
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= tms_pad_i;
+ tms_q2 <= tms_q1;
+ tms_q3 <= tms_q2;
+ tms_q4 <= tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<= 1'b1;
+ else if (tms_reset)
+ test_logic_reset<= 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<= 1'b1;
+ else
+ test_logic_reset<= 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<= 1'b0;
+ else if (tms_reset)
+ run_test_idle<= 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<= 1'b1;
+ else
+ run_test_idle<= 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<= 1'b0;
+ else if (tms_reset)
+ select_dr_scan<= 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<= 1'b1;
+ else
+ select_dr_scan<= 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<= 1'b0;
+ else if (tms_reset)
+ capture_dr<= 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<= 1'b1;
+ else
+ capture_dr<= 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<= 1'b0;
+ else if (tms_reset)
+ shift_dr<= 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<= 1'b1;
+ else
+ shift_dr<= 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<= 1'b0;
+ else if (tms_reset)
+ exit1_dr<= 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<= 1'b1;
+ else
+ exit1_dr<= 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<= 1'b0;
+ else if (tms_reset)
+ pause_dr<= 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<= 1'b1;
+ else
+ pause_dr<= 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<= 1'b0;
+ else if (tms_reset)
+ exit2_dr<= 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<= 1'b1;
+ else
+ exit2_dr<= 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<= 1'b0;
+ else if (tms_reset)
+ update_dr<= 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<= 1'b1;
+ else
+ update_dr<= 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<= 1'b0;
+ else if (tms_reset)
+ select_ir_scan<= 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<= 1'b1;
+ else
+ select_ir_scan<= 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<= 1'b0;
+ else if (tms_reset)
+ capture_ir<= 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<= 1'b1;
+ else
+ capture_ir<= 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<= 1'b0;
+ else if (tms_reset)
+ shift_ir<= 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<= 1'b1;
+ else
+ shift_ir<= 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<= 1'b0;
+ else if (tms_reset)
+ exit1_ir<= 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<= 1'b1;
+ else
+ exit1_ir<= 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<= 1'b0;
+ else if (tms_reset)
+ pause_ir<= 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<= 1'b1;
+ else
+ pause_ir<= 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<= 1'b0;
+ else if (tms_reset)
+ exit2_ir<= 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<= 1'b1;
+ else
+ exit2_ir<= 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<= 1'b0;
+ else if (tms_reset)
+ update_ir<= 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<= 1'b1;
+ else
+ update_ir<= 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[IR_LENGTH-1:0] <= {IR_LENGTH{1'b0}};
+ else if(capture_ir)
+ jtag_ir <= 6'b000101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= idcode_reg[0];
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<= 1'b0;
+ else if(shift_dr)
+ bypass_reg<= tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <= bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <= IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <= IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <= jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ EXTEST: extest_select = 1'b1; // External test
+ SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ IDCODE: idcode_select = 1'b1; // ID Code
+ MBIST: mbist_select = 1'b1; // Mbist test
+ DEBUG: debug_select = 1'b1; // Debug
+ BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= shift_ir;
+ latched_jtag_ir_neg <= latched_jtag_ir;
+end
+
+
+endmodule
diff --git a/verilog/rtl/uart_defines.v b/verilog/rtl/uart_defines.v
new file mode 100644
index 0000000..fca7b6a
--- /dev/null
+++ b/verilog/rtl/uart_defines.v
@@ -0,0 +1,233 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_defines.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// Defines of the Core ////
+//// ////
+//// Known problems (limits): ////
+//// None ////
+//// ////
+//// To Do: ////
+//// Nothing. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2001/05/17 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.13 2003/06/11 16:37:47 gorban
+// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
+//
+// Revision 1.12 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.10 2001/12/11 08:55:40 mohor
+// Scratch register define added.
+//
+// Revision 1.9 2001/12/03 21:44:29 gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.8 2001/11/26 21:38:54 gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.7 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.6 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.5 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.4 2001/05/21 19:12:02 gorban
+// Corrected some Linter messages.
+//
+// Revision 1.3 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:11+02 jacob
+// Initial revision
+//
+//
+
+// Uncomment this if you want your UART to have
+// 16xBaudrate output port.
+// If defined, the enable signal will be used to drive baudrate_o signal
+// It's frequency is 16xbaudrate
+
+// `define UART_HAS_BAUDRATE_OUTPUT
+
+// Register addresses
+`define UART_REG_RB 3'd0 // receiver buffer
+`define UART_REG_TR 3'd0 // transmitter
+`define UART_REG_IE 3'd1 // Interrupt enable
+`define UART_REG_II 3'd2 // Interrupt identification
+`define UART_REG_FC 3'd2 // FIFO control
+`define UART_REG_LC 3'd3 // Line Control
+`define UART_REG_MC 3'd4 // Modem control
+`define UART_REG_LS 3'd5 // Line status
+`define UART_REG_MS 3'd6 // Modem status
+`define UART_REG_SR 3'd7 // Scratch register
+`define UART_REG_DL1 3'd0 // Divisor latch bytes (1-2)
+`define UART_REG_DL2 3'd1
+
+// Interrupt Enable register bits
+`define UART_IE_RDA 0 // Received Data available interrupt
+`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
+`define UART_IE_RLS 2 // Receiver Line Status Interrupt
+`define UART_IE_MS 3 // Modem Status Interrupt
+
+// Interrupt Identification register bits
+`define UART_II_IP 0 // Interrupt pending when 0
+`define UART_II_II 3:1 // Interrupt identification
+
+// Interrupt identification values for bits 3:1
+`define UART_II_RLS 3'b011 // Receiver Line Status
+`define UART_II_RDA 3'b010 // Receiver Data available
+`define UART_II_TI 3'b110 // Timeout Indication
+`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
+`define UART_II_MS 3'b000 // Modem Status
+
+// FIFO Control Register bits
+`define UART_FC_TL 1:0 // Trigger level
+
+// FIFO trigger level values
+`define UART_FC_1 2'b00
+`define UART_FC_4 2'b01
+`define UART_FC_8 2'b10
+`define UART_FC_14 2'b11
+
+// Line Control register bits
+`define UART_LC_BITS 1:0 // bits in character
+`define UART_LC_SB 2 // stop bits
+`define UART_LC_PE 3 // parity enable
+`define UART_LC_EP 4 // even parity
+`define UART_LC_SP 5 // stick parity
+`define UART_LC_BC 6 // Break control
+`define UART_LC_DL 7 // Divisor Latch access bit
+
+// Modem Control register bits
+`define UART_MC_DTR 0
+`define UART_MC_RTS 1
+`define UART_MC_OUT1 2
+`define UART_MC_OUT2 3
+`define UART_MC_LB 4 // Loopback mode
+
+// Line Status Register bits
+`define UART_LS_DR 0 // Data ready
+`define UART_LS_OE 1 // Overrun Error
+`define UART_LS_PE 2 // Parity Error
+`define UART_LS_FE 3 // Framing Error
+`define UART_LS_BI 4 // Break interrupt
+`define UART_LS_TFE 5 // Transmit FIFO is empty
+`define UART_LS_TE 6 // Transmitter Empty indicator
+`define UART_LS_EI 7 // Error indicator
+
+// Modem Status Register bits
+`define UART_MS_DCTS 0 // Delta signals
+`define UART_MS_DDSR 1
+`define UART_MS_TERI 2
+`define UART_MS_DDCD 3
+`define UART_MS_CCTS 4 // Complement signals
+`define UART_MS_CDSR 5
+`define UART_MS_CRI 6
+`define UART_MS_CDCD 7
+
+// FIFO parameter defines
+
+`define UART_FIFO_WIDTH 8
+`define UART_FIFO_DEPTH 16
+`define UART_FIFO_POINTER_W 4
+`define UART_FIFO_COUNTER_W 5
+// receiver fifo has width 11 because it has break, parity and framing error bits
+`define UART_FIFO_REC_WIDTH 11
+
+
+`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
+`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
+`define FAST_TEST 1 // 64/1024 packets are sent
+
+
+
+
+
+
+
diff --git a/verilog/rtl/uart_receiver.v b/verilog/rtl/uart_receiver.v
new file mode 100644
index 0000000..44c2936
--- /dev/null
+++ b/verilog/rtl/uart_receiver.v
@@ -0,0 +1,475 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_receiver.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core receiver logic ////
+//// ////
+//// Known problems (limits): ////
+//// None known ////
+//// ////
+//// To Do: ////
+//// Thourough testing. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2001/05/17 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.29 2002/07/29 21:16:18 gorban
+// The uart_defines.v file is included again in sources.
+//
+// Revision 1.28 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.27 2001/12/30 20:39:13 mohor
+// More than one character was stored in case of break. End of the break
+// was not detected correctly.
+//
+// Revision 1.26 2001/12/20 13:28:27 mohor
+// Missing declaration of rf_push_q fixed.
+//
+// Revision 1.25 2001/12/20 13:25:46 mohor
+// rx push changed to be only one cycle wide.
+//
+// Revision 1.24 2001/12/19 08:03:34 mohor
+// Warnings cleared.
+//
+// Revision 1.23 2001/12/19 07:33:54 mohor
+// Synplicity was having troubles with the comment.
+//
+// Revision 1.22 2001/12/17 14:46:48 mohor
+// overrun signal was moved to separate block because many sequential lsr
+// reads were preventing data from being written to rx fifo.
+// underrun signal was not used and was removed from the project.
+//
+// Revision 1.21 2001/12/13 10:31:16 mohor
+// timeout irq must be set regardless of the rda irq (rda irq does not reset the
+// timeout counter).
+//
+// Revision 1.20 2001/12/10 19:52:05 gorban
+// Igor fixed break condition bugs
+//
+// Revision 1.19 2001/12/06 14:51:04 gorban
+// Bug in LSR[0] is fixed.
+// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
+//
+// Revision 1.18 2001/12/03 21:44:29 gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.17 2001/11/28 19:36:39 gorban
+// Fixed: timeout and break didn't pay attention to current data format when counting time
+//
+// Revision 1.16 2001/11/27 22:17:09 gorban
+// Fixed bug that prevented synthesis in uart_receiver.v
+//
+// Revision 1.15 2001/11/26 21:38:54 gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.14 2001/11/10 12:43:21 gorban
+// Logic Synthesis bugs fixed. Some other minor changes
+//
+// Revision 1.13 2001/11/08 14:54:23 mohor
+// Comments in Slovene language deleted, few small fixes for better work of
+// old tools. IRQs need to be fix.
+//
+// Revision 1.12 2001/11/07 17:51:52 gorban
+// Heavily rewritten interrupt and LSR subsystems.
+// Many bugs hopefully squashed.
+//
+// Revision 1.11 2001/10/31 15:19:22 gorban
+// Fixes to break and timeout conditions
+//
+// Revision 1.10 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.9 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.8 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.6 2001/06/23 11:21:48 gorban
+// DL made 16-bit long. Fixed transmission/reception bugs.
+//
+// Revision 1.5 2001/06/02 14:28:14 gorban
+// Fixed receiver and transmitter. Major bug fixed.
+//
+// Revision 1.4 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.3 2001/05/27 17:37:49 gorban
+// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
+//
+// Revision 1.2 2001/05/21 19:12:02 gorban
+// Corrected some Linter messages.
+//
+// Revision 1.1 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:11+02 jacob
+// Initial revision
+//
+//
+
+`include "uart_defines.v"
+
+module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
+ counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
+
+input clk;
+input wb_rst_i;
+input [7:0] lcr;
+input rf_pop;
+input srx_pad_i;
+input enable;
+input rx_reset;
+input lsr_mask;
+
+output [9:0] counter_t;
+output [`UART_FIFO_COUNTER_W-1:0] rf_count;
+output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
+output rf_overrun;
+output rf_error_bit;
+output [3:0] rstate;
+output rf_push_pulse;
+
+reg [3:0] rstate;
+reg [3:0] rcounter16;
+reg [2:0] rbit_counter;
+reg [7:0] rshift; // receiver shift register
+reg rparity; // received parity
+reg rparity_error;
+reg rframing_error; // framing error flag
+reg rparity_xor;
+reg [7:0] counter_b; // counts the 0 (low) signals
+reg rf_push_q;
+
+// RX FIFO signals
+reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
+wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
+wire rf_push_pulse;
+reg rf_push;
+wire rf_pop;
+wire rf_overrun;
+wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
+wire rf_error_bit; // an error (parity or framing) is inside the fifo
+wire break_error = (counter_b == 0);
+
+// RX FIFO instance
+uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
+ .clk( clk ),
+ .wb_rst_i( wb_rst_i ),
+ .data_in( rf_data_in ),
+ .data_out( rf_data_out ),
+ .push( rf_push_pulse ),
+ .pop( rf_pop ),
+ .overrun( rf_overrun ),
+ .count( rf_count ),
+ .error_bit( rf_error_bit ),
+ .fifo_reset( rx_reset ),
+ .reset_status(lsr_mask)
+);
+
+wire rcounter16_eq_7 = (rcounter16 == 4'd7);
+wire rcounter16_eq_0 = (rcounter16 == 4'd0);
+
+wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1;
+
+parameter sr_idle = 4'd0;
+parameter sr_rec_start = 4'd1;
+parameter sr_rec_bit = 4'd2;
+parameter sr_rec_parity = 4'd3;
+parameter sr_rec_stop = 4'd4;
+parameter sr_check_parity = 4'd5;
+parameter sr_rec_prepare = 4'd6;
+parameter sr_end_bit = 4'd7;
+parameter sr_ca_lc_parity = 4'd8;
+parameter sr_wait1 = 4'd9;
+parameter sr_push = 4'd10;
+
+
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ begin
+ rstate <= sr_idle;
+ rcounter16 <= 0;
+ rbit_counter <= 0;
+ rparity_xor <= 1'b0;
+ rframing_error <= 1'b0;
+ rparity_error <= 1'b0;
+ rparity <= 1'b0;
+ rshift <= 0;
+ rf_push <= 1'b0;
+ rf_data_in <= 0;
+ end
+ else
+ if (enable)
+ begin
+ case (rstate)
+ sr_idle : begin
+ rf_push <= 1'b0;
+ rf_data_in <= 0;
+ rcounter16 <= 4'b1110;
+ if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
+ begin
+ rstate <= sr_rec_start;
+ end
+ end
+ sr_rec_start : begin
+ rf_push <= 1'b0;
+ if (rcounter16_eq_7) // check the pulse
+ if (srx_pad_i==1'b1) // no start bit
+ rstate <= sr_idle;
+ else // start bit detected
+ rstate <= sr_rec_prepare;
+ rcounter16 <= rcounter16_minus_1;
+ end
+ sr_rec_prepare:begin
+ case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
+ 2'b00 : rbit_counter <= 3'b100;
+ 2'b01 : rbit_counter <= 3'b101;
+ 2'b10 : rbit_counter <= 3'b110;
+ 2'b11 : rbit_counter <= 3'b111;
+ endcase
+ if (rcounter16_eq_0)
+ begin
+ rstate <= sr_rec_bit;
+ rcounter16 <= 4'b1110;
+ rshift <= 0;
+ end
+ else
+ rstate <= sr_rec_prepare;
+ rcounter16 <= rcounter16_minus_1;
+ end
+ sr_rec_bit : begin
+ if (rcounter16_eq_0)
+ rstate <= sr_end_bit;
+ if (rcounter16_eq_7) // read the bit
+ case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
+ 2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
+ 2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
+ 2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
+ 2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
+ endcase
+ rcounter16 <= rcounter16_minus_1;
+ end
+ sr_end_bit : begin
+ if (rbit_counter==3'b0) // no more bits in word
+ if (lcr[`UART_LC_PE]) // choose state based on parity
+ rstate <= sr_rec_parity;
+ else
+ begin
+ rstate <= sr_rec_stop;
+ rparity_error <= 1'b0; // no parity - no error :)
+ end
+ else // else we have more bits to read
+ begin
+ rstate <= sr_rec_bit;
+ rbit_counter <= rbit_counter - 3'd1;
+ end
+ rcounter16 <= 4'b1110;
+ end
+ sr_rec_parity: begin
+ if (rcounter16_eq_7) // read the parity
+ begin
+ rparity <= srx_pad_i;
+ rstate <= sr_ca_lc_parity;
+ end
+ rcounter16 <= rcounter16_minus_1;
+ end
+ sr_ca_lc_parity : begin // rcounter equals 6
+ rcounter16 <= rcounter16_minus_1;
+ rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data
+ rstate <= sr_check_parity;
+ end
+ sr_check_parity: begin // rcounter equals 5
+ case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
+ 2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1
+ 2'b01: rparity_error <= ~rparity; // parity should sticked to 1
+ 2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd
+ 2'b11: rparity_error <= rparity; // parity should be sticked to 0
+ endcase
+ rcounter16 <= rcounter16_minus_1;
+ rstate <= sr_wait1;
+ end
+ sr_wait1 : if (rcounter16_eq_0)
+ begin
+ rstate <= sr_rec_stop;
+ rcounter16 <= 4'b1110;
+ end
+ else
+ rcounter16 <= rcounter16_minus_1;
+ sr_rec_stop : begin
+ if (rcounter16_eq_7) // read the parity
+ begin
+ rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit)
+ rstate <= sr_push;
+ end
+ rcounter16 <= rcounter16_minus_1;
+ end
+ sr_push : begin
+///////////////////////////////////////
+// $display($time, ": received: %b", rf_data_in);
+ if(srx_pad_i | break_error)
+ begin
+ if(break_error)
+ rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
+ else
+ rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
+ rf_push <= 1'b1;
+ rstate <= sr_idle;
+ end
+ else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
+ begin
+ rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
+ rf_push <= 1'b1;
+ rcounter16 <= 4'b1110;
+ rstate <= sr_rec_start;
+ end
+
+ end
+ default : rstate <= sr_idle;
+ endcase
+ end // if (enable)
+end // always of receiver
+
+always @ (posedge clk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ rf_push_q <= 0;
+ else
+ rf_push_q <= rf_push;
+end
+
+assign rf_push_pulse = rf_push & ~rf_push_q;
+
+
+//
+// Break condition detection.
+// Works in conjuction with the receiver state machine
+
+reg [9:0] toc_value; // value to be set to timeout counter
+
+always @(lcr)
+ case (lcr[3:0])
+ 4'b0000 : toc_value = 447; // 7 bits
+ 4'b0100 : toc_value = 479; // 7.5 bits
+ 4'b0001, 4'b1000 : toc_value = 511; // 8 bits
+ 4'b1100 : toc_value = 543; // 8.5 bits
+ 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
+ 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
+ 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
+ 4'b1111 : toc_value = 767; // 12 bits
+ endcase // case(lcr[3:0])
+
+wire [7:0] brc_value; // value to be set to break counter
+assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
+
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ counter_b <= 8'd159;
+ else
+ if (srx_pad_i)
+ counter_b <= brc_value; // character time length - 1
+ else
+ if(enable & counter_b != 8'b0) // only work on enable times break not reached.
+ counter_b <= counter_b - 8'd1; // decrement break counter
+end // always of break condition detection
+
+///
+/// Timeout condition detection
+reg [9:0] counter_t; // counts the timeout condition clocks
+
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ counter_t <= 10'd639; // 10 bits for the default 8N1
+ else
+ if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
+ counter_t <= toc_value;
+ else
+ if (enable && counter_t != 10'b0) // we don't want to underflow
+ counter_t <= counter_t - 10'd1;
+end
+
+endmodule
diff --git a/verilog/rtl/uart_regs.v b/verilog/rtl/uart_regs.v
new file mode 100644
index 0000000..931632c
--- /dev/null
+++ b/verilog/rtl/uart_regs.v
@@ -0,0 +1,888 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_regs.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// Registers of the uart 16550 core ////
+//// ////
+//// Known problems (limits): ////
+//// Inserts 1 wait state in all WISHBONE transfers ////
+//// ////
+//// To Do: ////
+//// Nothing or verification. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: (See log for the revision history ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.41 2004/05/21 11:44:41 tadejm
+// Added synchronizer flops for RX input.
+//
+// Revision 1.40 2003/06/11 16:37:47 gorban
+// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
+//
+// Revision 1.39 2002/07/29 21:16:18 gorban
+// The uart_defines.v file is included again in sources.
+//
+// Revision 1.38 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.37 2001/12/27 13:24:09 mohor
+// lsr[7] was not showing overrun errors.
+//
+// Revision 1.36 2001/12/20 13:25:46 mohor
+// rx push changed to be only one cycle wide.
+//
+// Revision 1.35 2001/12/19 08:03:34 mohor
+// Warnings cleared.
+//
+// Revision 1.34 2001/12/19 07:33:54 mohor
+// Synplicity was having troubles with the comment.
+//
+// Revision 1.33 2001/12/17 10:14:43 mohor
+// Things related to msr register changed. After THRE IRQ occurs, and one
+// character is written to the transmit fifo, the detection of the THRE bit in the
+// LSR is delayed for one character time.
+//
+// Revision 1.32 2001/12/14 13:19:24 mohor
+// MSR register fixed.
+//
+// Revision 1.31 2001/12/14 10:06:58 mohor
+// After reset modem status register MSR should be reset.
+//
+// Revision 1.30 2001/12/13 10:09:13 mohor
+// thre irq should be cleared only when being source of interrupt.
+//
+// Revision 1.29 2001/12/12 09:05:46 mohor
+// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
+//
+// Revision 1.28 2001/12/10 19:52:41 gorban
+// Scratch register added
+//
+// Revision 1.27 2001/12/06 14:51:04 gorban
+// Bug in LSR[0] is fixed.
+// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
+//
+// Revision 1.26 2001/12/03 21:44:29 gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.25 2001/11/28 19:36:39 gorban
+// Fixed: timeout and break didn't pay attention to current data format when counting time
+//
+// Revision 1.24 2001/11/26 21:38:54 gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.23 2001/11/12 21:57:29 gorban
+// fixed more typo bugs
+//
+// Revision 1.22 2001/11/12 15:02:28 mohor
+// lsr1r error fixed.
+//
+// Revision 1.21 2001/11/12 14:57:27 mohor
+// ti_int_pnd error fixed.
+//
+// Revision 1.20 2001/11/12 14:50:27 mohor
+// ti_int_d error fixed.
+//
+// Revision 1.19 2001/11/10 12:43:21 gorban
+// Logic Synthesis bugs fixed. Some other minor changes
+//
+// Revision 1.18 2001/11/08 14:54:23 mohor
+// Comments in Slovene language deleted, few small fixes for better work of
+// old tools. IRQs need to be fix.
+//
+// Revision 1.17 2001/11/07 17:51:52 gorban
+// Heavily rewritten interrupt and LSR subsystems.
+// Many bugs hopefully squashed.
+//
+// Revision 1.16 2001/11/02 09:55:16 mohor
+// no message
+//
+// Revision 1.15 2001/10/31 15:19:22 gorban
+// Fixes to break and timeout conditions
+//
+// Revision 1.14 2001/10/29 17:00:46 gorban
+// fixed parity sending and tx_fifo resets over- and underrun
+//
+// Revision 1.13 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.12 2001/10/19 16:21:40 gorban
+// Changes data_out to be synchronous again as it should have been.
+//
+// Revision 1.11 2001/10/18 20:35:45 gorban
+// small fix
+//
+// Revision 1.10 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.9 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.10 2001/06/23 11:21:48 gorban
+// DL made 16-bit long. Fixed transmission/reception bugs.
+//
+// Revision 1.9 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.8 2001/05/29 20:05:04 gorban
+// Fixed some bugs and synthesis problems.
+//
+// Revision 1.7 2001/05/27 17:37:49 gorban
+// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
+//
+// Revision 1.6 2001/05/21 19:12:02 gorban
+// Corrected some Linter messages.
+//
+// Revision 1.5 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:11+02 jacob
+// Initial revision
+//
+//
+
+`include "uart_defines.v"
+
+`define UART_DL1 7:0
+`define UART_DL2 15:8
+
+module uart_regs
+#(parameter SIM = 0)
+ (clk,
+ wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
+
+// additional signals
+ modem_inputs,
+ stx_pad_o, srx_pad_i,
+
+ rts_pad_o, dtr_pad_o, int_o
+`ifdef UART_HAS_BAUDRATE_OUTPUT
+ , baud_o
+`endif
+
+ );
+
+input clk;
+input wb_rst_i;
+input [2:0] wb_addr_i;
+input [7:0] wb_dat_i;
+output [7:0] wb_dat_o;
+input wb_we_i;
+input wb_re_i;
+
+output stx_pad_o;
+input srx_pad_i;
+
+input [3:0] modem_inputs;
+output rts_pad_o;
+output dtr_pad_o;
+output int_o;
+`ifdef UART_HAS_BAUDRATE_OUTPUT
+output baud_o;
+`endif
+
+wire [3:0] modem_inputs;
+reg enable;
+`ifdef UART_HAS_BAUDRATE_OUTPUT
+assign baud_o = enable; // baud_o is actually the enable signal
+`endif
+
+
+wire stx_pad_o; // received from transmitter module
+wire srx_pad_i;
+wire srx_pad;
+
+reg [7:0] wb_dat_o;
+
+wire [2:0] wb_addr_i;
+wire [7:0] wb_dat_i;
+
+
+reg [3:0] ier;
+reg [3:0] iir;
+reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
+reg [4:0] mcr;
+reg [7:0] lcr;
+reg [7:0] msr;
+reg [15:0] dl; // 32-bit divisor latch
+reg [7:0] scratch; // UART scratch register
+reg start_dlc; // activate dlc on writing to UART_DL1
+reg lsr_mask_d; // delay for lsr_mask condition
+reg msi_reset; // reset MSR 4 lower bits indicator
+//reg threi_clear; // THRE interrupt clear flag
+reg [15:0] dlc; // 32-bit divisor latch counter
+reg int_o;
+
+reg [3:0] trigger_level; // trigger level of the receiver FIFO
+reg rx_reset;
+reg tx_reset;
+
+wire dlab; // divisor latch access bit
+wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
+wire loopback; // loopback bit (MCR bit 4)
+wire cts, dsr, ri, dcd; // effective signals
+wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
+wire rts_pad_o, dtr_pad_o; // modem control outputs
+
+// LSR bits wires and regs
+wire [7:0] lsr;
+wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
+reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
+wire lsr_mask; // lsr_mask
+
+//
+// ASSINGS
+//
+
+assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
+
+assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
+assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
+
+assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
+ : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
+
+assign dlab = lcr[`UART_LC_DL];
+assign loopback = mcr[4];
+
+// assign modem outputs
+assign rts_pad_o = mcr[`UART_MC_RTS];
+assign dtr_pad_o = mcr[`UART_MC_DTR];
+
+// Interrupt signals
+wire rls_int; // receiver line status interrupt
+wire rda_int; // receiver data available interrupt
+wire ti_int; // timeout indicator interrupt
+wire thre_int; // transmitter holding register empty interrupt
+wire ms_int; // modem status interrupt
+
+// FIFO signals
+reg tf_push;
+reg rf_pop;
+wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
+wire rf_error_bit; // an error (parity or framing) is inside the fifo
+wire rf_overrun;
+wire rf_push_pulse;
+wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
+wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
+wire [2:0] tstate;
+wire [3:0] rstate;
+wire [9:0] counter_t;
+
+wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
+reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
+reg [7:0] block_value; // One character length minus stop bit
+
+// Transmitter Instance
+wire serial_out;
+
+uart_transmitter #(.SIM (SIM)) transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
+
+ // Synchronizing and sampling serial RX input
+ uart_sync_flops i_uart_sync_flops
+ (
+ .rst_i (wb_rst_i),
+ .clk_i (clk),
+ .stage1_rst_i (1'b0),
+ .stage1_clk_en_i (1'b1),
+ .async_dat_i (srx_pad_i),
+ .sync_dat_o (srx_pad)
+ );
+ defparam i_uart_sync_flops.width = 1;
+ defparam i_uart_sync_flops.init_value = 1'b1;
+
+// handle loopback
+wire serial_in = loopback ? serial_out : srx_pad;
+assign stx_pad_o = loopback ? 1'b1 : serial_out;
+
+// Receiver Instance
+uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
+ counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
+
+
+// Asynchronous reading here because the outputs are sampled in uart_wb.v file
+always @(dl or dlab or ier or iir or scratch
+ or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
+begin
+ case (wb_addr_i)
+ `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
+ `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : {4'd0,ier};
+ `UART_REG_II : wb_dat_o = {4'b1100,iir};
+ `UART_REG_LC : wb_dat_o = lcr;
+ `UART_REG_LS : wb_dat_o = lsr;
+ `UART_REG_MS : wb_dat_o = msr;
+ `UART_REG_SR : wb_dat_o = scratch;
+ default: wb_dat_o = 8'b0; // ??
+ endcase // case(wb_addr_i)
+end // always @ (dl or dlab or ier or iir or scratch...
+
+
+// rf_pop signal handling
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ rf_pop <= 0;
+ else
+ if (rf_pop) // restore the signal to 0 after one clock cycle
+ rf_pop <= 0;
+ else
+ if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
+ rf_pop <= 1; // advance read pointer
+end
+
+wire lsr_mask_condition;
+wire iir_read;
+wire msr_read;
+wire fifo_read;
+wire fifo_write;
+
+assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
+assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
+assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
+assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
+assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
+
+// lsr_mask_d delayed signal handling
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ lsr_mask_d <= 0;
+ else // reset bits in the Line Status Register
+ lsr_mask_d <= lsr_mask_condition;
+end
+
+// lsr_mask is rise detected
+assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
+
+// msi_reset signal handling
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ msi_reset <= 1;
+ else
+ if (msi_reset)
+ msi_reset <= 0;
+ else
+ if (msr_read)
+ msi_reset <= 1; // reset bits in Modem Status Register
+end
+
+
+//
+// WRITES AND RESETS //
+//
+// Line Control Register
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ lcr <= 8'b00000011; // 8n1 setting
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_LC)
+ lcr <= wb_dat_i;
+
+// Interrupt Enable Register or UART_DL2
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ begin
+ ier <= 4'b0000; // no interrupts after reset
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL2] <= `PRESCALER_HIGH_PRESET;
+`else
+ dl[`UART_DL2] <= 8'b0;
+`endif
+ end
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_IE)
+ if (dlab)
+ begin
+ dl[`UART_DL2] <=
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL2];
+`else
+ wb_dat_i;
+`endif
+ end
+ else
+ ier <= wb_dat_i[3:0]; // ier uses only 4 lsb
+
+
+// FIFO Control Register and rx_reset, tx_reset signals
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) begin
+ fcr <= 2'b11;
+ rx_reset <= 0;
+ tx_reset <= 0;
+ end else
+ if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
+ fcr <= wb_dat_i[7:6];
+ rx_reset <= wb_dat_i[1];
+ tx_reset <= wb_dat_i[2];
+ end else begin
+ rx_reset <= 0;
+ tx_reset <= 0;
+ end
+
+// Modem Control Register
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ mcr <= 5'b0;
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_MC)
+ mcr <= wb_dat_i[4:0];
+
+// Scratch register
+// Line Control Register
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ scratch <= 0; // 8n1 setting
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_SR)
+ scratch <= wb_dat_i;
+
+// TX_FIFO or UART_DL1
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ begin
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL1] <= `PRESCALER_LOW_PRESET;
+`else
+ dl[`UART_DL1] <= 8'b0;
+`endif
+ tf_push <= 1'b0;
+ start_dlc <= 1'b0;
+ end
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_TR)
+ if (dlab)
+ begin
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL1] <= dl[`UART_DL1];
+`else
+ dl[`UART_DL1] <= wb_dat_i;
+`endif
+ start_dlc <= 1'b1; // enable DL counter
+ tf_push <= 1'b0;
+ end
+ else
+ begin
+ tf_push <= 1'b1;
+ start_dlc <= 1'b0;
+ end // else: !if(dlab)
+ else
+ begin
+ start_dlc <= 1'b0;
+ tf_push <= 1'b0;
+ end // else: !if(dlab)
+
+// Receiver FIFO trigger level selection logic (asynchronous mux)
+always @(fcr)
+ case (fcr[`UART_FC_TL])
+ 2'b00 : trigger_level = 1;
+ 2'b01 : trigger_level = 4;
+ 2'b10 : trigger_level = 8;
+ 2'b11 : trigger_level = 14;
+ endcase // case(fcr[`UART_FC_TL])
+
+//
+// STATUS REGISTERS //
+//
+
+// Modem Status Register
+reg [3:0] delayed_modem_signals;
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ begin
+ msr <= 0;
+ delayed_modem_signals[3:0] <= 0;
+ end
+ else begin
+ msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
+ msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
+ msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
+ delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
+ end
+end
+
+
+// Line Status Register
+
+// activation conditions
+assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
+assign lsr1 = rf_overrun; // Receiver overrun error
+assign lsr2 = rf_data_out[1]; // parity error bit
+assign lsr3 = rf_data_out[0]; // framing error bit
+assign lsr4 = rf_data_out[2]; // break error in the character
+assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
+assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
+assign lsr7 = rf_error_bit | rf_overrun;
+
+// lsr bit0 (receiver data available)
+reg lsr0_d;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr0_d <= 0;
+ else lsr0_d <= lsr0;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr0r <= 0;
+ else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 1'b0 : // deassert condition
+ lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
+
+// lsr bit 1 (receiver overrun)
+reg lsr1_d; // delayed
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr1_d <= 0;
+ else lsr1_d <= lsr1;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr1r <= 0;
+ else lsr1r <= lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
+
+// lsr bit 2 (parity error)
+reg lsr2_d; // delayed
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr2_d <= 0;
+ else lsr2_d <= lsr2;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr2r <= 0;
+ else lsr2r <= lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
+
+// lsr bit 3 (framing error)
+reg lsr3_d; // delayed
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr3_d <= 0;
+ else lsr3_d <= lsr3;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr3r <= 0;
+ else lsr3r <= lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
+
+// lsr bit 4 (break indicator)
+reg lsr4_d; // delayed
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr4_d <= 0;
+ else lsr4_d <= lsr4;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr4r <= 0;
+ else lsr4r <= lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d);
+
+// lsr bit 5 (transmitter fifo is empty)
+reg lsr5_d;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr5_d <= 1;
+ else lsr5_d <= lsr5;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr5r <= 1;
+ else lsr5r <= (fifo_write) ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d);
+
+// lsr bit 6 (transmitter empty indicator)
+reg lsr6_d;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr6_d <= 1;
+ else lsr6_d <= lsr6;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr6r <= 1;
+ else lsr6r <= (fifo_write) ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d);
+
+// lsr bit 7 (error in fifo)
+reg lsr7_d;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr7_d <= 0;
+ else lsr7_d <= lsr7;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr7r <= 0;
+ else lsr7r <= lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d);
+
+// Frequency divider
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ dlc <= 0;
+ else
+ if (start_dlc | ~ (|dlc))
+ dlc <= dl - 16'd1; // preset counter
+ else
+ dlc <= dlc - 16'd1; // decrement counter
+end
+
+// Enable signal generation logic
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ enable <= 1'b0;
+ else
+ if (|dl & ~(|dlc)) // dl>0 & dlc==0
+ enable <= 1'b1;
+ else
+ enable <= 1'b0;
+end
+
+// Delaying THRE status for one character cycle after a character is written to an empty fifo.
+always @(lcr)
+ case (lcr[3:0])
+ 4'b0000 : block_value = 95; // 6 bits
+ 4'b0100 : block_value = 103; // 6.5 bits
+ 4'b0001, 4'b1000 : block_value = 111; // 7 bits
+ 4'b1100 : block_value = 119; // 7.5 bits
+ 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
+ 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
+ 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
+ 4'b1111 : block_value = 175; // 11 bits
+ endcase // case(lcr[3:0])
+
+// Counting time of one character minus stop bit
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ block_cnt <= 8'd0;
+ else
+ if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
+ block_cnt <= SIM ? 8'd1 : block_value;
+ else
+ if (enable & block_cnt != 8'b0) // only work on enable times
+ block_cnt <= block_cnt - 8'd1; // decrement break counter
+end // always of break condition detection
+
+// Generating THRE status enable signal
+assign thre_set_en = ~(|block_cnt);
+
+
+//
+// INTERRUPT LOGIC
+//
+
+assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
+assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
+assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
+assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
+assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
+
+reg rls_int_d;
+reg thre_int_d;
+reg ms_int_d;
+reg ti_int_d;
+reg rda_int_d;
+
+// delay lines
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rls_int_d <= 0;
+ else rls_int_d <= rls_int;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rda_int_d <= 0;
+ else rda_int_d <= rda_int;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) thre_int_d <= 0;
+ else thre_int_d <= thre_int;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ms_int_d <= 0;
+ else ms_int_d <= ms_int;
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ti_int_d <= 0;
+ else ti_int_d <= ti_int;
+
+// rise detection signals
+
+wire rls_int_rise;
+wire thre_int_rise;
+wire ms_int_rise;
+wire ti_int_rise;
+wire rda_int_rise;
+
+assign rda_int_rise = rda_int & ~rda_int_d;
+assign rls_int_rise = rls_int & ~rls_int_d;
+assign thre_int_rise = thre_int & ~thre_int_d;
+assign ms_int_rise = ms_int & ~ms_int_d;
+assign ti_int_rise = ti_int & ~ti_int_d;
+
+// interrupt pending flags
+reg rls_int_pnd;
+reg rda_int_pnd;
+reg thre_int_pnd;
+reg ms_int_pnd;
+reg ti_int_pnd;
+
+// interrupt pending flags assignments
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rls_int_pnd <= 0;
+ else
+ rls_int_pnd <= lsr_mask ? 1'b0 : // reset condition
+ rls_int_rise ? 1'b1 : // latch condition
+ rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rda_int_pnd <= 0;
+ else
+ rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 1'b0 : // reset condition
+ rda_int_rise ? 1'b1 : // latch condition
+ rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) thre_int_pnd <= 0;
+ else
+ thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 1'b0 :
+ thre_int_rise ? 1'b1 :
+ thre_int_pnd && ier[`UART_IE_THRE];
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ms_int_pnd <= 0;
+ else
+ ms_int_pnd <= msr_read ? 1'b0 :
+ ms_int_rise ? 1'b1 :
+ ms_int_pnd && ier[`UART_IE_MS];
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ti_int_pnd <= 0;
+ else
+ ti_int_pnd <= fifo_read ? 1'b0 :
+ ti_int_rise ? 1'b1 :
+ ti_int_pnd && ier[`UART_IE_RDA];
+// end of pending flags
+
+// INT_O logic
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ int_o <= 1'b0;
+ else
+ int_o <=
+ rls_int_pnd ? ~lsr_mask :
+ rda_int_pnd ? 1'b1 :
+ ti_int_pnd ? ~fifo_read :
+ thre_int_pnd ? !(fifo_write & iir_read) :
+ ms_int_pnd ? ~msr_read :
+ 1'd0; // if no interrupt are pending
+end
+
+
+// Interrupt Identification register
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ iir <= 1;
+ else
+ if (rls_int_pnd) // interrupt is pending
+ begin
+ iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value
+ iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending)
+ end else // the sequence of conditions determines priority of interrupt identification
+ if (rda_int)
+ begin
+ iir[`UART_II_II] <= `UART_II_RDA;
+ iir[`UART_II_IP] <= 1'b0;
+ end
+ else if (ti_int_pnd)
+ begin
+ iir[`UART_II_II] <= `UART_II_TI;
+ iir[`UART_II_IP] <= 1'b0;
+ end
+ else if (thre_int_pnd)
+ begin
+ iir[`UART_II_II] <= `UART_II_THRE;
+ iir[`UART_II_IP] <= 1'b0;
+ end
+ else if (ms_int_pnd)
+ begin
+ iir[`UART_II_II] <= `UART_II_MS;
+ iir[`UART_II_IP] <= 1'b0;
+ end else // no interrupt is pending
+ begin
+ iir[`UART_II_II] <= 0;
+ iir[`UART_II_IP] <= 1'b1;
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/uart_rfifo.v b/verilog/rtl/uart_rfifo.v
new file mode 100644
index 0000000..59a29b9
--- /dev/null
+++ b/verilog/rtl/uart_rfifo.v
@@ -0,0 +1,316 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_rfifo.v (Modified from uart_fifo.v) ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core receiver FIFO ////
+//// ////
+//// To Do: ////
+//// Nothing. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2002/07/22 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2003/06/11 16:37:47 gorban
+// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
+//
+// Revision 1.2 2002/07/29 21:16:18 gorban
+// The uart_defines.v file is included again in sources.
+//
+// Revision 1.1 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.16 2001/12/20 13:25:46 mohor
+// rx push changed to be only one cycle wide.
+//
+// Revision 1.15 2001/12/18 09:01:07 mohor
+// Bug that was entered in the last update fixed (rx state machine).
+//
+// Revision 1.14 2001/12/17 14:46:48 mohor
+// overrun signal was moved to separate block because many sequential lsr
+// reads were preventing data from being written to rx fifo.
+// underrun signal was not used and was removed from the project.
+//
+// Revision 1.13 2001/11/26 21:38:54 gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.12 2001/11/08 14:54:23 mohor
+// Comments in Slovene language deleted, few small fixes for better work of
+// old tools. IRQs need to be fix.
+//
+// Revision 1.11 2001/11/07 17:51:52 gorban
+// Heavily rewritten interrupt and LSR subsystems.
+// Many bugs hopefully squashed.
+//
+// Revision 1.10 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.9 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.8 2001/08/24 08:48:10 mohor
+// FIFO was not cleared after the data was read bug fixed.
+//
+// Revision 1.7 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.3 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.3 2001/05/27 17:37:48 gorban
+// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
+//
+// Revision 1.2 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:12+02 jacob
+// Initial revision
+//
+//
+
+`include "uart_defines.v"
+
+module uart_rfifo (clk,
+ wb_rst_i, data_in, data_out,
+// Control signals
+ push, // push strobe, active high
+ pop, // pop strobe, active high
+// status signals
+ overrun,
+ count,
+ error_bit,
+ fifo_reset,
+ reset_status
+ );
+
+
+// FIFO parameters
+parameter fifo_width = `UART_FIFO_WIDTH;
+parameter fifo_depth = `UART_FIFO_DEPTH;
+parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
+parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
+
+input clk;
+input wb_rst_i;
+input push;
+input pop;
+input [fifo_width-1:0] data_in;
+input fifo_reset;
+input reset_status;
+
+output [fifo_width-1:0] data_out;
+output overrun;
+output [fifo_counter_w-1:0] count;
+output error_bit;
+
+wire [fifo_width-1:0] data_out;
+wire [7:0] data8_out;
+// flags FIFO
+reg [2:0] fifo[fifo_depth-1:0];
+
+// FIFO pointers
+reg [fifo_pointer_w-1:0] top;
+reg [fifo_pointer_w-1:0] bottom;
+
+reg [fifo_counter_w-1:0] count;
+reg overrun;
+
+wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1;
+
+raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
+ (.clk(clk),
+ .we(push),
+ .a(top),
+ .dpra(bottom),
+ .di(data_in[fifo_width-1:fifo_width-8]),
+ .dpo(data8_out)
+ );
+
+always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
+begin
+ if (wb_rst_i)
+ begin
+ top <= 0;
+ bottom <= 0;
+ count <= 0;
+ fifo[0] <= 0;
+ fifo[1] <= 0;
+ fifo[2] <= 0;
+ fifo[3] <= 0;
+ fifo[4] <= 0;
+ fifo[5] <= 0;
+ fifo[6] <= 0;
+ fifo[7] <= 0;
+ fifo[8] <= 0;
+ fifo[9] <= 0;
+ fifo[10] <= 0;
+ fifo[11] <= 0;
+ fifo[12] <= 0;
+ fifo[13] <= 0;
+ fifo[14] <= 0;
+ fifo[15] <= 0;
+ end
+ else
+ if (fifo_reset) begin
+ top <= 0;
+ bottom <= 0;
+ count <= 0;
+ fifo[0] <= 0;
+ fifo[1] <= 0;
+ fifo[2] <= 0;
+ fifo[3] <= 0;
+ fifo[4] <= 0;
+ fifo[5] <= 0;
+ fifo[6] <= 0;
+ fifo[7] <= 0;
+ fifo[8] <= 0;
+ fifo[9] <= 0;
+ fifo[10] <= 0;
+ fifo[11] <= 0;
+ fifo[12] <= 0;
+ fifo[13] <= 0;
+ fifo[14] <= 0;
+ fifo[15] <= 0;
+ end
+ else
+ begin
+ case ({push, pop})
+ 2'b10 : if (count<fifo_depth) // overrun condition
+ begin
+ top <= top_plus_1;
+ fifo[top] <= data_in[2:0];
+ count <= count + 5'd1;
+ end
+ 2'b01 : if(count>0)
+ begin
+ fifo[bottom] <= 0;
+ bottom <= bottom + 4'd1;
+ count <= count - 5'd1;
+ end
+ 2'b11 : begin
+ bottom <= bottom + 4'd1;
+ top <= top_plus_1;
+ fifo[top] <= data_in[2:0];
+ end
+ default: ;
+ endcase
+ end
+end // always
+
+always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
+begin
+ if (wb_rst_i)
+ overrun <= 1'b0;
+ else
+ if(fifo_reset | reset_status)
+ overrun <= 1'b0;
+ else
+ if(push & ~pop & (count==fifo_depth))
+ overrun <= 1'b1;
+end // always
+
+
+// please note though that data_out is only valid one clock after pop signal
+assign data_out = {data8_out,fifo[bottom]};
+
+// Additional logic for detection of error conditions (parity and framing) inside the FIFO
+// for the Line Status Register bit 7
+
+wire [2:0] word0 = fifo[0];
+wire [2:0] word1 = fifo[1];
+wire [2:0] word2 = fifo[2];
+wire [2:0] word3 = fifo[3];
+wire [2:0] word4 = fifo[4];
+wire [2:0] word5 = fifo[5];
+wire [2:0] word6 = fifo[6];
+wire [2:0] word7 = fifo[7];
+
+wire [2:0] word8 = fifo[8];
+wire [2:0] word9 = fifo[9];
+wire [2:0] word10 = fifo[10];
+wire [2:0] word11 = fifo[11];
+wire [2:0] word12 = fifo[12];
+wire [2:0] word13 = fifo[13];
+wire [2:0] word14 = fifo[14];
+wire [2:0] word15 = fifo[15];
+
+// a 1 is returned if any of the error bits in the fifo is 1
+assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
+ word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
+ word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
+ word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
+
+endmodule
diff --git a/verilog/rtl/uart_sync_flops.v b/verilog/rtl/uart_sync_flops.v
new file mode 100644
index 0000000..82a3a61
--- /dev/null
+++ b/verilog/rtl/uart_sync_flops.v
@@ -0,0 +1,117 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_sync_flops.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core receiver logic ////
+//// ////
+//// Known problems (limits): ////
+//// None known ////
+//// ////
+//// To Do: ////
+//// Thourough testing. ////
+//// ////
+//// Author(s): ////
+//// - Andrej Erzen (andreje@flextronics.si) ////
+//// - Tadej Markovic (tadejm@flextronics.si) ////
+//// ////
+//// Created: 2004/05/20 ////
+//// Last Updated: 2004/05/20 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module uart_sync_flops
+(
+ // internal signals
+ rst_i,
+ clk_i,
+ stage1_rst_i,
+ stage1_clk_en_i,
+ async_dat_i,
+ sync_dat_o
+);
+
+parameter width = 1;
+parameter init_value = 1'b0;
+
+input rst_i; // reset input
+input clk_i; // clock input
+input stage1_rst_i; // synchronous reset for stage 1 FF
+input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
+input [width-1:0] async_dat_i; // asynchronous data input
+output [width-1:0] sync_dat_o; // synchronous data output
+
+
+//
+// Interal signal declarations
+//
+
+reg [width-1:0] sync_dat_o;
+reg [width-1:0] flop_0;
+
+
+// first stage
+always @ (posedge clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ flop_0 <= {width{init_value}};
+ else
+ flop_0 <= async_dat_i;
+end
+
+// second stage
+always @ (posedge clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ sync_dat_o <= {width{init_value}};
+ else if (stage1_rst_i)
+ sync_dat_o <= {width{init_value}};
+ else if (stage1_clk_en_i)
+ sync_dat_o <= flop_0;
+end
+
+endmodule
diff --git a/verilog/rtl/uart_tfifo.v b/verilog/rtl/uart_tfifo.v
new file mode 100644
index 0000000..5b254cb
--- /dev/null
+++ b/verilog/rtl/uart_tfifo.v
@@ -0,0 +1,239 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_tfifo.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core transmitter FIFO ////
+//// ////
+//// To Do: ////
+//// Nothing. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2002/07/22 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.16 2001/12/20 13:25:46 mohor
+// rx push changed to be only one cycle wide.
+//
+// Revision 1.15 2001/12/18 09:01:07 mohor
+// Bug that was entered in the last update fixed (rx state machine).
+//
+// Revision 1.14 2001/12/17 14:46:48 mohor
+// overrun signal was moved to separate block because many sequential lsr
+// reads were preventing data from being written to rx fifo.
+// underrun signal was not used and was removed from the project.
+//
+// Revision 1.13 2001/11/26 21:38:54 gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.12 2001/11/08 14:54:23 mohor
+// Comments in Slovene language deleted, few small fixes for better work of
+// old tools. IRQs need to be fix.
+//
+// Revision 1.11 2001/11/07 17:51:52 gorban
+// Heavily rewritten interrupt and LSR subsystems.
+// Many bugs hopefully squashed.
+//
+// Revision 1.10 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.9 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.8 2001/08/24 08:48:10 mohor
+// FIFO was not cleared after the data was read bug fixed.
+//
+// Revision 1.7 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.3 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.3 2001/05/27 17:37:48 gorban
+// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
+//
+// Revision 1.2 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:12+02 jacob
+// Initial revision
+//
+//
+
+`include "uart_defines.v"
+
+module uart_tfifo (clk,
+ wb_rst_i, data_in, data_out,
+// Control signals
+ push, // push strobe, active high
+ pop, // pop strobe, active high
+// status signals
+ overrun,
+ count,
+ fifo_reset,
+ reset_status
+ );
+
+
+// FIFO parameters
+parameter fifo_width = `UART_FIFO_WIDTH;
+parameter fifo_depth = `UART_FIFO_DEPTH;
+parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
+parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
+
+input clk;
+input wb_rst_i;
+input push;
+input pop;
+input [fifo_width-1:0] data_in;
+input fifo_reset;
+input reset_status;
+
+output [fifo_width-1:0] data_out;
+output overrun;
+output [fifo_counter_w-1:0] count;
+
+wire [fifo_width-1:0] data_out;
+
+// FIFO pointers
+reg [fifo_pointer_w-1:0] top;
+reg [fifo_pointer_w-1:0] bottom;
+
+reg [fifo_counter_w-1:0] count;
+reg overrun;
+wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
+
+raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
+ (.clk(clk),
+ .we(push),
+ .a(top),
+ .dpra(bottom),
+ .di(data_in),
+ .dpo(data_out)
+ );
+
+
+always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
+begin
+ if (wb_rst_i)
+ begin
+ top <= 0;
+ bottom <= 0;
+ count <= 0;
+ end
+ else
+ if (fifo_reset) begin
+ top <= 0;
+ bottom <= 0;
+ count <= 0;
+ end
+ else
+ begin
+ case ({push, pop})
+ 2'b10 : if (count<fifo_depth) // overrun condition
+ begin
+ top <= top_plus_1;
+ count <= count + 5'd1;
+ end
+ 2'b01 : if(count>0)
+ begin
+ bottom <= bottom + 4'd1;
+ count <= count - 5'd1;
+ end
+ 2'b11 : begin
+ bottom <= bottom + 4'd1;
+ top <= top_plus_1;
+ end
+ default: ;
+ endcase
+ end
+end // always
+
+always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
+begin
+ if (wb_rst_i)
+ overrun <= 1'b0;
+ else
+ if(fifo_reset | reset_status)
+ overrun <= 1'b0;
+ else
+ if(push & (count==fifo_depth))
+ overrun <= 1'b1;
+end // always
+
+endmodule
diff --git a/verilog/rtl/uart_top.v b/verilog/rtl/uart_top.v
new file mode 100644
index 0000000..528f2f7
--- /dev/null
+++ b/verilog/rtl/uart_top.v
@@ -0,0 +1,261 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_top.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core top level. ////
+//// ////
+//// Known problems (limits): ////
+//// Note that transmitter and receiver instances are inside ////
+//// the uart_regs.v file. ////
+//// ////
+//// To Do: ////
+//// Nothing so far. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2001/05/17 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.18 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.17 2001/12/19 08:40:03 mohor
+// Warnings fixed (unused signals removed).
+//
+// Revision 1.16 2001/12/06 14:51:04 gorban
+// Bug in LSR[0] is fixed.
+// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
+//
+// Revision 1.15 2001/12/03 21:44:29 gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.14 2001/11/07 17:51:52 gorban
+// Heavily rewritten interrupt and LSR subsystems.
+// Many bugs hopefully squashed.
+//
+// Revision 1.13 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.12 2001/08/25 15:46:19 gorban
+// Modified port names again
+//
+// Revision 1.11 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.10 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.4 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.3 2001/05/21 19:12:02 gorban
+// Corrected some Linter messages.
+//
+// Revision 1.2 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:12+02 jacob
+// Initial revision
+//
+//
+
+`include "uart_defines.v"
+
+module uart_top (
+ wb_clk_i,
+
+ // Wishbone signals
+ wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
+ int_o, // interrupt request
+
+ // UART signals
+ // serial input/output
+ stx_pad_o, srx_pad_i,
+
+ // modem signals
+ rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
+`ifdef UART_HAS_BAUDRATE_OUTPUT
+ , baud_o
+`endif
+ );
+parameter SIM = 0;
+parameter debug = 0;
+
+input wb_clk_i;
+
+// WISHBONE interface
+input wb_rst_i;
+input [2:0] wb_adr_i;
+input [7:0] wb_dat_i;
+output [7:0] wb_dat_o;
+input wb_we_i;
+input wb_stb_i;
+input wb_cyc_i;
+input [3:0] wb_sel_i;
+output wb_ack_o;
+output int_o;
+
+// UART signals
+input srx_pad_i;
+output stx_pad_o;
+output rts_pad_o;
+input cts_pad_i;
+output dtr_pad_o;
+input dsr_pad_i;
+input ri_pad_i;
+input dcd_pad_i;
+
+// optional baudrate output
+`ifdef UART_HAS_BAUDRATE_OUTPUT
+output baud_o;
+`endif
+
+
+wire stx_pad_o;
+wire rts_pad_o;
+wire dtr_pad_o;
+
+wire [2:0] wb_adr_i;
+wire [7:0] wb_dat_i;
+wire [7:0] wb_dat_o;
+
+wire [7:0] wb_dat8_i; // 8-bit internal data input
+wire [7:0] wb_dat8_o; // 8-bit internal data output
+wire [31:0] wb_dat32_o; // debug interface 32-bit output
+wire [3:0] wb_sel_i; // WISHBONE select signal
+wire [2:0] wb_adr_int;
+wire we_o; // Write enable for registers
+wire re_o; // Read enable for registers
+//
+// MODULE INSTANCES
+//
+
+//// WISHBONE interface module
+uart_wb wb_interface(
+ .clk( wb_clk_i ),
+ .wb_rst_i( wb_rst_i ),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_dat8_i(wb_dat8_i),
+ .wb_dat8_o(wb_dat8_o),
+ .wb_dat32_o(32'b0),
+ .wb_sel_i(4'b0),
+ .wb_we_i( wb_we_i ),
+ .wb_stb_i( wb_stb_i ),
+ .wb_cyc_i( wb_cyc_i ),
+ .wb_ack_o( wb_ack_o ),
+ .wb_adr_i(wb_adr_i),
+ .wb_adr_int(wb_adr_int),
+ .we_o( we_o ),
+ .re_o(re_o)
+ );
+
+// Registers
+uart_regs #(.SIM (SIM)) regs(
+ .clk( wb_clk_i ),
+ .wb_rst_i( wb_rst_i ),
+ .wb_addr_i( wb_adr_int ),
+ .wb_dat_i( wb_dat8_i ),
+ .wb_dat_o( wb_dat8_o ),
+ .wb_we_i( we_o ),
+ .wb_re_i(re_o),
+ .modem_inputs( {cts_pad_i, dsr_pad_i,
+ ri_pad_i, dcd_pad_i} ),
+ .stx_pad_o( stx_pad_o ),
+ .srx_pad_i( srx_pad_i ),
+ .rts_pad_o( rts_pad_o ),
+ .dtr_pad_o( dtr_pad_o ),
+ .int_o( int_o )
+`ifdef UART_HAS_BAUDRATE_OUTPUT
+ , .baud_o(baud_o)
+`endif
+
+);
+
+initial
+begin
+ if(debug) begin
+ `ifdef UART_HAS_BAUDRATE_OUTPUT
+ $display("(%m) UART INFO: Has baudrate output\n");
+ `else
+ $display("(%m) UART INFO: Doesn't have baudrate output\n");
+ `endif
+ end
+end
+
+endmodule
+
+
diff --git a/verilog/rtl/uart_transmitter.v b/verilog/rtl/uart_transmitter.v
new file mode 100644
index 0000000..e2e8cf3
--- /dev/null
+++ b/verilog/rtl/uart_transmitter.v
@@ -0,0 +1,354 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_transmitter.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core transmitter logic ////
+//// ////
+//// Known problems (limits): ////
+//// None known ////
+//// ////
+//// To Do: ////
+//// Thourough testing. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2001/05/17 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.18 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.16 2002/01/08 11:29:40 mohor
+// tf_pop was too wide. Now it is only 1 clk cycle width.
+//
+// Revision 1.15 2001/12/17 14:46:48 mohor
+// overrun signal was moved to separate block because many sequential lsr
+// reads were preventing data from being written to rx fifo.
+// underrun signal was not used and was removed from the project.
+//
+// Revision 1.14 2001/12/03 21:44:29 gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.13 2001/11/08 14:54:23 mohor
+// Comments in Slovene language deleted, few small fixes for better work of
+// old tools. IRQs need to be fix.
+//
+// Revision 1.12 2001/11/07 17:51:52 gorban
+// Heavily rewritten interrupt and LSR subsystems.
+// Many bugs hopefully squashed.
+//
+// Revision 1.11 2001/10/29 17:00:46 gorban
+// fixed parity sending and tx_fifo resets over- and underrun
+//
+// Revision 1.10 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.9 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.8 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.6 2001/06/23 11:21:48 gorban
+// DL made 16-bit long. Fixed transmission/reception bugs.
+//
+// Revision 1.5 2001/06/02 14:28:14 gorban
+// Fixed receiver and transmitter. Major bug fixed.
+//
+// Revision 1.4 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.3 2001/05/27 17:37:49 gorban
+// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
+//
+// Revision 1.2 2001/05/21 19:12:02 gorban
+// Corrected some Linter messages.
+//
+// Revision 1.1 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:12+02 jacob
+// Initial revision
+//
+//
+
+`include "uart_defines.v"
+
+module uart_transmitter
+#(parameter SIM = 0)
+ (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
+
+input clk;
+input wb_rst_i;
+input [7:0] lcr;
+input tf_push;
+input [7:0] wb_dat_i;
+input enable;
+input tx_reset;
+input lsr_mask; //reset of fifo
+output stx_pad_o;
+output [2:0] tstate;
+output [`UART_FIFO_COUNTER_W-1:0] tf_count;
+
+reg [2:0] tstate;
+reg [4:0] counter;
+reg [2:0] bit_counter; // counts the bits to be sent
+reg [6:0] shift_out; // output shift register
+reg stx_o_tmp;
+reg parity_xor; // parity of the word
+reg tf_pop;
+reg bit_out;
+
+// TX FIFO instance
+//
+// Transmitter FIFO signals
+wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
+wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
+wire tf_push;
+wire tf_overrun;
+wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
+
+assign tf_data_in = wb_dat_i;
+
+uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO
+ .clk( clk ),
+ .wb_rst_i( wb_rst_i ),
+ .data_in( tf_data_in ),
+ .data_out( tf_data_out ),
+ .push( tf_push ),
+ .pop( tf_pop ),
+ .overrun( tf_overrun ),
+ .count( tf_count ),
+ .fifo_reset( tx_reset ),
+ .reset_status(lsr_mask)
+);
+
+// TRANSMITTER FINAL STATE MACHINE
+
+localparam s_idle = 3'd0;
+localparam s_send_start = 3'd1;
+localparam s_send_byte = 3'd2;
+localparam s_send_parity = 3'd3;
+localparam s_send_stop = 3'd4;
+localparam s_pop_byte = 3'd5;
+
+always @(posedge clk or posedge wb_rst_i)
+begin
+ if (wb_rst_i)
+ begin
+ tstate <= s_idle;
+ stx_o_tmp <= 1'b1;
+ counter <= 5'b0;
+ shift_out <= 7'b0;
+ bit_out <= 1'b0;
+ parity_xor <= 1'b0;
+ tf_pop <= 1'b0;
+ bit_counter <= 3'b0;
+ end
+ else
+ if (enable | SIM)
+ begin
+ case (tstate)
+ s_idle : if (~|tf_count) // if tf_count==0
+ begin
+ tstate <= s_idle;
+ stx_o_tmp <= 1'b1;
+ end
+ else
+ begin
+ tf_pop <= 1'b0;
+ stx_o_tmp <= 1'b1;
+ tstate <= s_pop_byte;
+ end
+ s_pop_byte : begin
+ tf_pop <= 1'b1;
+ case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
+ 2'b00 : begin
+ bit_counter <= 3'b100;
+ parity_xor <= ^tf_data_out[4:0];
+ end
+ 2'b01 : begin
+ bit_counter <= 3'b101;
+ parity_xor <= ^tf_data_out[5:0];
+ end
+ 2'b10 : begin
+ bit_counter <= 3'b110;
+ parity_xor <= ^tf_data_out[6:0];
+ end
+ 2'b11 : begin
+ bit_counter <= 3'b111;
+ parity_xor <= ^tf_data_out[7:0];
+ end
+ endcase
+ {shift_out[6:0], bit_out} <= tf_data_out;
+ tstate <= s_send_start;
+ end
+ s_send_start : begin
+ tf_pop <= 1'b0;
+ if (~|counter)
+ counter <= 5'b01111;
+ else
+ if (counter == 5'b00001)
+ begin
+ counter <= 0;
+ tstate <= s_send_byte;
+ end
+ else
+ counter <= counter - 5'd1;
+ stx_o_tmp <= 1'b0;
+ if (SIM) begin
+ tstate <= s_idle;
+ $write("%c", tf_data_out);
+ $fflush(32'h80000001);
+ end
+ end
+ s_send_byte : begin
+ if (~|counter)
+ counter <= 5'b01111;
+ else
+ if (counter == 5'b00001)
+ begin
+ if (bit_counter > 3'b0)
+ begin
+ bit_counter <= bit_counter - 3'd1;
+ {shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
+ tstate <= s_send_byte;
+ end
+ else // end of byte
+ if (~lcr[`UART_LC_PE])
+ begin
+ tstate <= s_send_stop;
+ end
+ else
+ begin
+ case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
+ 2'b00: bit_out <= ~parity_xor;
+ 2'b01: bit_out <= 1'b1;
+ 2'b10: bit_out <= parity_xor;
+ 2'b11: bit_out <= 1'b0;
+ endcase
+ tstate <= s_send_parity;
+ end
+ counter <= 0;
+ end
+ else
+ counter <= counter - 5'd1;
+ stx_o_tmp <= bit_out; // set output pin
+ end
+ s_send_parity : begin
+ if (~|counter)
+ counter <= 5'b01111;
+ else
+ if (counter == 5'b00001)
+ begin
+ counter <= 5'd0;
+ tstate <= s_send_stop;
+ end
+ else
+ counter <= counter - 5'd1;
+ stx_o_tmp <= bit_out;
+ end
+ s_send_stop : begin
+ if (~|counter)
+ begin
+ casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
+ 3'b0??: counter <= 5'b01101; // 1 stop bit ok igor
+ 3'b100: counter <= 5'b10101; // 1.5 stop bit
+ default: counter <= 5'b11101; // 2 stop bits
+ endcase
+ end
+ else
+ if (counter == 5'b00001)
+ begin
+ counter <= 0;
+ tstate <= s_idle;
+ end
+ else
+ counter <= counter - 5'd1;
+ stx_o_tmp <= 1'b1;
+ end
+
+ default : // should never get here
+ tstate <= s_idle;
+ endcase
+ end // end if enable
+ else
+ tf_pop <= 1'b0; // tf_pop must be 1 cycle width
+end // transmitter logic
+
+assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
+
+endmodule
diff --git a/verilog/rtl/uart_wb.v b/verilog/rtl/uart_wb.v
new file mode 100644
index 0000000..d537b70
--- /dev/null
+++ b/verilog/rtl/uart_wb.v
@@ -0,0 +1,258 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// uart_wb.v ////
+//// ////
+//// ////
+//// This file is part of the "UART 16550 compatible" project ////
+//// http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Documentation related to this project: ////
+//// - http://www.opencores.org/cores/uart16550/ ////
+//// ////
+//// Projects compatibility: ////
+//// - WISHBONE ////
+//// RS232 Protocol ////
+//// 16550D uart (mostly supported) ////
+//// ////
+//// Overview (main Features): ////
+//// UART core WISHBONE interface. ////
+//// ////
+//// Known problems (limits): ////
+//// Inserts one wait state on all transfers. ////
+//// Note affected signals and the way they are affected. ////
+//// ////
+//// To Do: ////
+//// Nothing. ////
+//// ////
+//// Author(s): ////
+//// - gorban@opencores.org ////
+//// - Jacob Gorban ////
+//// - Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// Created: 2001/05/12 ////
+//// Last Updated: 2001/05/17 ////
+//// (See log for the revision history) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.16 2002/07/29 21:16:18 gorban
+// The uart_defines.v file is included again in sources.
+//
+// Revision 1.15 2002/07/22 23:02:23 gorban
+// Bug Fixes:
+// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+// Problem reported by Kenny.Tung.
+// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+// * Made FIFO's as general inferrable memory where possible.
+// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+// * Added optional baudrate output (baud_o).
+// This is identical to BAUDOUT* signal on 16550 chip.
+// It outputs 16xbit_clock_rate - the divided clock.
+// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.12 2001/12/19 08:03:34 mohor
+// Warnings cleared.
+//
+// Revision 1.11 2001/12/06 14:51:04 gorban
+// Bug in LSR[0] is fixed.
+// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
+//
+// Revision 1.10 2001/12/03 21:44:29 gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.9 2001/10/20 09:58:40 gorban
+// Small synopsis fixes
+//
+// Revision 1.8 2001/08/24 21:01:12 mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.7 2001/08/23 16:05:05 mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.4 2001/05/31 20:08:01 gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.3 2001/05/21 19:12:01 gorban
+// Corrected some Linter messages.
+//
+// Revision 1.2 2001/05/17 18:34:18 gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0 2001-05-17 21:27:13+02 jacob
+// Initial revision
+//
+//
+
+// UART core WISHBONE interface
+//
+// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
+// Company: Flextronics Semiconductor
+//
+
+`include "uart_defines.v"
+
+module uart_wb (clk, wb_rst_i,
+ wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
+ wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
+ we_o, re_o // Write and read enable output for the core
+);
+
+input clk;
+
+// WISHBONE interface
+input wb_rst_i;
+input wb_we_i;
+input wb_stb_i;
+input wb_cyc_i;
+input [3:0] wb_sel_i;
+input [2:0] wb_adr_i; //WISHBONE address line
+
+input [7:0] wb_dat_i; //input WISHBONE bus
+output [7:0] wb_dat_o;
+reg [7:0] wb_dat_o;
+wire [7:0] wb_dat_i;
+reg [7:0] wb_dat_is;
+
+output [2:0] wb_adr_int; // internal signal for address bus
+input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
+output [7:0] wb_dat8_i;
+input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
+output wb_ack_o;
+output we_o;
+output re_o;
+
+wire we_o;
+reg wb_ack_o;
+reg [7:0] wb_dat8_i;
+wire [7:0] wb_dat8_o;
+wire [2:0] wb_adr_int; // internal signal for address bus
+reg [2:0] wb_adr_is;
+reg wb_we_is;
+reg wb_cyc_is;
+reg wb_stb_is;
+wire [3:0] wb_sel_i;
+reg wre ;// timing control signal for write or read enable
+
+// wb_ack_o FSM
+reg [1:0] wbstate;
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) begin
+ wb_ack_o <= 1'b0;
+ wbstate <= 0;
+ wre <= 1'b1;
+ end else
+ case (wbstate)
+ 0: begin
+ if (wb_stb_is & wb_cyc_is) begin
+ wre <= 0;
+ wbstate <= 1;
+ wb_ack_o <= 1;
+ end else begin
+ wre <= 1;
+ wb_ack_o <= 0;
+ end
+ end
+ 1: begin
+ wb_ack_o <= 0;
+ wbstate <= 2;
+ wre <= 0;
+ end
+ 2: begin
+ wb_ack_o <= 0;
+ wbstate <= 3;
+ wre <= 0;
+ end
+ 3: begin
+ wb_ack_o <= 0;
+ wbstate <= 0;
+ wre <= 1;
+ end
+ endcase
+
+assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
+assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
+
+// Sample input signals
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) begin
+ wb_adr_is <= 0;
+ wb_we_is <= 0;
+ wb_cyc_is <= 0;
+ wb_stb_is <= 0;
+ wb_dat_is <= 0;
+ end else begin
+ wb_adr_is <= wb_adr_i;
+ wb_we_is <= wb_we_i;
+ wb_cyc_is <= wb_cyc_i;
+ wb_stb_is <= wb_stb_i;
+ wb_dat_is <= wb_dat_i;
+ end
+
+always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ wb_dat_o <= 0;
+ else
+ wb_dat_o <= wb_dat8_o;
+
+always @(wb_dat_is)
+ wb_dat8_i = wb_dat_is;
+
+assign wb_adr_int = wb_adr_is;
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
deleted file mode 100644
index 44e8eda..0000000
--- a/verilog/rtl/user_proj_example.v
+++ /dev/null
@@ -1,172 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_proj_example
- *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only). The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project. The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
- *
- *-------------------------------------------------------------
- */
-
-module user_proj_example #(
- parameter BITS = 32
-)(
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oen,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb
-);
- wire clk;
- wire rst;
-
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
-
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
- );
-
-endmodule
-
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end
- end
- end
-
- genvar i;
- generate
- for(i=0; i<BITS; i=i+1) begin
- always @(posedge clk) begin
- if (la_write[i]) count[i] <= la_input[i];
- end
- end
- endgenerate
-
-endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 47d92f4..e114075 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -19,12 +19,7 @@
*
* user_project_wrapper
*
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper. The
- * example should be removed and replaced with the actual
- * user project.
+ * This connects microwatt up to caravel.
*
*-------------------------------------------------------------
*/
@@ -46,6 +41,7 @@
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
+
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
@@ -74,51 +70,170 @@
// Independent clock (on independent integer divider)
input user_clock2
);
+ wire clk;
+ wire rst; // active high
- /*--------------------------------------*/
- /* User project is instantiated here */
- /*--------------------------------------*/
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
- user_proj_example mprj (
+ // microwatt signals
+ wire ext_clk;
+ reg ext_rst_n; // active low
+ wire alt_reset;
+ wire jtag_tck;
+ wire jtag_tdi;
+ wire jtag_tdo;
+ wire jtag_tms;
+ wire jtag_trst;
+ wire spi_flash_clk;
+ wire spi_flash_cs_n;
+ wire [3:0] spi_flash_i;
+ wire [3:0] spi_flash_o;
+ wire [3:0] spi_flash_oe;
+ wire uart0_rxd;
+ wire uart0_txd;
+ wire uart1_rxd; // not hooked up
+ wire uart1_txd; // not hooked up
+ wire [31:0] logic_analyzeri;
+ wire [31:0] logic_analyzero;
+
+ wire oib_clk;
+ wire [7:0] ob_data;
+ wire ob_pty;
+ wire [7:0] ib_data;
+ wire ib_pty;
+
+ assign uart1_rxd = 1; // not hooked up
+
+ // Management engine wishbone slave is unused
+ assign wbs_ack_o = 1'b0;
+
+ assign clk = wb_clk_i;
+
+ // LA probe 65 controls microwatt reset
+ assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+
+ // LA probe 66 controls the reset address (RAM or FLASH)
+ assign alt_reset = (~la_oen[66]) ? la_data_in[66]: 1'b0;
+
+ // microwatt signals
+ assign ext_clk = clk;
+
+ reg [11:0] reset_counter;
+ always @(posedge clk) begin
+ if (rst) begin
+ ext_rst_n <= 1'b0;
+ reset_counter <= 0;
+ end else if (reset_counter < 4095) begin
+ ext_rst_n <= 1'b0;
+ reset_counter <= reset_counter + 1'b1;
+ end else begin
+ ext_rst_n <= 1'b1;
+ end
+ end
+
+ // UART pins 5-6 shared with management soc
+ assign uart0_rxd = io_in[5];
+ assign io_out[5] = 0; // don't care
+ assign io_oeb[5] = 1; // input
+
+ // assign unused = io_in[6];
+ assign io_out[6] = uart0_txd;
+ assign io_oeb[6] = rst;
+
+ // 7 unused
+
+ // SPI pins 8-13
+ // assign unused = io_in[8];
+ assign io_out[8] = spi_flash_cs_n; //(polarity??)
+ assign io_oeb[8] = rst; // output
+
+ // assign unused = io_in[9];
+ assign io_out[9] = spi_flash_clk;
+ assign io_oeb[9] = rst; // output
+
+ // Bi direction SPI pins
+ assign io_out[10] = spi_flash_o[0];
+ assign io_out[11] = spi_flash_o[1];
+ assign io_out[12] = spi_flash_o[2];
+ assign io_out[13] = spi_flash_o[3];
+
+ assign io_oeb[10] = ~spi_flash_oe[0];
+ assign io_oeb[11] = ~spi_flash_oe[1];
+ assign io_oeb[12] = ~spi_flash_oe[2];
+ assign io_oeb[13] = ~spi_flash_oe[3];
+
+ assign spi_flash_i[0] = io_in[10];
+ assign spi_flash_i[1] = io_in[11];
+ assign spi_flash_i[2] = io_in[12];
+ assign spi_flash_i[3] = io_in[13];
+
+ // JTAG pins 14-17
+ // assign unused = io_in[14];
+ assign io_out[14] = jtag_tdo;
+ assign io_oeb[14] = rst; // output
+
+ assign jtag_tms = io_in[15];
+ assign io_out[15] = 0; // don't care
+ assign io_oeb[15] = 1; // input
+
+ assign jtag_tck = io_in[16];
+ assign io_out[16] = 0; // don't care
+ assign io_oeb[16] = 1; // input
+
+ assign jtag_tdi = io_in[17];
+ assign io_out[17] = 0; // don't care
+ assign io_oeb[17] = 1; // input
+
+ assign jtag_trst = rst;
+
+ // external bus pins 18-36 -> 18-27 outputs, 28-36 inputs
+ //assign = in[18:27] = rst; don't care
+ assign io_oeb[27:18] = {10{rst}}; // outputs
+ assign io_out[18] = oib_clk;
+ assign io_out[26:19] = ob_data;
+ assign io_out[27] = ob_pty;
+
+ assign io_out[36:28] = 0; // don't care
+ assign io_oeb[36:28] = {9{1'b1}}; // input
+ assign ib_data = io_in[35:28];
+ assign ib_pty = io_in[36];
+
+ // 37 unused
+
+ assign la_data_out[31:0] = logic_analyzero[31:0];
+ assign logic_analyzeri[31:0] = la_data_in[63:32];
+
+ microwatt microwatt_0(
`ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
.vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
`endif
-
- // MGMT core clock and reset
-
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oen (la_oen),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb)
- );
+ .ext_clk(ext_clk),
+ .ext_rst(ext_rst_n),
+ .alt_reset(alt_reset),
+ .uart0_rxd(uart0_rxd),
+ .uart1_rxd(uart1_rxd),
+ .jtag_tck(jtag_tck),
+ .jtag_tdi(jtag_tdi),
+ .jtag_tms(jtag_tms),
+ .jtag_trst(jtag_trst),
+ .uart0_txd(uart0_txd),
+ .uart1_txd(uart1_txd),
+ .spi_flash_cs_n(spi_flash_cs_n),
+ .spi_flash_clk(spi_flash_clk),
+ .spi_flash_sdat_o(spi_flash_o),
+ .spi_flash_sdat_i(spi_flash_i),
+ .spi_flash_sdat_oe(spi_flash_oe),
+ .jtag_tdo(jtag_tdo),
+ .oib_clk(oib_clk),
+ .ob_data(ob_data),
+ .ob_pty(ob_pty),
+ .ib_data(ib_data),
+ .ib_pty(ib_pty),
+ .gpio_in(logic_analyzeri),
+ .gpio_out(logic_analyzero));
endmodule // user_project_wrapper
`default_nettype wire
