verilog/rtl/icache.v

/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */

module plru_1(clk, rst, acc, acc_en, lru);
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  input acc;
  input acc_en;
  input clk;
  output lru;
  input rst;
  reg [1:0] tree;
  assign _0_ = ~ acc;
  assign _1_ = acc_en ? _0_ : tree[1];
  assign _2_ = rst ? 1'h0 : tree[0];
  assign _3_ = rst ? 1'h0 : _1_;
  always @(posedge clk)
    tree <= { _3_, _2_ };
  assign lru = tree[1];
endmodule

module cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
  wire [127:0] _00_;
  wire [7:0] _01_;
  wire [127:0] _02_;
  wire [7:0] _03_;
  wire [127:0] _04_;
  wire [7:0] _05_;
  wire [127:0] _06_;
  wire [7:0] _07_;
  wire [127:0] _08_;
  wire [7:0] _09_;
  wire [127:0] _10_;
  wire [7:0] _11_;
  wire [127:0] _12_;
  wire [7:0] _13_;
  wire [127:0] _14_;
  wire [7:0] _15_;
  input clk;
  input [3:0] rd_addr;
  output [63:0] rd_data;
  input rd_en;
  input [3:0] wr_addr;
  input [63:0] wr_data;
  input [7:0] wr_sel;
  reg [7:0] \$mem$\20409  [15:0];
  reg [7:0] \$mem$\20410  [15:0];
  reg [7:0] \$mem$\20411  [15:0];
  reg [7:0] \$mem$\20412  [15:0];
  reg [7:0] \$mem$\20413  [15:0];
  reg [7:0] \$mem$\20414  [15:0];
  reg [7:0] \$mem$\20415  [15:0];
  reg [7:0] \$mem$\20416  [15:0];
  (* ram_style = "block" *)
  reg [7:0] \20409  [15:0];
  reg [7:0] _16_;
  always @(posedge clk) begin
    if (rd_en) _16_ <= \20409 [rd_addr];
    if (wr_sel[0]) \20409 [wr_addr] <= wr_data[7:0];
  end
  assign _01_ = _16_;
  (* ram_style = "block" *)
  reg [7:0] \20410  [15:0];
  reg [7:0] _17_;
  always @(posedge clk) begin
    if (rd_en) _17_ <= \20410 [rd_addr];
    if (wr_sel[1]) \20410 [wr_addr] <= wr_data[15:8];
  end
  assign _03_ = _17_;
  (* ram_style = "block" *)
  reg [7:0] \20411  [15:0];
  reg [7:0] _18_;
  always @(posedge clk) begin
    if (rd_en) _18_ <= \20411 [rd_addr];
    if (wr_sel[2]) \20411 [wr_addr] <= wr_data[23:16];
  end
  assign _05_ = _18_;
  (* ram_style = "block" *)
  reg [7:0] \20412  [15:0];
  reg [7:0] _19_;
  always @(posedge clk) begin
    if (rd_en) _19_ <= \20412 [rd_addr];
    if (wr_sel[3]) \20412 [wr_addr] <= wr_data[31:24];
  end
  assign _07_ = _19_;
  (* ram_style = "block" *)
  reg [7:0] \20413  [15:0];
  reg [7:0] _20_;
  always @(posedge clk) begin
    if (rd_en) _20_ <= \20413 [rd_addr];
    if (wr_sel[4]) \20413 [wr_addr] <= wr_data[39:32];
  end
  assign _09_ = _20_;
  (* ram_style = "block" *)
  reg [7:0] \20414  [15:0];
  reg [7:0] _21_;
  always @(posedge clk) begin
    if (rd_en) _21_ <= \20414 [rd_addr];
    if (wr_sel[5]) \20414 [wr_addr] <= wr_data[47:40];
  end
  assign _11_ = _21_;
  (* ram_style = "block" *)
  reg [7:0] \20415  [15:0];
  reg [7:0] _22_;
  always @(posedge clk) begin
    if (rd_en) _22_ <= \20415 [rd_addr];
    if (wr_sel[6]) \20415 [wr_addr] <= wr_data[55:48];
  end
  assign _13_ = _22_;
  (* ram_style = "block" *)
  reg [7:0] \20416  [15:0];
  reg [7:0] _23_;
  always @(posedge clk) begin
    if (rd_en) _23_ <= \20416 [rd_addr];
    if (wr_sel[7]) \20416 [wr_addr] <= wr_data[63:56];
  end
  assign _15_ = _23_;
  assign rd_data = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
endmodule

module icache(
`ifdef USE_POWER_PINS
	vccd1, vssd1,
`endif
	clk, rst, i_in, m_in, stall_in, flush_in, inval_in, wishbone_in, i_out, stall_out, wishbone_out);
`ifdef USE_POWER_PINS
  inout vccd1;
  inout vssd1;
`endif

  wire _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire [1:0] _010_;
  wire _011_;
  wire [1:0] _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire [1:0] _016_;
  wire [1:0] _017_;
  wire _018_;
  wire _019_;
  wire [1:0] _020_;
  wire [1:0] _021_;
  wire [3:0] _022_;
  wire [3:0] _023_;
  wire [3:0] _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire _033_;
  wire _034_;
  wire _035_;
  wire _036_;
  wire _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  wire [2:0] _041_;
  wire _042_;
  wire _043_;
  wire _044_;
  wire _045_;
  wire _046_;
  wire _047_;
  wire _048_;
  wire _049_;
  wire _050_;
  wire _051_;
  wire _052_;
  wire _053_;
  wire _054_;
  wire [2:0] _055_;
  wire _056_;
  wire _057_;
  wire _058_;
  wire _059_;
  wire _060_;
  wire _061_;
  wire _062_;
  wire _063_;
  wire _064_;
  wire _065_;
  wire _066_;
  wire _067_;
  wire _068_;
  wire _069_;
  wire _070_;
  wire _071_;
  wire _072_;
  wire _073_;
  wire _074_;
  wire _075_;
  wire _076_;
  wire _077_;
  wire _078_;
  wire _079_;
  wire _080_;
  wire _081_;
  wire [64:0] _082_;
  reg [66:0] _083_;
  wire [3:0] _084_;
  wire _085_;
  wire [2:0] _086_;
  wire [33:0] _087_;
  wire [1:0] _088_;
  wire [58:0] _089_;
  wire _090_;
  wire _091_;
  wire _092_;
  wire _093_;
  wire _094_;
  wire _095_;
  wire [199:0] _096_;
  wire _097_;
  wire _098_;
  wire _099_;
  wire [199:0] _100_;
  wire [199:0] _101_;
  wire [3:0] _102_;
  wire [1:0] _103_;
  wire _104_;
  wire _105_;
  wire _106_;
  wire _107_;
  wire _108_;
  wire _109_;
  wire _110_;
  wire _111_;
  wire [2:0] _112_;
  wire [31:0] _113_;
  wire _114_;
  wire _115_;
  wire [2:0] _116_;
  wire _117_;
  wire _118_;
  wire _119_;
  wire _120_;
  wire _121_;
  wire [3:0] _122_;
  wire [1:0] _123_;
  wire _124_;
  wire [2:0] _125_;
  wire _126_;
  wire _127_;
  wire _128_;
  wire [3:0] _129_;
  wire [7:0] _130_;
  wire _131_;
  wire _132_;
  wire _133_;
  wire [199:0] _134_;
  wire [3:0] _135_;
  wire [1:0] _136_;
  wire [31:0] _137_;
  wire _138_;
  wire _139_;
  wire _140_;
  wire _141_;
  wire [3:0] _142_;
  wire [53:0] _143_;
  wire _144_;
  wire _145_;
  wire _146_;
  wire _147_;
  wire _148_;
  wire _149_;
  wire _150_;
  wire _151_;
  wire [199:0] _152_;
  wire [3:0] _153_;
  wire [33:0] _154_;
  wire [71:0] _155_;
  wire [1:0] _156_;
  wire _157_;
  wire [67:0] _158_;
  wire _159_;
  wire _160_;
  wire _161_;
  wire _162_;
  wire _163_;
  wire _164_;
  wire _165_;
  wire _166_;
  reg [177:0] _167_;
  wire [255:0] _168_;
  wire [63:0] _169_;
  wire [199:0] _170_;
  wire [49:0] _171_;
  wire _172_;
  wire _173_;
  wire _174_;
  wire _175_;
  wire _176_;
  wire _177_;
  wire _178_;
  wire _179_;
  wire _180_;
  wire _181_;
  wire _182_;
  wire _183_;
  wire _184_;
  wire _185_;
  wire _186_;
  wire _187_;
  wire _188_;
  wire _189_;
  wire _190_;
  wire _191_;
  wire _192_;
  wire _193_;
  wire _194_;
  wire _195_;
  wire _196_;
  wire [99:0] _197_;
  wire _198_;
  wire _199_;
  wire _200_;
  wire _201_;
  wire [99:0] _202_;
  wire _203_;
  wire [63:0] _204_;
  wire [31:0] _205_;
  wire _206_;
  wire _207_;
  wire _208_;
  wire _209_;
  wire _210_;
  wire _211_;
  wire _212_;
  wire _213_;
  wire _214_;
  wire _215_;
  wire [99:0] _216_;
  wire _217_;
  wire [99:0] _218_;
  wire [99:0] _219_;
  wire [99:0] _220_;
  wire _221_;
  wire [99:0] _222_;
  wire [99:0] _223_;
  wire _224_;
  wire _225_;
  wire _226_;
  wire _227_;
  wire _228_;
  wire _229_;
  wire _230_;
  wire _231_;
  wire _232_;
  wire _233_;
  wire _234_;
  wire _235_;
  wire _236_;
  wire _237_;
  wire _238_;
  wire _239_;
  wire _240_;
  wire _241_;
  wire _242_;
  wire _243_;
  wire _244_;
  wire _245_;
  wire _246_;
  wire _247_;
  wire _248_;
  wire _249_;
  wire _250_;
  wire _251_;
  wire _252_;
  wire _253_;
  wire _254_;
  wire _255_;
  wire _256_;
  wire _257_;
  wire _258_;
  wire _259_;
  wire _260_;
  wire _261_;
  wire _262_;
  wire _263_;
  wire _264_;
  wire _265_;
  wire _266_;
  wire access_ok;
  reg [199:0] cache_tags;
  reg [3:0] cache_valids;
  input clk;
  wire eaa_priv;
  input flush_in;
  input [69:0] i_in;
  output [98:0] i_out;
  input inval_in;
  reg [3:0] itlb_valids;
  input [130:0] m_in;
  wire \maybe_plrus.plrus:0.plru_acc_en ;
  wire \maybe_plrus.plrus:0.plru_out ;
  wire \maybe_plrus.plrus:1.plru_acc_en ;
  wire \maybe_plrus.plrus:1.plru_out ;
  wire priv_fault;
  wire ra_valid;
  wire \rams:0.do_read ;
  wire \rams:0.do_write ;
  wire [63:0] \rams:0.dout ;
  wire [63:0] \rams:0.wr_dat ;
  wire \rams:1.do_read ;
  wire \rams:1.do_write ;
  wire [63:0] \rams:1.dout ;
  wire [63:0] \rams:1.wr_dat ;
  wire [55:0] real_addr;
  wire replace_way;
  wire req_hit_way;
  wire req_is_hit;
  wire req_is_miss;
  input rst;
  input stall_in;
  output stall_out;
  wire [1:0] tlb_req_index;
  wire use_previous;
  input [65:0] wishbone_in;
  output [106:0] wishbone_out;
  reg [63:0] \$mem$\8207  [3:0];
  reg [49:0] \$mem$\8210  [3:0];
  (* ram_style = "distributed" *)
  reg [63:0] \8207  [3:0];
  always @(posedge clk) begin
    if (_032_) \8207 [_017_] <= m_in[130:67];
  end
  assign _169_ = \8207 [tlb_req_index];
  (* ram_style = "distributed" *)
  reg [49:0] \8210  [3:0];
  always @(posedge clk) begin
    if (_028_) \8210 [_017_] <= m_in[66:17];
  end
  assign _171_ = \8210 [tlb_req_index];
  assign _257_ = _012_[0] ? itlb_valids[1] : itlb_valids[0];
  assign _258_ = _041_[0] ? _167_[170] : _167_[169];
  assign _259_ = _041_[0] ? _167_[174] : _167_[173];
  assign _260_ = _055_[0] ? _167_[170] : _167_[169];
  assign _261_ = _055_[0] ? _167_[174] : _167_[173];
  assign _262_ = _012_[0] ? itlb_valids[3] : itlb_valids[2];
  assign _263_ = _041_[0] ? _167_[172] : _167_[171];
  assign _264_ = _041_[0] ? _167_[176] : _167_[175];
  assign _265_ = _055_[0] ? _167_[172] : _167_[171];
  assign _266_ = _055_[0] ? _167_[176] : _167_[175];
  assign _172_ = _012_[1] ? _262_ : _257_;
  assign _194_ = _041_[1] ? _263_ : _258_;
  assign _195_ = _041_[1] ? _264_ : _259_;
  assign _199_ = _055_[1] ? _265_ : _260_;
  assign _200_ = _055_[1] ? _266_ : _261_;
  assign _000_ = ~ _167_[164];
  assign \rams:0.wr_dat  = _000_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
  assign _001_ = stall_in | use_previous;
  assign \rams:0.do_read  = ~ _001_;
  assign _002_ = { 31'h00000000, replace_way } == 32'd0;
  assign _003_ = wishbone_in[64] & _002_;
  assign \rams:0.do_write  = _003_ ? 1'h1 : 1'h0;
  assign _004_ = ~ _167_[164];
  assign \rams:1.wr_dat  = _004_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
  assign _005_ = stall_in | use_previous;
  assign \rams:1.do_read  = ~ _005_;
  assign _006_ = { 31'h00000000, replace_way } == 32'd1;
  assign _007_ = wishbone_in[64] & _006_;
  assign \rams:1.do_write  = _007_ ? 1'h1 : 1'h0;
  assign _008_ = { 31'h00000000, _083_[7] } == 32'd0;
  assign \maybe_plrus.plrus:0.plru_acc_en  = _008_ ? _083_[66] : 1'h0;
  assign _009_ = { 31'h00000000, _083_[7] } == 32'd1;
  assign \maybe_plrus.plrus:1.plru_acc_en  = _009_ ? _083_[66] : 1'h0;
  assign _010_ = i_in[19:18] ^ i_in[21:20];
  assign tlb_req_index = _010_ ^ i_in[23:22];
  assign _011_ = _171_ == i_in[69:20];
  assign _012_ = 2'h3 - tlb_req_index;
  assign _013_ = _011_ ? _172_ : 1'h0;
  assign eaa_priv = i_in[1] ? _169_[3] : 1'h1;
  assign real_addr = i_in[1] ? { _169_[55:12], i_in[17:6] } : i_in[61:6];
  assign ra_valid = i_in[1] ? _013_ : 1'h1;
  assign _014_ = ~ i_in[2];
  assign priv_fault = eaa_priv & _014_;
  assign _015_ = ~ priv_fault;
  assign access_ok = ra_valid & _015_;
  assign _016_ = m_in[16:15] ^ m_in[18:17];
  assign _017_ = _016_ ^ m_in[20:19];
  assign _018_ = m_in[1] & m_in[2];
  assign _019_ = rst | _018_;
  assign _020_ = 2'h3 - _017_;
  assign _021_ = 2'h3 - _017_;
  assign _022_ = m_in[0] ? { _192_, _191_, _190_, _189_ } : itlb_valids;
  assign _023_ = m_in[1] ? { _182_, _181_, _180_, _179_ } : _022_;
  assign _024_ = _019_ ? 4'h0 : _023_;
  always @(posedge clk)
    itlb_valids <= _024_;
  assign _025_ = ~ _019_;
  assign _026_ = ~ m_in[1];
  assign _027_ = _025_ & _026_;
  assign _028_ = _027_ & m_in[0];
  assign _029_ = ~ _019_;
  assign _030_ = ~ m_in[1];
  assign _031_ = _029_ & _030_;
  assign _032_ = _031_ & m_in[0];
  assign _033_ = i_in[8] != 1'h0;
  assign _034_ = i_in[5] & _083_[66];
  assign use_previous = _033_ ? _034_ : 1'h0;
  assign _035_ = 1'h1 - i_in[12];
  assign _036_ = _167_[1:0] == 2'h2;
  assign _037_ = { 31'h00000000, i_in[12] } == { 31'h00000000, _167_[110] };
  assign _038_ = _036_ & _037_;
  assign _039_ = 32'd0 == { 31'h00000000, _167_[109] };
  assign _040_ = _038_ & _039_;
  assign _041_ = 3'h7 - i_in[11:9];
  assign _042_ = _040_ & _196_;
  assign _043_ = _193_ | _042_;
  assign _044_ = i_in[0] & _043_;
  assign _045_ = 1'h1 - i_in[12];
  assign _046_ = _197_[49:0] == { i_in[3], real_addr[55:7] };
  assign _047_ = _046_ ? 1'h1 : 1'h0;
  assign _048_ = _044_ ? _047_ : 1'h0;
  assign _049_ = 1'h1 - i_in[12];
  assign _050_ = _167_[1:0] == 2'h2;
  assign _051_ = { 31'h00000000, i_in[12] } == { 31'h00000000, _167_[110] };
  assign _052_ = _050_ & _051_;
  assign _053_ = 32'd1 == { 31'h00000000, _167_[109] };
  assign _054_ = _052_ & _053_;
  assign _055_ = 3'h7 - i_in[11:9];
  assign _056_ = _054_ & _201_;
  assign _057_ = _198_ | _056_;
  assign _058_ = i_in[0] & _057_;
  assign _059_ = 1'h1 - i_in[12];
  assign _060_ = _202_[99:50] == { i_in[3], real_addr[55:7] };
  assign _061_ = _063_ ? 1'h1 : _048_;
  assign _062_ = _060_ ? 1'h1 : 1'h0;
  assign _063_ = _058_ & _060_;
  assign req_hit_way = _058_ ? _062_ : 1'h0;
  assign _064_ = i_in[0] & access_ok;
  assign _065_ = ~ flush_in;
  assign _066_ = _064_ & _065_;
  assign _067_ = ~ rst;
  assign _068_ = _066_ & _067_;
  assign _069_ = ~ _061_;
  assign req_is_hit = _068_ ? _061_ : 1'h0;
  assign req_is_miss = _068_ ? _069_ : 1'h0;
  assign _070_ = _167_[1:0] == 2'h1;
  assign _071_ = 1'h1 - _167_[110];
  assign replace_way = _070_ ? _203_ : _167_[109];
  assign _072_ = 1'h1 - _083_[0];
  assign _073_ = _061_ & access_ok;
  assign _074_ = ~ _073_;
  assign _075_ = stall_in | use_previous;
  assign _076_ = rst | flush_in;
  assign _077_ = _076_ ? 1'h0 : _083_[66];
  assign _078_ = req_is_hit ? req_hit_way : _083_[0];
  assign _079_ = _075_ ? _083_[0] : _078_;
  assign _080_ = _075_ ? _077_ : req_is_hit;
  assign _081_ = ~ stall_in;
  assign _082_ = _081_ ? { i_in[4], i_in[69:6] } : _083_[65:1];
  always @(posedge clk)
    _083_ <= { _080_, _082_, _079_ };
  assign _084_ = inval_in ? 4'h0 : cache_valids;
  assign _085_ = inval_in ? 1'h0 : _167_[165];
  assign _086_ = real_addr[5:3] - 3'h1;
  assign _087_ = req_is_miss ? { real_addr[31:3], 5'h01 } : _167_[33:0];
  assign _088_ = req_is_miss ? 2'h3 : _167_[107:106];
  assign _089_ = req_is_miss ? { _086_, 1'h1, i_in[3], real_addr[55:3], i_in[12] } : { _167_[168:166], _085_, _167_[164:110] };
  assign _090_ = _167_[1:0] == 2'h0;
  assign _091_ = _167_[1:0] == 2'h1;
  assign _092_ = 1'h1 - i_in[12];
  assign _093_ = 32'd0 == { 31'h00000000, replace_way };
  assign _094_ = 1'h1 - _167_[110];
  assign _095_ = 1'h1 - _167_[110];
  assign _096_ = _093_ ? { _219_, _218_ } : cache_tags;
  assign _097_ = 32'd1 == { 31'h00000000, replace_way };
  assign _098_ = 1'h1 - _167_[110];
  assign _099_ = 1'h1 - _167_[110];
  assign _100_ = _097_ ? { _223_, _222_ } : _096_;
  assign _101_ = _091_ ? _100_ : cache_tags;
  assign _102_ = _091_ ? { _215_, _214_, _213_, _212_ } : _084_;
  assign _103_ = _091_ ? 2'h2 : _167_[1:0];
  assign _104_ = _091_ ? replace_way : _167_[109];
  assign _105_ = ~ _167_[107];
  assign _106_ = ~ wishbone_in[65];
  assign _107_ = ~ _105_;
  assign _108_ = _106_ & _107_;
  assign _109_ = _167_[7:5] == _167_[168:166];
  assign _110_ = _114_ ? 1'h0 : _167_[107];
  assign _111_ = _115_ ? 1'h1 : _105_;
  assign _112_ = _167_[7:5] + 3'h1;
  assign _113_ = _108_ ? { _167_[33:8], _112_, _167_[4:2] } : _167_[33:2];
  assign _114_ = _108_ & _109_;
  assign _115_ = _108_ & _109_;
  assign _116_ = 3'h7 - _167_[113:111];
  assign _117_ = _167_[113:111] == _167_[168:166];
  assign _118_ = _111_ & _117_;
  assign _119_ = 1'h1 - _167_[110];
  assign _120_ = ~ inval_in;
  assign _121_ = _167_[165] & _120_;
  assign _122_ = _126_ ? { _256_, _255_, _254_, _253_ } : _102_;
  assign _123_ = _127_ ? 2'h0 : _103_;
  assign _124_ = _128_ ? 1'h0 : _167_[106];
  assign _125_ = _167_[113:111] + 3'h1;
  assign _126_ = wishbone_in[64] & _118_;
  assign _127_ = wishbone_in[64] & _118_;
  assign _128_ = wishbone_in[64] & _118_;
  assign _129_ = wishbone_in[64] ? { _167_[114], _125_ } : _167_[114:111];
  assign _130_ = wishbone_in[64] ? { _246_, _245_, _244_, _243_, _242_, _241_, _240_, _239_ } : _167_[176:169];
  assign _131_ = _167_[1:0] == 2'h1;
  assign _132_ = _167_[1:0] == 2'h2;
  assign _133_ = _131_ | _132_;
  function [199:0] \8094 ;
    input [199:0] a;
    input [399:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8094  = b[199:0];
      2'b1?:
        \8094  = b[399:200];
      default:
        \8094  = a;
    endcase
  endfunction
  assign _134_ = \8094 (200'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _101_, cache_tags }, { _133_, _090_ });
  function [3:0] \8096 ;
    input [3:0] a;
    input [7:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8096  = b[3:0];
      2'b1?:
        \8096  = b[7:4];
      default:
        \8096  = a;
    endcase
  endfunction
  assign _135_ = \8096 (4'hx, { _122_, _084_ }, { _133_, _090_ });
  function [1:0] \8099 ;
    input [1:0] a;
    input [3:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8099  = b[1:0];
      2'b1?:
        \8099  = b[3:2];
      default:
        \8099  = a;
    endcase
  endfunction
  assign _136_ = \8099 (2'hx, { _123_, _087_[1:0] }, { _133_, _090_ });
  function [31:0] \8102 ;
    input [31:0] a;
    input [63:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8102  = b[31:0];
      2'b1?:
        \8102  = b[63:32];
      default:
        \8102  = a;
    endcase
  endfunction
  assign _137_ = \8102 (32'hxxxxxxxx, { _113_, _087_[33:2] }, { _133_, _090_ });
  function [0:0] \8105 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8105  = b[0:0];
      2'b1?:
        \8105  = b[1:1];
      default:
        \8105  = a;
    endcase
  endfunction
  assign _138_ = \8105 (1'hx, { _124_, _088_[0] }, { _133_, _090_ });
  function [0:0] \8108 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8108  = b[0:0];
      2'b1?:
        \8108  = b[1:1];
      default:
        \8108  = a;
    endcase
  endfunction
  assign _139_ = \8108 (1'hx, { _110_, _088_[1] }, { _133_, _090_ });
  function [0:0] \8111 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8111  = b[0:0];
      2'b1?:
        \8111  = b[1:1];
      default:
        \8111  = a;
    endcase
  endfunction
  assign _140_ = \8111 (1'hx, { _104_, _167_[109] }, { _133_, _090_ });
  function [0:0] \8115 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8115  = b[0:0];
      2'b1?:
        \8115  = b[1:1];
      default:
        \8115  = a;
    endcase
  endfunction
  assign _141_ = \8115 (1'hx, { _167_[110], _089_[0] }, { _133_, _090_ });
  function [3:0] \8118 ;
    input [3:0] a;
    input [7:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8118  = b[3:0];
      2'b1?:
        \8118  = b[7:4];
      default:
        \8118  = a;
    endcase
  endfunction
  assign _142_ = \8118 (4'hx, { _129_, _089_[4:1] }, { _133_, _090_ });
  function [53:0] \8124 ;
    input [53:0] a;
    input [107:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8124  = b[53:0];
      2'b1?:
        \8124  = b[107:54];
      default:
        \8124  = a;
    endcase
  endfunction
  assign _143_ = \8124 (54'hxxxxxxxxxxxxxx, { _167_[168:166], _085_, _167_[164:115], _089_[58:5] }, { _133_, _090_ });
  function [0:0] \8127 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8127  = b[0:0];
      2'b1?:
        \8127  = b[1:1];
      default:
        \8127  = a;
    endcase
  endfunction
  assign _144_ = \8127 (1'hx, { _130_[0], 1'h0 }, { _133_, _090_ });
  function [0:0] \8130 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8130  = b[0:0];
      2'b1?:
        \8130  = b[1:1];
      default:
        \8130  = a;
    endcase
  endfunction
  assign _145_ = \8130 (1'hx, { _130_[1], 1'h0 }, { _133_, _090_ });
  function [0:0] \8133 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8133  = b[0:0];
      2'b1?:
        \8133  = b[1:1];
      default:
        \8133  = a;
    endcase
  endfunction
  assign _146_ = \8133 (1'hx, { _130_[2], 1'h0 }, { _133_, _090_ });
  function [0:0] \8136 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8136  = b[0:0];
      2'b1?:
        \8136  = b[1:1];
      default:
        \8136  = a;
    endcase
  endfunction
  assign _147_ = \8136 (1'hx, { _130_[3], 1'h0 }, { _133_, _090_ });
  function [0:0] \8139 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8139  = b[0:0];
      2'b1?:
        \8139  = b[1:1];
      default:
        \8139  = a;
    endcase
  endfunction
  assign _148_ = \8139 (1'hx, { _130_[4], 1'h0 }, { _133_, _090_ });
  function [0:0] \8142 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8142  = b[0:0];
      2'b1?:
        \8142  = b[1:1];
      default:
        \8142  = a;
    endcase
  endfunction
  assign _149_ = \8142 (1'hx, { _130_[5], 1'h0 }, { _133_, _090_ });
  function [0:0] \8145 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8145  = b[0:0];
      2'b1?:
        \8145  = b[1:1];
      default:
        \8145  = a;
    endcase
  endfunction
  assign _150_ = \8145 (1'hx, { _130_[6], 1'h0 }, { _133_, _090_ });
  function [0:0] \8148 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \8148  = b[0:0];
      2'b1?:
        \8148  = b[1:1];
      default:
        \8148  = a;
    endcase
  endfunction
  assign _151_ = \8148 (1'hx, { _130_[7], 1'h0 }, { _133_, _090_ });
  assign _152_ = rst ? cache_tags : _134_;
  assign _153_ = rst ? 4'h0 : _135_;
  assign _154_ = rst ? 34'h000000000 : { _137_, _136_ };
  assign _155_ = rst ? 72'hff0000000000000000 : _167_[105:34];
  assign _156_ = rst ? 2'h0 : { _139_, _138_ };
  assign _157_ = rst ? 1'h0 : _167_[108];
  assign _158_ = rst ? _167_[176:109] : { _151_, _150_, _149_, _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_ };
  assign _159_ = rst | flush_in;
  assign _160_ = _159_ | m_in[0];
  assign _161_ = ~ access_ok;
  assign _162_ = i_in[0] & _161_;
  assign _163_ = ~ stall_in;
  assign _164_ = _162_ & _163_;
  assign _165_ = _164_ ? 1'h1 : _167_[177];
  assign _166_ = _160_ ? 1'h0 : _165_;
  always @(posedge clk)
    cache_tags <= _152_;
  always @(posedge clk)
    cache_valids <= _153_;
  always @(posedge clk)
    _167_ <= { _166_, _158_, _157_, _156_, _155_, _154_ };
  assign _173_ = ~ _020_[1];
  assign _174_ = ~ _020_[0];
  assign _175_ = _173_ & _174_;
  assign _176_ = _173_ & _020_[0];
  assign _177_ = _020_[1] & _174_;
  assign _178_ = _020_[1] & _020_[0];
  assign _179_ = _175_ ? 1'h0 : itlb_valids[0];
  assign _180_ = _176_ ? 1'h0 : itlb_valids[1];
  assign _181_ = _177_ ? 1'h0 : itlb_valids[2];
  assign _182_ = _178_ ? 1'h0 : itlb_valids[3];
  assign _183_ = ~ _021_[1];
  assign _184_ = ~ _021_[0];
  assign _185_ = _183_ & _184_;
  assign _186_ = _183_ & _021_[0];
  assign _187_ = _021_[1] & _184_;
  assign _188_ = _021_[1] & _021_[0];
  assign _189_ = _185_ ? 1'h1 : itlb_valids[0];
  assign _190_ = _186_ ? 1'h1 : itlb_valids[1];
  assign _191_ = _187_ ? 1'h1 : itlb_valids[2];
  assign _192_ = _188_ ? 1'h1 : itlb_valids[3];
  assign _193_ = _035_ ? cache_valids[2] : cache_valids[0];
  assign _196_ = _041_[2] ? _195_ : _194_;
  assign _197_ = _045_ ? cache_tags[199:100] : cache_tags[99:0];
  assign _198_ = _049_ ? cache_valids[3] : cache_valids[1];
  assign _201_ = _055_[2] ? _200_ : _199_;
  assign _202_ = _059_ ? cache_tags[199:100] : cache_tags[99:0];
  assign _203_ = _071_ ? \maybe_plrus.plrus:0.plru_out  : \maybe_plrus.plrus:1.plru_out ;
  assign _204_ = _072_ ? \rams:0.dout  : \rams:1.dout ;
  assign _205_ = _083_[3] ? _204_[63:32] : _204_[31:0];
  assign _206_ = ~ _092_;
  assign _207_ = ~ replace_way;
  assign _208_ = _206_ & _207_;
  assign _209_ = _206_ & replace_way;
  assign _210_ = _092_ & _207_;
  assign _211_ = _092_ & replace_way;
  assign _212_ = _208_ ? 1'h0 : _084_[0];
  assign _213_ = _209_ ? 1'h0 : _084_[1];
  assign _214_ = _210_ ? 1'h0 : _084_[2];
  assign _215_ = _211_ ? 1'h0 : _084_[3];
  assign _216_ = _094_ ? cache_tags[199:100] : cache_tags[99:0];
  assign _217_ = ~ _095_;
  assign _218_ = _217_ ? { _216_[99:50], _167_[164:115] } : cache_tags[99:0];
  assign _219_ = _095_ ? { _216_[99:50], _167_[164:115] } : cache_tags[199:100];
  assign _220_ = _098_ ? cache_tags[199:100] : cache_tags[99:0];
  assign _221_ = ~ _099_;
  assign _222_ = _221_ ? { _167_[164:115], _220_[49:0] } : _096_[99:0];
  assign _223_ = _099_ ? { _167_[164:115], _220_[49:0] } : _096_[199:100];
  assign _224_ = ~ _116_[2];
  assign _225_ = ~ _116_[1];
  assign _226_ = _224_ & _225_;
  assign _227_ = _224_ & _116_[1];
  assign _228_ = _116_[2] & _225_;
  assign _229_ = _116_[2] & _116_[1];
  assign _230_ = ~ _116_[0];
  assign _231_ = _226_ & _230_;
  assign _232_ = _226_ & _116_[0];
  assign _233_ = _227_ & _230_;
  assign _234_ = _227_ & _116_[0];
  assign _235_ = _228_ & _230_;
  assign _236_ = _228_ & _116_[0];
  assign _237_ = _229_ & _230_;
  assign _238_ = _229_ & _116_[0];
  assign _239_ = _231_ ? 1'h1 : _167_[169];
  assign _240_ = _232_ ? 1'h1 : _167_[170];
  assign _241_ = _233_ ? 1'h1 : _167_[171];
  assign _242_ = _234_ ? 1'h1 : _167_[172];
  assign _243_ = _235_ ? 1'h1 : _167_[173];
  assign _244_ = _236_ ? 1'h1 : _167_[174];
  assign _245_ = _237_ ? 1'h1 : _167_[175];
  assign _246_ = _238_ ? 1'h1 : _167_[176];
  assign _247_ = ~ _119_;
  assign _248_ = ~ replace_way;
  assign _249_ = _247_ & _248_;
  assign _250_ = _247_ & replace_way;
  assign _251_ = _119_ & _248_;
  assign _252_ = _119_ & replace_way;
  assign _253_ = _249_ ? _121_ : _102_[0];
  assign _254_ = _250_ ? _121_ : _102_[1];
  assign _255_ = _251_ ? _121_ : _102_[2];
  assign _256_ = _252_ ? _121_ : _102_[3];
  plru_1 \maybe_plrus.plrus:0.plru  (
    .acc(_083_[0]),
    .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:0.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:1.plru  (
    .acc(_083_[0]),
    .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:1.plru_out ),
    .rst(rst)
  );
  cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:0.way  (
    .clk(clk),
    .rd_addr(i_in[12:9]),
    .rd_data(\rams:0.dout ),
    .rd_en(\rams:0.do_read ),
    .wr_addr(_167_[114:111]),
    .wr_data(\rams:0.wr_dat ),
    .wr_sel({ \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write  })
  );
  cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:1.way  (
    .clk(clk),
    .rd_addr(i_in[12:9]),
    .rd_data(\rams:1.dout ),
    .rd_en(\rams:1.do_read ),
    .wr_addr(_167_[114:111]),
    .wr_data(\rams:1.wr_dat ),
    .wr_sel({ \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write  })
  );
  assign i_out = { _205_, _083_[64:1], _167_[177], _083_[65], _083_[66] };
  assign stall_out = _074_;
  assign wishbone_out = _167_[108:2];
endmodule