- f757546 Merge pull request #15 from ax3ghazy/release by R. Timothy Edwards · 3 years, 7 months ago
- f052d23 Added colors indicating power supplies on the PCB footprint drawing. by Tim Edwards · 3 years, 7 months ago
- 6a0750a Updated the datasheet corresponding to a modified padframe and bump by Tim Edwards · 3 years, 7 months ago
- 2adba10 Fix typos in parameter names by Ahmed Ghazy · 3 years, 7 months ago
- 6d9739d Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 3 years, 7 months ago
- 7ea4895 Fixed sysctrl unit test by Manar · 3 years, 7 months ago
- ba04b40 Allow PDK_PATH to be user-specified by Ahmed Ghazy · 3 years, 7 months ago
- 81d5a89 Move wire declarations before they're first used by Ahmed Ghazy · 3 years, 7 months ago
- 60aeb5f Added a placeholder padframe layout, and added an almost-complete by Tim Edwards · 3 years, 8 months ago
- 49a4ff6 Fixed broken links for dv examples by Mohamed Kassem · 3 years, 8 months ago alpha-1
- 63c933f Removed VCD and hex files, which should not be in the repository. by Tim Edwards · 3 years, 8 months ago
- b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 3 years, 8 months ago
- 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 3 years, 8 months ago
- e2ef673 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 3 years, 8 months ago
- 4c73335 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 3 years, 8 months ago
- 7a8cbb1 Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 3 years, 8 months ago
- 53d9218 Added additional protection for all the signals output to the user by Tim Edwards · 3 years, 8 months ago
- ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 3 years, 8 months ago
- 4286ae1 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 3 years, 8 months ago
- f645a84 Finalized the voltage clamp arrangement and the total number of pads. by Tim Edwards · 3 years, 8 months ago
- 3245e2f Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 3 years, 8 months ago
- 406d37f Solved the trap issue by not driving the PLL clock so fast (not sure why by Tim Edwards · 3 years, 8 months ago
- 9073946 Removed a small error in the PLL testbench C code. However, the by Tim Edwards · 3 years, 8 months ago
- bb3cd69 Added a behavioral model for the ring oscillator, and a testbench by Tim Edwards · 3 years, 8 months ago
- 8115320 Modified code to let SPI master control the housekeeping SPI through by Tim Edwards · 3 years, 8 months ago
- 856b092 Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 3 years, 8 months ago
- b78e1c1 Added management flash SPI pass-through mode testbench and debugged it. by Tim Edwards · 3 years, 8 months ago
- 0c03240 Updated all the testbenches to use the new split power supplies and 37-bit by Tim Edwards · 3 years, 8 months ago
- b3cef09 Removed temporary file. by Tim Edwards · 3 years, 8 months ago
- 5ae07d9 Corrected the error causing the failure of the GPIO testbench. by Tim Edwards · 3 years, 8 months ago
- 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 3 years, 8 months ago
- 0553751 Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 3 years, 8 months ago
- ca2f318 Various corrections to simplify the user project I/O wiring by Tim Edwards · 3 years, 8 months ago
- f51dd08 Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 3 years, 8 months ago
- 89f0924 Made corrections; GPIO testbench now passes. by Tim Edwards · 3 years, 8 months ago
- 251e0df Serial chain loading of the I/O configurations is now working. by Tim Edwards · 3 years, 8 months ago
- 44bab47 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 3 years, 8 months ago
- 61bfc1f Corrected the primary issue with simulation, which was the failure by Tim Edwards · 3 years, 8 months ago
- c18c474 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 3 years, 8 months ago
- 04ba17f Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 3 years, 8 months ago
- 49e2c18 Some minor updates to the testbench Makefiles and verilog. by Tim Edwards · 3 years, 8 months ago
- c5265b8 Corrected some things from the initial pass of removing unused GPIO by Tim Edwards · 3 years, 8 months ago
- ef8312e Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 3 years, 8 months ago
- 12a9a1d Update README.md by Mohamed Shalan · 3 years, 9 months ago
- 49fc489 Update README.md by Mohamed Shalan · 3 years, 9 months ago
- 65a3487 delete not nedded files by shalan · 3 years, 9 months ago
- 0d14e6e harness phase1 initial commit by shalan · 3 years, 9 months ago
- fd13eb5 initial commit by shalan · 3 years, 9 months ago
- cd64af5 Started adding RTL for the Caravel project by Tim Edwards · 3 years, 10 months ago
- 33de054 populated the project with data subfolders. by mkk · 3 years, 10 months ago
- ecdaf58 Initial commit by Mohamed Kassem · 3 years, 10 months ago
