| commit | 9eda80dd074325b1d42354785b1aece24ce83017 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Thu Oct 08 21:36:44 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Thu Oct 08 21:36:44 2020 -0400 |
| tree | 7936f65502d97c97d36a01441a638b9283f0c28f | |
| parent | 055375111fc49797ccf31971f17be971c29b1925 [diff] |
Split the main power supply into managment and two user areas. Mostly put back together again from phase2, although only the gpio testbench has been updated, and the gpio tesbench is currently not passing although most signals seem to be right. Modified the memory map to allow for an additional word in the management I/O GPIO read/write data, and rewrote the code to handle any number of I/Os in the user space, expanding the memory map by one word for every 32 user GPIO pads (there are currently 37 user GPIO pads specified, so this change resolves issues with the upper 5 pads; the last phase2 design defined only 32 user I/O pads).
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: