| commit | 44bab477f9cce5e8229fbd63a16ad84b57663938 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Sun Oct 04 22:09:54 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Sun Oct 04 22:09:54 2020 -0400 |
| tree | 7f48e6862ee2c465e479707de32f424544937b3e | |
| parent | 61bfc1f4c75fbb9a2c915bcd539f7e01c5978a55 [diff] |
In spite of many errors that still need fixing, this is a major advance over the previous commit. All verilog modules are in place more or less as intended, with various functions such as the housekeeping SPI placed on user area pads, with the ability to switch to user control from the configuration. The pad control bits are local to the pads and loaded via serial shift register, so that there are not hundreds of control wires feeding into the user space. The user has three basic controls over each pad: in, out, and outenb. Two timer/counters and an SPI master have been added to the SoC. The SPI master shares I/O with the housekeeping SPI, so that all housekeeping SPI registers can be accessed from the SoC directly.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: