blob: 924a52c2904fc0ed16765f105df944b00b058368 [file] [log] [blame]
module mega_project #(
parameter IO_PADS = 32,
parameter BITS = 32
)(
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,
// IOs
input [IO_PADS-1:0] io_in,
output [IO_PADS-1:0] io_out
);
wire clk;
wire rst;
wire [31:0] rdata;
wire [31:0] wdata;
wire [BITS-1:0] count;
wire valid;
wire [3:0] wstrb;
wire [31:0] la_write;
// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;
// IO
assign io_out = count;
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
// Assuming LA probes [63:32] are for controlling the count register
assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
counter #(
.BITS(BITS)
) counter(
.clk(clk),
.reset(rst),
.ready(wbs_ack_i),
.valid(valid),
.rdata(rdata),
.wdata(wbs_dat_i),
.wstrb(wstrb),
.la_write(la_write),
.la_input(la_data_in[63:32]),
.count(count)
);
endmodule
module counter #(
parameter BITS = 32
)(
input clk,
input reset,
input valid,
input [3:0] wstrb,
input [BITS-1:0] wdata,
input [BITS-1:0] la_write,
input [BITS-1:0] la_input,
output ready,
output [BITS-1:0] rdata,
output [BITS-1:0] count
);
reg ready;
reg [BITS-1:0] count;
reg [BITS-1:0] rdata;
always @(posedge clk) begin
if (reset) begin
count <= 0;
ready <= 0;
end else begin
ready <= 1'b0;
if (~|la_write) begin
count <= count + 1;
end
if (valid && !ready) begin
ready <= 1'b1;
rdata <= count;
if (wstrb[0]) count[7:0] <= wdata[7:0];
if (wstrb[1]) count[15:8] <= wdata[15:8];
if (wstrb[2]) count[23:16] <= wdata[23:16];
if (wstrb[3]) count[31:24] <= wdata[31:24];
end
end
end
genvar i;
generate
for(i=0; i<BITS; i=i+1) begin
always @(posedge clk) begin
if (la_write[i]) count[i] <= la_input[i];
end
end
endgenerate
endmodule