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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-019 / f51dd08a1f4716df0cca0a0ebe28f99544cc611c / . / verilog / dv / caravel / defs.h
blob: ac5dfdf81f9355c5525cf7e13e058d0457e99c25 [file] [log] [blame]
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]1#ifndef _STRIVE_H_
2#define _STRIVE_H_
3
4#include <stdint.h>
5#include <stdbool.h>
6
7// a pointer to this is a null pointer, but the compiler does not
8// know that because "sram" is a linker symbol from sections.lds.
9extern uint32_t sram;
10
11// Pointer to firmware flash routines
12extern uint32_t flashio_worker_begin;
13extern uint32_t flashio_worker_end;
14
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]15// UART (0x2000_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]16#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
17#define reg_uart_data (*(volatile uint32_t*)0x20000004)
18
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]19// GPIO (0x2100_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]20#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
21#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
22#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
23#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
24
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]25// Logic Analyzer (0x2200_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]26#define reg_la0_data (*(volatile uint32_t*)0x22000000)
27#define reg_la1_data (*(volatile uint32_t*)0x22000004)
28#define reg_la2_data (*(volatile uint32_t*)0x22000008)
29#define reg_la3_data (*(volatile uint32_t*)0x2200000c)
30
31#define reg_la0_ena (*(volatile uint32_t*)0x22000010)
32#define reg_la1_ena (*(volatile uint32_t*)0x22000014)
33#define reg_la2_ena (*(volatile uint32_t*)0x22000018)
34#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
35
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]36// Mega Project Control (0x2300_0000)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]37#define reg_mprj_data (*(volatile uint32_t*)0x23000000)
38#define reg_mprj_xfer (*(volatile uint32_t*)0x23000004)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]39
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]40#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000008)
41#define reg_mprj_io_1 (*(volatile uint32_t*)0x2300000c)
42#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000010)
43#define reg_mprj_io_3 (*(volatile uint32_t*)0x23000014)
44#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000018)
45#define reg_mprj_io_5 (*(volatile uint32_t*)0x2300001c)
46#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000020)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]47
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]48#define reg_mprj_io_7 (*(volatile uint32_t*)0x23000024)
49#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000028)
50#define reg_mprj_io_9 (*(volatile uint32_t*)0x2300002c)
51#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000030)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]52
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]53#define reg_mprj_io_11 (*(volatile uint32_t*)0x23000034)
54#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000038)
55#define reg_mprj_io_13 (*(volatile uint32_t*)0x2300003c)
56#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000040)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]57
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]58#define reg_mprj_io_15 (*(volatile uint32_t*)0x23000044)
59#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000048)
60#define reg_mprj_io_17 (*(volatile uint32_t*)0x2300004c)
61#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000050)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]62
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]63#define reg_mprj_io_19 (*(volatile uint32_t*)0x23000054)
64#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000058)
65#define reg_mprj_io_21 (*(volatile uint32_t*)0x2300005c)
66#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000060)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]67
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]68#define reg_mprj_io_23 (*(volatile uint32_t*)0x23000064)
69#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000068)
70#define reg_mprj_io_25 (*(volatile uint32_t*)0x2300006c)
71#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000070)
72
73#define reg_mprj_io_27 (*(volatile uint32_t*)0x23000074)
74#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000078)
75#define reg_mprj_io_29 (*(volatile uint32_t*)0x2300007c)
76#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000080)
77#define reg_mprj_io_31 (*(volatile uint32_t*)0x23000084)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]78
79// Mega Project Slaves (0x3000_0000)
80#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
81
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]82// Flash Control SPI Configuration (2D00_0000)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]83#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]84
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]85// Counter-Timer 0 Configuration
86#define reg_timer0_config (*(volatile uint32_t*)0x21100000)
87#define reg_timer0_value (*(volatile uint32_t*)0x21100004)
88#define reg_timer0_data (*(volatile uint32_t*)0x21100008)
89
90// Counter-Timer 1 Configuration
91#define reg_timer1_config (*(volatile uint32_t*)0x21200000)
92#define reg_timer1_value (*(volatile uint32_t*)0x21200004)
93#define reg_timer1_data (*(volatile uint32_t*)0x21200008)
94
95// SPI Master Configuration
96#define reg_spimaster_config (*(volatile uint32_t*)0x21300000)
97#define reg_spimaster_data (*(volatile uint32_t*)0x21300004)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]98
99// System Area (0x2F00_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]100#define reg_pll_out_dest (*(volatile uint32_t*)0x2F00000c)
101#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000010)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]102#define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
103#define reg_irq8_source (*(volatile uint32_t*)0x2F000018)
104
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]105// Crossbar Slave Addresses (0x8000_0000 - 0xB000_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]106#define qspi_ctrl_slave (*(volatile uint32_t*)0x80000000)
107#define storage_area_slave (*(volatile uint32_t*)0x90000000)
108#define mega_any_slave1 (*(volatile uint32_t*)0xA0000000)
109#define mega_any_slave2 (*(volatile uint32_t*)0xB0000000)
110
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]111// Useful GPIO mode values
112#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
113#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
114#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
Tim Edwardsf51dd082020-10-05 16:30:24 -0400[diff] [blame^]115#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]116
117#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
118#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
119#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
Tim Edwardsf51dd082020-10-05 16:30:24 -0400[diff] [blame^]120#define GPIO_MODE_USER_STD_OUTPUT 0x1808
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]121
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]122// --------------------------------------------------------
123#endif